S93C86B

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www.sii-ic.com FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM © Seiko Instruments Inc., 2009-2015 Rev.2.1 _00 Seiko Instruments Inc. 1 The S-93C86B H Series is a high tem perature operation 3-wire serial E 2PROM for automotive co mponents. The S-93C86B H Series has the capacity of 16 K-bit, and the organization is 1024-word × 16-bit. It is capable of s equential read, at which time addresses are automatically incremented in 16-bit blocks. The communication method is by the Microwire bus.  Features

• Operating voltage range: R ead 2.7 V to 5.5 V (Ta = −40°C to +105°C) Write 2.7 V to 5.5 V (Ta = − 40°C to +105°C)
• Operation frequency: 1.0 MHz (VCC = 4.5 V to 5.5 V, Ta = −40°C to +105°C)
• Write time: 4.0 ms max.
• Sequential read capable
• Write protect function during the low power supply voltage
• Function to protect against write due to erroneous instruction recognition
• Endurance: 106 cycles/word*1 (Ta = +85°C) 5 × 105 cycles/word*1 (Ta = +105°C)
• Data retention: 100 years (Ta = +25°C) 20 years (Ta = +105°C)
• Memory capacity: 16 K-bit
• Initial delivery state: FFFFh
• Operation temperature range: Ta = −40°C to +105°C
• Lead-free (Sn 100%), halogen-free*2 *1. For each address (Word: 16-bit) *2. Refer to “ Product Name Structure” for details.  Packages
• 8-Pin SOP (JEDEC)
• 8-Pin TSSOP Caution Before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to SII is indispensable.

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM S-93C86B H Series Rev.2.1_00 Seiko Instruments Inc. 2  Pin Configurations 8-Pin SOP(JEDEC) Top view Table 1 VCC NC TEST GND CS SK DO DI Figure 1 S-93C86BD4H-J8T2U Pin No. Symbol Description

1 CS Chip select input

2 SK Serial clock input

3 DI Serial data input

4 DO Serial data output

5 GND Ground

6 TEST*1 Test

7 NC No connection

8 VCC Power supply

*1. Connect to GND or V CC. Even if this pin is not connected, performance is not affected so long as the absolute maximum rating is not exceeded. 8-Pin TSSOP Top view Table 2 VCC NC TEST GND CS SK DO DI Figure 2 S-93C86BD4H-T8T2U Pin No. Symbol Description *1. Connect to GND or V CC. Even if this pin is not connected, performance is not affected so long as the absolute maximum rating is not exceeded. Remark See Dimensions for details of the package drawings.

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM Rev.2.1_00 S-93C86B H Series Seiko Instruments Inc. 3  Block Diagram Memory array Data register Address decoder Mode decode logic Clock pulse monitoring circuit Output buffer VCC GND DO DI CS Clock generator Voltage detector SK Figure 3

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM S-93C86B H Series Rev.2.1_00 Seiko Instruments Inc. 4  Instruction Sets Table 3 Instruction Start Bit Operation Code Address Data SK input clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 to 29 READ (Read data) 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 Output*1 WRITE (Write data) 1 0 1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 Input ERASE (Erase data) 1 1 1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ⎯ WRAL (Write all) 1 0 0 0 1 x x x x x x x x D15 to D0 Input ERAL (Erase all) 1 0 0 1 0 x x x x x x x x ⎯ EWEN (Write enable) 1 0 0 1 1 x x x x x x x x ⎯ EWDS (Write disable) 1 0 0 0 0 x x x x x x x x ⎯ *1. When the 16-bit data in the specified address has been output, the dat a in the next address is output. Remark x: Don’t care

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM Rev.2.1_00 S-93C86B H Series Seiko Instruments Inc. 5  Absolute Maximum Ratings Table 4 Item Symbol Ratings Unit Power supply voltage VCC −0.3 to +7.0 V Input voltage VIN −0.3 to VCC +0.3 V Output voltage VOUT −0.3 to VCC V Operating ambient temperature T opr −40 to +105 ° C Storage temperature Tstg −65 to +150 °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions.  Recommended Operating Conditions Table 5 Item Symbol Conditions −40 to +85°C +85 to +105°C UnitMin. Max. Min. Max. Power supply voltage V CC READ, EWDS 1.8 5.5 2.7 5.5 V WRITE, ERASE, EWEN 2.7 5.5 2.7 5.5 V WRAL, ERAL 2.7 5.5 4.5 5.5 V High level input voltage V IH VCC = 4.5 to 5.5 V 2.0 V CC 2.0 V CC V VCC = 2.7 to 4.5 V 0.8 × VCC VCC 0.8 × VCC V CC V VCC = 1.8 to 2.7 V 0.8 × VCC VCC ⎯ ⎯ V Low level input voltage V IL VCC = 1.8 to 2.7 V 0.0 0.15 × VCC ⎯ ⎯ V  Pin Capacitance Table 6 (Ta = 25°C, f = 1.0 MHz, VCC = 5.0 V) Item Symbol Conditions Min. Max. Unit Input Capacitance CIN VIN = 0 V ⎯ 8 pF Output Capacitance COUT VOUT = 0 V ⎯ 10 pF  Endurance Table 7 Item Symbol Operating Ambient Temperature Min. Max. Unit Endurance N W −40 to +85°C 10 6 ⎯ cycles/word*1 +85 to +105°C 5 × 105 ⎯ cycles/word*1 *1. For each address (Word: 16 bits)  Data Retention Table 8 Item Symbol Operating Ambient Temperature Min. Max. Unit Data Retention ⎯ +25°C 100 ⎯ year −40 to +105°C 20 ⎯ year

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM S-93C86B H Series Rev.2.1_00 Seiko Instruments Inc. 6  DC Electrical Characteristics Table 9 (1/2) Item Symbol Conditions −40 to +85°C Current consumption (READ) ICC1 DO no load ⎯ 0.8 ⎯ 0.5 ⎯ 0.4 mA Table 9 (2/2) Item Symbol Conditions +85 to +105°C UnitVCC = 4.5 to 5.5 V VCC = 2.7 to 4.5 V Min. Max. Min. Max. Current consumption (READ) I CC1 DO no load ⎯ 0.8 ⎯ 0.5 mA Table 10 (1/2) Item Symbol Conditions −40 to +85°C UnitVCC = 4.5 to 5.5 V VCC = 2.7 to 4.5 V Min. Max. Min. Max. Current consumption (WRITE) I CC2 DO no load ⎯ 2.0 ⎯ 1.5 mA Table 10 (2/2) Item Symbol Conditions +85 to +105°C UnitVCC = 2.7 to 5.5 V Min. Max. Current consumption (WRITE) I CC2 DO no load ⎯ 2.0 mA

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM Rev.2.1_00 S-93C86B H Series Seiko Instruments Inc. 7 Table 11 (1/2) Item Symbol Conditions −40 to +85°C Standby current consumption ISB CS = GND, DO = Open, Other inputs to V CC or GND Input leakage current I LI VIN = GND to VCC ⎯ 1.0 ⎯ 1.0 ⎯ 1.0 μA Output leakage current I LO V OUT = GND to VCC ⎯ 1.0 ⎯ 1.0 ⎯ 1.0 μA Low level output voltage V OL IOL = 2.1 mA ⎯ 0.4 ⎯ ⎯ ⎯ ⎯ V IOL = 100 μA ⎯ 0.1 ⎯ 0.1 ⎯ 0.1 V High level output voltage VOH IOH = −100 μA V CC− 0.3 ⎯ V CC− 0.3 ⎯ ⎯ ⎯ V IOH = −10 μA V CC− 0.2 ⎯ V CC− 0.2 ⎯ V CC− 0.2 ⎯ V Data hold voltage of write enable latch V DH Only program disable mode 1.5 ⎯ 1.5 ⎯ 1.5 ⎯ V Table 11 (2/2) Item Symbol Conditions +85 to +105°C UnitVCC = 4.5 to 5.5 V VCC = 2.7 to 4.5 V Min. Max. Min. Max. Standby current consumption I SB CS = GND, DO = Open, Other inputs to V CC or GND ⎯ 2.0 ⎯ 2.0 μA Input leakage current I LI VIN = GND to VCC ⎯ 1.0 ⎯ 1.0 μA Output leakage current I LO V OUT = GND to VCC ⎯ 1.0 ⎯ 1.0 μA Low level output voltage V OL IOL = 2.1 mA ⎯ 0.4 ⎯ ⎯ V IOL = 100 μA ⎯ 0.1 ⎯ 0.1 V High level output voltage VOH IOH = −400 μA 2.4 ⎯ ⎯ ⎯ V IOH = −100 μA V CC− 0.3 ⎯ V CC− 0.3 ⎯ V IOH = −10 μA V CC− 0.2 ⎯ V CC− 0.2 ⎯ V Data hold voltage of write enable latch V DH Only program disable mode 1.5 ⎯ 1.5 ⎯ V

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM S-93C86B H Series Rev.2.1_00 Seiko Instruments Inc. 8  AC Electrical Characteristics Table 12 Measurement Conditions Input pulse voltage 0.1 × VCC to 0.9 × VCC Output reference voltage 0.5 × VCC Output load 100 pF Table 13 (1/2) Item Symbol −40 to +85°C CS setup time tCSS 0.2 ⎯ 0.4 ⎯ 1.0 ⎯ μs CS hold time tCSH 0 ⎯ 0 ⎯ 0 ⎯ μs CS deselect time t CDS 0.2 ⎯ 0.2 ⎯ 0.4 ⎯ μs Data setup time tDS 0.1 ⎯ 0.2 ⎯ 0.4 ⎯ μs Data hold time tDH 0.1 ⎯ 0.2 ⎯ 0.4 ⎯ μs Output delay time t PD ⎯ 0.4 ⎯ 0.8 ⎯ 2.0 μs Clock frequency*1 fSK 0 2.0 0 0.5 0 0.25 MHz SK clock time “L” *1 tSKL 0.1 ⎯ 0.5 ⎯ 1.0 ⎯ μs SK clock time “H” *1 tSKH 0.1 ⎯ 0.5 ⎯ 1.0 ⎯ μs Output disable time t HZ1, tHZ2 0 0.15 0 0.5 0 1.0 μs Output enable time t SV 0 0.15 0 0.5 0 1.0 μs Table 13 (2/2) Item Symbol +85 to +105°C UnitVCC = 4.5 to 5.5 V VCC = 2.7 to 4.5 V Min. Max. Min. Max. CS setup time tCSS 0.2 ⎯ 0.4 ⎯ μs CS hold time tCSH 0 ⎯ 0 ⎯ μs CS deselect time t CDS 0.2 ⎯ 0.2 ⎯ μs Data setup time tDS 0.1 ⎯ 0.2 ⎯ μs Data hold time tDH 0.1 ⎯ 0.2 ⎯ μs Output delay time t PD ⎯ 0.6 ⎯ 0.8 μs Clock frequency*1 fSK 0 1.0 0 0.5 MHz SK clock time “L” *1 tSKL 0.25 ⎯ 0.5 ⎯ μs SK clock time “H” *1 tSKH 0.25 ⎯ 0.5 ⎯ μs Output disable time t HZ1, tHZ2 0 0.15 0 0.5 μs Output enable time t SV 0 0.15 0 0.5 μs *1. The clock cycle of the SK clock (frequency: f SK) is 1/fSK μs. This clock cycle is determined by a combination of several AC characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle (1/fSK) cannot be made to equal tSKL(Min.) + tSKH(Min.).

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM Rev.2.1_00 S-93C86B H Series Seiko Instruments Inc. 9 Table 14 Item Symbol −40 to +85°C +85 to +105°C UnitVCC = 2.7 to 5.5 V V CC = 4.5 to 5.5 V Write time tPR ⎯ 2.0 4.0 ⎯ 2.0 4.0 ms tSKH tCDS tCSS CS Valid data DI tSKL SK tSV tHZ2 tCSH tHZ1 tPD tPD tDS tDH tDS tDH High-Z High-Z High-Z DO DO (READ) (VERIFY) High-Z*1 Valid data 1/fSK *1. Indicates high impedance. *2. 1 / fSK is the SK clock cycle. This clock cycle is determined by a combination of several AC characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle (1/fSK) cannot be made to equal tSKL(Min.) + tSKH(Min.). Figure 4 Timing Chart  Initial Delivery State Initial delivery state of all addresses is "FFFFh".

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM S-93C86B H Series Rev.2.1_00 Seiko Instruments Inc. 10  Operation All instructions are executed by inpu tting DI in synchronization with the rising edge of SK after CS goes high. An instruction set is input in the order of start bit, instruction, address, and data. Instruction input finishes when CS goes low. A lo w level must be input to CS between commands during t CDS. While a low level is being input to CS, the S-93C86B is in standby mode, so the SK and DI inputs ar e invalid and no instructions are allowed.  Start Bit A start bit is recognized when the DI pin goes high at the rise of SK after CS goes hi gh. After CS goes high, a start bit is not recognized even if the SK pulse is input as long as the DI pin is low. 1. Dummy clock SK clocks input while the DI pin is lo w before a start bit is input are called dummy clocks. Dummy clocks are effective when aligning the number of inst ruction sets (clocks) sent by the CPU with those required for serial memory operation. For example, when a CPU in struction set is 16 bits, the number of instruction set clocks can be adjusted by inserting a 3-bit dummy clock for the S-93C86B. 2. Start bit input failure

• When the output status of the DO pin is high during the verify period after a write operation, if a high level is input to the DI pin at the rising edge of SK, the S-93C86B recognize s that a start bit has been input. To prevent this failure, input a low level to the DI pin during the verify operation period (refer to “4.1 Verify operation”).
• When a 3-wire interface is configur ed by connecting the DI input pin and DO output pin, a period in which the data output from the CPU and the serial me mory collide may be generated, preventing successful input of the start bit. Take the measures described in “ 3-Wire Interface (Direct Connection between DI and DO)”.

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM Rev.2.1_00 S-93C86B H Series Seiko Instruments Inc. 11 3. Reading (READ) The READ instruction reads data from a specified address. After CS has gone high, input an instruction in the order of the start bit, read instruction, and address. Since the last input address (A0) has been latched, the output status of the DO pin changes fr om high impedance (High-Z) to low, which is held until the next rise of SK. 16-bit data starts to be output in synchronization with the next rise of SK.

3.1 Sequential read

After the 16-bit data at the specif ied address has been output, inputting SK while CS is high automatically increments the address, and causes the 16-bit data at the next address to be out put sequentially. The above method makes it possible to read the data in the whole memory space. The last address (A 9  A 1 A0 = 1  1 1) rolls over to the top address (A9  A 1 A0 = 0  0 0). SK D13 D15 0 D14 D14 D13 D0 D1 D2 D15 D14 D0 D1 D2 D13 D15 43 42 45 46 44 30 29 28 27 26 A5 A6 A7 A2 A3 A4 DI 13 11 10 9 8 7 6 5 4 3 2 1 12 CS DO 47 31 14 High-Z ADRINC High-Z 0 1 <1> ADRINC A9 A0 A1 15 16 Figure 5 Read Timing

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM S-93C86B H Series Rev.2.1_00 Seiko Instruments Inc. 12 4. Writing (WRITE, ERASE, WRAL, ERAL) A write operation includes four write instructions: data wr ite (WRITE), data erase (ER ASE), chip write (WRAL), and chip erase (ERAL). A write instruction (WRITE, ERASE, WRAL, ERAL) starts a write operation to the memory cell when a low level is input to CS after a specified number of clocks have been input. The SK and DI inputs are invalid during the write period, so do not input an instruction. Input an instruction while the output status of the DO pin is high or high impedance (High-Z). A write operation is valid only in program enable mode (refer to “ 5. Write enable (EWEN) and write disable (EWDS)”).

4.1 Verify operation

A write operation executed by any instruction is completed within 4 ms (write time t PR: typically 2 ms), so if the completion of the write operation is recognized, the write cycle can be mi nimized. A sequential operation to confirm the status of a write operation is called a verify operation. (1) Operation After the write operation has started (CS = low), the status of the wr ite operation can be verified by confirming the output status of the DO pin by inputting a high leve l to CS again. This sequence is called a verify operation, and the period that a high level is input to the CS pi n after the write operation has started is called the verify operation period. The relationship between the output st atus of the DO pin and the write operation during the verify operation period is as follows.

• DO pin = low: Writing in progress (busy)
• DO pin = high: Writing completed (ready) (2) Operation example There are two methods to perform a verify operation: Waiting for a change in the output status of the DO pin while keeping CS high, or su spending the verify operation (CS = low) once and then performing it again to verify the output status of t he DO pin. The latter method allows the CPU to perform other processing during the wait period, allowing an efficient system to be designed. Caution 1. Input a low level to the DI pin during a verify operation. 2. If a high level is input to the DI pin at the rise of SK when the output status of the DO pin is high, the S-93C86B latches the instruction assuming that a start bit has been input. In this case, note that the DO pin immediately enters a high-impedance (High-Z) state.

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM Rev.2.1_00 S-93C86B H Series Seiko Instruments Inc. 13

4.2 Writing data (WRITE)

To write 16-bit data to a specified address, change CS to high and then input the WRITE instruction, address, and 16-bit data following the start bit. The write operation starts when CS goes low. There is no need to set the data to 1 before writi ng. When the clocks more than the specified number have been input, the clock pulse monitoring circuit cancels the WRITE instruction. For det ails of the clock pulse monitoring circuit, refer to “  Function to Protect Against Write due to Erroneous Instruction Recognition”. A9 D15 <1> 1 2 3 4 5 6 7 8 9 10 11 0 1 A8 A7 A6 A5 A4 A3 A2 CS SK DI DO High-Z ready busy tPR tSV tCDS 2914 High-Z Verify Standby tHZ1 12 13 A1 A0 Figure 6 Data Write Timing

4.3 Erasing data (ERASE)

To erase 16-bit data at a specified address, set all 16 bits of the data to 1, change CS to high, and then input the ERASE instruction and address following the start bit. There is no need to input data. The data erase operation starts when CS goes low. When the clocks more than the specified number have been input, the clock pulse monitoring circuit cancels the ERASE instruction. For details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction Recognition”. SK DI <1> A8 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 CS DO High-Z 1 1 ready tCDS tSV High-Z tHZ1 tPR A1 A0 12 13 busy Verify Standby A3 A2 10 11 Figure 7 Data Erase Timing

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM S-93C86B H Series Rev.2.1_00 Seiko Instruments Inc. 14

4.4 Writing to chip (WRAL)

To write the same 16-bit data to the entire memory address space, change CS to high, and then input the WRAL instruction, an address, and 16-bit dat a following the start bit. Any addre ss can be input. The write operation starts when CS goes low. There is no need to set the dat a to 1 before writing. W hen the clocks more than the specified number been input, the clock pulse monitoring circui t cancels the WRAL instruction. For details of the clock pulse monitoring circuit, refer to “  Function to Protect Against Write due to Erroneous Instruction Recognition”. 2 3 4 5 6 7 8 9 101 SK DI CS DO High-Z <1> 0 0 0 1 8Xs Verify tCDS tSV tHZ1 High-ZtPR busy Standby 13 14 29 ready D15 11 12 Figure 8 Chip Write Timing

4.5 Erasing chip (ERAL)

To erase the data of the ent ire memory address space, set all the dat a to 1, change CS to high, and then input the ERAL instruction and an address following the start bit. Any address can be input. There is no need to input data. The chips er ase operation starts when CS goes low. When the clocks more than the specified number have been input, the clock pulse monitoring circuit c ancels the ERAL instructi on. For details of the clock pulse monitoring circuit, refer to “  Function to Protect Against Write due to Erroneous Instruction Recognition”. 76 5 4 3 2 1 9 8 CS SK DI DO 8Xs 0 1 0 <1> 0 tCDS tSV ready busy tHZ1 High-Z tPR StandbyVerify 1211 10 High-Z Figure 9 Chip Erase Timing

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM Rev.2.1_00 S-93C86B H Series Seiko Instruments Inc. 15 5. Write enable (EWEN) and write disable (EWDS) The EWEN instruction is an instructi on that enables a write operat ion. The status in wh ich a write operation is enabled is called the program enable mode. The EWDS instruction is an instruction that disables a write oper ation. The status in which a write operation is disabled is called the program disable mode. After CS goes high, input an instructi on in the order of the start bit, EW EN or EWDS instruction, and address (optional). Each mode becomes valid by inputting a low le vel to CS after the last address (optional) has been input. DI SK 6 54 3 21 9 8 7 CS 8Xs11 = EWEN 00 = EWDS 0<1> 0 13 12 Standby 1110 Figure 10 Write Enable/Disable Timing (1) Recommendation for write operation disable instruction It is recommended to implement a design that prevents an incorrect write operation when a write instruction is erroneously recognized by executing t he write operation disable instruction when executing inst ructions other than write instruction, and immediately after power-on and before power off.

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM Rev.2.1_00 S-93C86B H Series Seiko Instruments Inc. 17  Function to Protect Against Write due to Erroneous Instruction Recognition The S-93C86B provides a built-in clock pulse monitoring circ uit which is used to prevent an erroneous write operation by canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized erroneously due to an erroneous clock count caused by the application of noise pulses or double counting of clocks. Instructions are cancelled if a clock pulse whose count other t han the one specified for each write instruction (WRITE, ERASE, WRAL, or ERAL) is detected. <Example> Erroneous recognition of program disable instruction (EWDS) as erase instruction (ERASE) Input EWDS instruction Erroneous recognition as ERASE instruction due to noise pulse Noise pulse Example of S-93C86B In products that do not incor porate a clock pulse monitori ng circuit, FFFF is mistakenly written to address 00h. However the S-93C86B detects the over count and cancels the instruction without performing a write operation. CS SK DI 1 3 4 5 6 7 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 10 11 0 0 0 0 1 0 1 8 9 0 0 0 0 12 13 Figure 12 Example of Clock Pulse Monitoring Circuit Operation

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM S-93C86B H Series Rev.2.1_00 Seiko Instruments Inc. 18  3-Wire Interface (Direct Connection between DI and DO) There are two types of serial interface configurations: a 4-wire interface conf igured using the CS, SK, DI, and DO pins, and a 3-wire interface that connects the DI input pin and DO output pin. When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI and DO pins of the S- 93C86B via a resistor (10 to 100 k Ω) so that the data output fr om the CPU takes precedence in being input to the DI pin (refer to “Figure 13 Connection of 3-Wire Interface ”). CPU S-93C86B R: 10 to 100 kΩ DI DO SIO Figure 13 Connection of 3-Wire Interface  I/O Pin 1. Connection of input pins All the input pins of the S- 93C86B employ a CMOS structure, so design the equipment so that high impedance will not be input while the S-93C86B is oper ating. Especially, deselect the CS input (a low level) when turning on/off power and during standby. When the CS pin is deselect ed (a low level), incorrect data writing will not occur. Connect the CS pin to GND via a resistor (10 to 100 k Ω pull-down resistor). To prevent malfuncti on, it is recommended to use equivalent pull- down resistors for pins other than the CS pin. 2. Equivalent circuit of input and output pin The following shows the equivalent circuits of input pins of the S-93C86B. None of the input pins incorporate pull-up and pull-down elements, so special care must be taken when designing to prevent a floating status. Output pins are high-level/low-level/high-impedance tri-state out puts. The TEST pin is di sconnected from the internal circuit by a switching transistor during no rmal operation. As long as the absolute maximum rating is satisfied, the TEST pin and internal circuit will never be connected.

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM Rev.2.1_00 S-93C86B H Series Seiko Instruments Inc. 19

2.1 Input pin

SK, DI Figure 15 SK, DI Pin TEST Figure 16 TEST Pin

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM S-93C86B H Series Rev.2.1_00 Seiko Instruments Inc. 20

2.2 Output pin

1. Input pin noise elimination time The S-93C86B includes a built-in low-pass filt er to eliminate noise at the SK, DI, and CS pins. This means that if the supply voltage is 5.0 V (at room temperature), noise with a pulse width of 20 ns or less can be eliminated. Note, therefore, that noise with a pul se width of more than 20 ns will be rec ognized as a pulse if the voltage exceeds VIH/VIL.  Precaution

• Do not apply an electrostatic discharge to this IC that ex ceeds the performance ratings of the built-in electrostatic protection circuit.
• SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of the products including this IC upon patents owned by a third party.

FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM Rev.2.1_00 S-93C86B H Series Seiko Instruments Inc. 21  Product Name Structure 1. Product name S-93C86B D 4 H - xxxx U Environmental code U: Lead-free (Sn 100%), halogen-free Package name (abbreviation) and IC packing specifications J8T2: 8-Pin SOP (JEDEC), Tape T8T2: 8-Pin TSSOP, Tape Operation temperature H: −40 to +105°C Fixed Product name S-93C86B: 16 K-bit Remark Please contact our sales office for products with product name structure other than those specified above. 2. Package Package name Drawing code Package Tape Reel 8-Pin SOP (JEDEC) FJ008-A-P-SD FJ008-D-C-SD FJ008-D-R-SD 8-Pin TSSOP FT008-A-P-SD FT008-E-C-SD FT008-E-R-SD

/X4E/X6F/X2E/X20/X46/X4A/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X32/X2E/X31 /X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54 /X6D/X6D /X53/X4F/X50/X38/X4A/X2D/X44/X2D/X50/X4B/X47/X20/X44/X69/X6D/X65/X6E/X73/X69/X6F/X6E/X73 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /X46/X4A/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X32/X2E/X31 /X30/X2E/X34/XB1/X30/X2E/X30/X35/X31/X2E/X32/X37 /X30/X2E/X32/X30/XB1/X30/X2E/X30/X35 /X35/X2E/X30/X32/XB1/X30/X2E/X32 /X31 /X34 /X38/X35

/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54 /X6D/X6D /X35 /X38/X31 /X34 /XF8/X32/X2E/X30/XB1/X30/X2E/X30/X35 /XF8/X31/X2E/X35/X35/XB1/X30/X2E/X30/X35 /X30/X2E/X33/XB1/X30/X2E/X30/X35 /X32/X2E/X31/XB1/X30/X2E/X31/X38/X2E/X30/XB1/X30/X2E/X31 /X35/XB0/X6D/X61/X78/X2E /X36/X2E/X37/XB1/X30/X2E/X31 /X32/X2E/X30/XB1/X30/X2E/X30/X35 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /X46/X65/X65/X64/X20/X64/X69/X72/X65/X63/X74/X69/X6F/X6E /X34/X2E/X30/XB1/X30/X2E/X31/X28/X31/X30/X20/X70/X69/X74/X63/X68/X65/X73/X3A/X34/X30/X2E/X30/XB1/X30/X2E/X32/X29 /X53/X4F/X50/X38/X4A/X2D/X44/X2D/X43/X61/X72/X72/X69/X65/X72/X20/X54/X61/X70/X65 /X4E/X6F/X2E/X20/X46/X4A/X30/X30/X38/X2D/X44/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X31 /X46/X4A/X30/X30/X38/X2D/X44/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X31

/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54/X6D/X6D /X51/X54/X59/X2E/X32/X2C/X30/X30/X30 /X32/XB1/X30/X2E/X35 /X31/X33/X2E/X35/XB1/X30/X2E/X35 /X36/X30/XB0 /X32/XB1/X30/X2E/X35 /XF8/X31/X33/XB1/X30/X2E/X32 /XF8/X32/X31/XB1/X30/X2E/X38 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /X45/X6E/X6C/X61/X72/X67/X65/X64/X20/X64/X72/X61/X77/X69/X6E/X67/X20/X69/X6E/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X72/X61/X6C/X20/X70/X61/X72/X74 /X53/X4F/X50/X38/X4A/X2D/X44/X2D/X52/X65/X65/X6C /X4E/X6F/X2E/X20/X46/X4A/X30/X30/X38/X2D/X44/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X31 /X46/X4A/X30/X30/X38/X2D/X44/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X31

/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /X54/X53/X53/X4F/X50/X38/X2D/X45/X2D/X50/X4B/X47/X20/X44/X69/X6D/X65/X6E/X73/X69/X6F/X6E/X73 /X4E/X6F/X2E/X20/X46/X54/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X31/X2E/X31 /X46/X54/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X31/X2E/X31 /X30/X2E/X31/X37/XB1/X30/X2E/X30/X35 /X33/X2E/X30/X30/X2B/X30/X2E/X33 /X20/X2D/X30/X2E/X32 /X30/X2E/X36/X35 /X30/X2E/X32/XB1/X30/X2E/X31 /X31 /X34 /X35/X38 /X6D/X6D

/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /XF8/X31/X2E/X35/X35/XB1/X30/X2E/X30/X35 /X32/X2E/X30/XB1/X30/X2E/X30/X35 /X38/X2E/X30/XB1/X30/X2E/X31/XF8/X31/X2E/X35/X35/X2B/X30/X2E/X31 /X20/X2D/X30/X2E/X30/X35 /X28/X34/X2E/X34/X29 /X30/X2E/X33/XB1/X30/X2E/X30/X35 /X31 /X34 /X35 /X38 /X34/X2E/X30/XB1/X30/X2E/X31 /X46/X65/X65/X64/X20/X64/X69/X72/X65/X63/X74/X69/X6F/X6E /X54/X53/X53/X4F/X50/X38/X2D/X45/X2D/X43/X61/X72/X72/X69/X65/X72/X20/X54/X61/X70/X65 /X4E/X6F/X2E/X20/X46/X54/X30/X30/X38/X2D/X45/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X30 /X46/X54/X30/X30/X38/X2D/X45/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X30 /X2B/X30/X2E/X34 /X20/X2D/X30/X2E/X32/X36/X2E/X36 /X6D/X6D

/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /X45/X6E/X6C/X61/X72/X67/X65/X64/X20/X64/X72/X61/X77/X69/X6E/X67/X20/X69/X6E/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X72/X61/X6C/X20/X70/X61/X72/X74 /X4E/X6F/X2E/X20/X46/X54/X30/X30/X38/X2D/X45/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X30 /X32/XB1/X30/X2E/X35 /XF8/X31/X33/XB1/X30/X2E/X35 /XF8/X32/X31/XB1/X30/X2E/X38 /X31/X33/X2E/X34/XB1/X31/X2E/X30 /X31/X37/X2E/X35/XB1/X31/X2E/X30 /X33/X2C/X30/X30/X30/X51/X54/X59/X2E /X54/X53/X53/X4F/X50/X38/X2D/X45/X2D/X52/X65/X65/X6C /X46/X54/X30/X30/X38/X2D/X45/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X30 /X6D/X6D

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