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Rev AB January 16, 2011 Document Number: SP-AP-0826 Page 1 of 16 2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com SL38160-17AH SL38160-23AH Key Features

  • Audio + video clock generation
  • Programmable on chip analog VCXO with typical pull range of +/-150ppm
  • VCXO control voltage, 0V to 3V
  • Uses 27MHz pullable crystal
  • 3.3V +/-10% power supply range
  • Available in both Commercial (0 to 70C)and Industrial (-40 to 85C) temperature grades
  • Low power dissipation and low jitter
  • Integrated internal voltage regulator

Applications

  • HDTV & SDTV
  • Wireless HDMI
  • Set Top Box
  • Media Center
  • DVR

Description

The SL38160AZC-17AH and SL38160AZC-23AH are programmable low power VCXO Clock Generators designed to enable clock recovery and to synthesize the audio and video clocks required for advanced multimedia applications. The product is designed using SpectraLinear proprietary programmable EProClock™ technology to generate the output clocks. The product is offered in a space saving 16-pin TSSOP package. The two parts are identical except for IIC address, where the SL38160AZC-17AH uses D2(hex) while the SL38160AZC-23AH uses DA(hex). Block Diagram Programmable Audio/Video CG with VCXO

Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 2 of 16 SL38160-17AH SL38160-23AH Pin Configuration 16-Pin TSSOP Package Pin Description Pin Number Pin Name Pin Type Pin Description 1 XIN Input Crystal oscillator input. Use fundamental parallel mode 27MHz crystal. 2 27M_REF1 Output 27 MHz reference clock output 1. (Default on) (Can be changed to off/synchronous stop, pulled low to VSS, through I2C)

3 VIN Input VCXO frequency control voltage

4, 5, 13, VDD Power 3.3V +/-10% Positive Power Supply. 6, 10,12 VSS Power Power supply ground for VDD.

7 SDATA I/O I2C Serial Data

8 SCLK Input I2C Clock

9 VCLK Output Video clock output. (Default on) (Can be changed to off/high impedance state through I2C) 11 ACLK Output Audio clock output .(Default on) (Can be changed to off/synchronous stop, pulled low to VSS, through I2C) 14 27M_REF2 Output 27 MHz reference clock output 2. (Default on) (Can be changed to off/synchronous stop, pulled low to VSS, through I2C) 16 XOUT Output Crystal oscillator output. Use fundamental parallel mode 27MHz crystal.

Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 3 of 16 SL38160-17AH SL38160-23AH Absolute Maximum Ratings Description Condition Min Max Unit Supply voltage, VDD -0.5 4.2 V All Inputs and Outputs -0.5 VDD+0.5 V Ambient Operating Temperature In operation 0 70 °C Ambient Operating Temperature Industrial grade, in operation -40 85 °C Storage Temperature No power is applied -65 150 °C Junction Temperature In operation, power is applied - 125 °C Soldering Temperature - 260 °C ESD Rating (Human Body Model) JEDEC22-A114D -4,000 4,000 V ESD Rating (Charge Device Model) JEDEC22-C101C -1,500 1,500 V ESD Rating (Machine Model) JEDEC22-A115D -250 250 V Moisture Sensitivity Level JEDEC (J-STD-020) 1 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or other conditions beyond those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Unless otherwise stated VDD= 3.3V+/-10%, VIN=1.65V, Output Load=15pF and Ambient Temperature range 0 to +70°C for Commercial or -40 to +85°C for Industrial temperature option. Description Symbol Condition Min Typ Max Unit Operating Voltage VDD 3.3V +/-10% 2.97 3.3 3.63 V Input High Voltage VIH 0.7xVDD - - V Input Low Voltage VIL - - 0.3xVDD V Output High Voltage VOH IOH=-6mA VDD-0.5 - - V Output Low Voltage VOL IOL=6mA - - 0.5 V Operating Supply Current IDD Output load = 0pF - 20 25 mA VIN Input Impedance VINR 1 - - MΩ Input Pull-Down/Up Resistor - 250 - KΩ

Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 4 of 16 SL38160-17AH SL38160-23AH Unless otherwise stated VDD= 3.3V+/-10%, VIN=1.65V, Output Load=15pF for f<200MHz, 5pF for f>200MHz and Ambient Temperature range 0 to +70°C for Commercial or -40 to +85°C for Industrial temperature option. Parameter Symbol Condition Min Typ Max Unit Input Frequency Range FIN Crystal input - 27 - MHz Output Rise Time Tr VCLK and ACLK, all frequencies - - 1.5 ns Output Rise Time Tr 27M_REF1,27M_ REF2 clocks - - 2.0 ns Output Fall Time Tf VCLK and ACLK, all frequencies - - 1.5 ns Output Fall Time Tf 27M_REF1,27M_ REF2 clocks - - 2.0 ns Output Duty Cycle - All outputs ,f≤100MHz 45 50 55 % Output Duty Cycle - All outputs, f>100MHz 40 50 60 % Output Frequency Synthesis Error FOUT All Frequencies except 193.16MHz, which has a +15ppm error - - 0 ppm Cycle to Cycle Jitter - 27M_REF1, 27M_REF2 outputs - 160 250 ps Cycle to Cycle Jitter - VCLK output - 175 350 ps Cycle to Cycle Jitter - ACLK output - 150 250 ps Long Term Jitter1 - 27M_REF1, 27M_REF2 outputs - 85 120 ps-rms Long Term Jitter - 1 VCLK output - 250 700 ps-rms Long Term Jitter - 1 ACLK output - 550 950 ps-rms Frequency Settling Time - Time before valid clock output after programming frequency via IIC - - 0.5 ms Power-up Time TPUP Time from VDD minimum to valid frequency output - - 5.5 ms VCXO Pull Range2 ΔFVCXO Monotonic VCXO Crystal Pull Range - +/-150 - ppm Recommended Crystal Specifications (for VCXO applications)2 Symbol Description Comments Min Typ Max Unit FNOM Nominal frequency Fundamental mode - 27 - MHz FDELTA25 Frequency tolerance at 25°C -20 - 20 ppm FDELTAT Temperature tolerance 0 to 70°C (reference to 25°C ) -20 - 20 ppm CLNOM Nominal load capacitance - 14 - pF R1 Equivalent series resistance Fundamental mode (CL=series) - 20 50 Ω DL Drive level Nominal VDD @25°C over +/-150ppm Pull range - - 500 uW C0 Shunt capacitance - 3.0 7.0 pF

1 Measured with 1000 samples at 10us delay on oscilloscope

2 KDS 1C727000CC1K crystal

Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 5 of 16 SL38160-17AH SL38160-23AH C1 Motional capacitance - 11.8 - fF C0/C1 Ratio of shunt to motional capacitance 250 F3SEPHI Third overtone separation, high side Mechanical third (High side of 3xFNOM) 240 - - ppm F3SEPLO Third overtone separation, low side Mechanical third (Low side of 3xFNOM) - - -240 ppm Serial Data Interface To enhance the flexibility and function of the device, an I2C compatible interface is provided. Through the Serial Data Interface, various device functions, such as ACLK and VCLK frequency setting and individual clock output buffers can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up. Clock device register changes can be made after the device power up initialization process has completed. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, Access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. F or byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code descried in the command code definition section. The block write and block read protocol is outlined in the block read and block write protocol section, while The byte read and byte write protocol section outlines byte read and byte write information. The slave receiver address is 11010010 (D2h) for the SL38160AZC-17AH. The slave receiver address is 11011010 (DAh) for the SL38160AZC-23AH.

Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 6 of 16 SL38160-17AH SL38160-23AH Command Code Definition Bit Description 7 0 = Block read or block write operation, 1 = Byte read or byte write operation (6:0) Byte offset for byte read or byte write operation. For block read or block operations, these bits should be ‘0000000’ Block Read and Block Write Protocol Block Write Protocol Block Read Protocol Bit Description Bit Description

1 Start 1 Start

8:2 Slave address-7bits 8:2 Slave address-7bits

9 Write 9 Write

10 Acknowledge from slave 10 Acknowledge from slave

18:11 Command Code-8bits 18:11 Command Code-8bits

19 Acknowledge from slave 19 Acknowledge from slave

27:20 Byte Count-8bits 20 Repeat start

28 Acknowledge from slave 27:21 Slave address-7bits

36:29 Data byte 1-8bits 28 Read = 1

37 Acknowledge from slave 29 Acknowledge from slave

45:38 Data byte 2-8bits 37:30 Byte Count from slave 8bits

46 Acknowledge from slave 38 Acknowledge

… Data Byte/Slave Acknowledges 46:39 Data byte 1 from slave-8bits … Data Byte N-8bits 47 Acknowledge … Acknowledge from slave 55:48 Data byte 2 from slave-8bits … Stop 56 Acknowledge … Data bytes from slave/Acknowledge … Data Byte N from slave-8bits … NOT Acknowledge … Stop

Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 7 of 16 SL38160-17AH SL38160-23AH Byte Read and Byte Write Protocol Byte Write Protocol Byte Read Protocol Bit Description Bit Description 8:2 Slave address-7bits 8:2 Slave address-7bits 18:11 Command Code-8bits 18:11 Command Code-8bits 27:20 Data byte-8bits 20 Repeat start

29 Stop 28 Read

29 Acknowledge from slave

37:30 Byte Count from slave 8bits

38 NOT Acknowledge

39 Stop

Note: When writing to any register bytes between 32d to 63d (20h to 40h), an additional byte outside this range must be written to immediately afterward for proper loading to the register bytes within this range. I2C-bus Timing Specification PARAMETER SYMBOL STANDARD-MODE FAST-MODE UNIT MIN. MAX. MIN. MAX. SCL Clock Frequency fSCL 0 100 0 400 KHz START hold time tHD;STA 4.0 - 0.6 - us SCLK LOW period t LOW 4.7 - 1.3 - us SCLK HIGH period t HIGH 4.0 - 0.6 - us START Set-up time t SU;DAT 4.7 - 0.6 - us

Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 8 of 16 SL38160-17AH SL38160-23AH PARAMETER SYMBOL STANDARD-MODE FAST-MODE UNIT MIN. MAX. MIN. MAX. SDA set-up time tSU;DAT 250 - 100 - ns SDA/SCLK rise time tR - 1000 - 300 ns SDA/SCLK fall time tF - 300 - 300 ns STOP set-up time tSU;STO 4.0 - 0.6 - ns Bus free time tBUF 4.7 - 1.3 - us tLOWtF tHD;STA tR tHD;DAT tSU;DAT tHIGH tF tSU;STA tHD;STA tSU;STO tBUF SDATA SCLK tR S Sr P S

Table 1. Audio Clock Frequency Settings (pin 11) Table 2. Digital Television Video Clock Frequency Settings (pin 9)

3 Default output frequency on power up

Table 3. VGA Video Clock Settings (pin 9)4

4 Pin 9 is the video output clock used for both the Digital Television and VGA Video frequency settings

Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 11 of 16 SL38160-17AH SL38160-23AH Screen Resolution Refresh Rate (Hz) Video Clock (MHz) Register Byte# (DEC) and Bit [7:0] HEX, Setting Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte 114 Byte 128 1920x1080i 50 72.000 07 80 AB C6 04 00 4A C7 03 83 3E 34 1920x12005 154.000 06 00 6B C6 26 82 44 C7 03 83 3E 34 60 193.160 05 80 AB DE 32 F8 C2 C7 03 83 3E 36 60 193.250 05 00 AB C6 C1 4D 82 C7 03 83 3E 34 75 245.250 06 80 6B C6 1B 41 82 C7 03 83 3E 34 85 281.250 06 80 6B C6 1F 43 00 C7 0F C3 BE 34 1792x 1344 60 204.750 31 00 AB C6 16 C1 82 C7 03 83 3E 34 75 261.000 07 00 AB C6 07 40 C0 C7 0F C3 BE 34 1856x1392 60 218.250 31 00 AB C6 18 41 82 C7 03 83 3E 34 75 288.000 07 00 AB C6 08 00 C0 C7 0F C3 BE 34 1920x 1440 60 234.000 31 80 AB C6 0D 00 C2 C7 03 83 3E 34 75 297.000 07 00 AB C6 05 80 80 C7 0F C3 BE 34 5 15ppm synthesis error

Table 4. Output Control Table 5. Power Down Control Table 6. Additional Bytes to Program Note: these bytes should be programmed once after device power up.

6 Default condition

Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 13 of 16 SL38160-17AH SL38160-23AH

Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 14 of 16 SL38160-17AH SL38160-23AH Typical Application Circuit 27M_REF1 XOUT VDD 27M_REF2 VDD VSS ACLK VSS VCLK XIN VIN VDD VSS SDATA SCLK VDD KDS1C727000CC1K 3.3V 0.01uF 3.3V 0.01uF 3.3V 0.01uF GND 3.3V 0.01uF GND GND GND 3.3V 10uF GND Pad Via Legend

22 Ohm

General Guidelines: 1. Place crystal on same side of the board. 2. Place 0.01µF capacitors as close as possible to the power pin. 3. Install one bulk capacitor (10µF). Note that this filtered power should connect to the 0.01µF capacitor pads first. This is known as pin-cap-via. 4. The 22 Ohm series resistors placed on clock outputs are board dependent. This is a nominal value for 50 Ohm impedance boards. Never share ground vias. 5. It is preferable to have a ground flood directly underneath the part. 6. If PCB process takes advantage of via-in-pad technology, then it is recommended that the ground side of all bypass capacitors have the GND via placed inside the pad to lower inductance to ground.

Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 15 of 16 SL38160-17AH SL38160-23AH Package Outline and Package Dimensions 16-Pin TSSOP Package (4.4mm)

Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 16 of 16 SL38160-17AH SL38160-23AH Thermal Characteristics Parameter Symbol Condition Min Typ Max Unit Thermal Resistance Junction to Ambient θ JA Still air - 80 - °C/W θ JA 1m/s air flow - 70 - °C/W θ JA 3m/s air flow - 68 - °C/W Thermal Resistance Junction to Case θ JC Independent of air flow - 36 - °C/W

Ordering Information

Ordering Number Marking Shipping Package Package Temperature SL38160AZC-17AH SL38160AZC-17AH Tube 16-pin TSSOP 0 to 70°C SL38160AZC-17AHT SL38160AZC-17AH Tape and Reel 16-pin TSSOP 0 to 70°C SL38160AZC-23AH SL38160AZC-23AH Tube 16-pin TSSOP 0 to 70°C SL38160AZC-23AHT SL38160AZC-23AH Tape and Reel 16-pin TSSOP 0 to 70°C SL38160AZI-17AH SL38160AZI-17AH Tube 16-pin TSSOP -40 to 85°C SL38160AZI-17AHT SL38160AZI-17AH Tape and Reel 16-pin TSSOP -40 to 85°C SL38160AZI-23AH SL38160AZI-23AH Tube 16-pin TSSOP -40 to 85°C SL38160AZI-23AHT SL38160AZI-23AH Tape and Reel 16-pin TSSOP -40 to 85°C Notes: 1. All SLI products are RoHS compliant. Document History Page REV. Issue Date Originator Description of change A.1.0 7/8/10 D. Christenberry Create initial datasheet as advance information. B.1.0 9/2/10 D. Christenberry Final datasheet B. 1.1 10/5/10 D. Christenberry New frequency support added per customer, also updated package drawing B.1.2 10/14/10 D. Christenberry Updated cy-cy jitter specifications AA 10/28/10 D. Christenberry Release version. Added additional bytes, 5pF load condition for f>200Mz AB 1/16/11 D. Christenberry Added Industrial temperature operation The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratorie s harmless against all claims and damages