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Document overview
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Technical content
Features
- Optimized 100 MHz Operating Frequencies to Meet the Next Generation PCI-Express Gen 2 & Gen 3
- Low power push-pull type differential output buffers
- Integrated voltage regulator
- Integrated resistors on differential clocks
- Four 100-MHz differential PCI-Express clocks
- Low jitter (<50pS)
- Buffered Reference Clock 25MHz
- EProClock ® Programmable Technology
- I 2C support with readback capabilities
- Triangular Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction
- 25MHz Crystal Input or Clock input
- Industrial Temperature -40oC to 85oC
- 3.3V Power supply
- 32-pin QFN package SRC 25M x4 x1 Block Diagram Pin Configuration
DOC#: SP-AP-0776 (Rev. 0.2) Page 2 of 16 32-QFN Pin Definitions EProClock® Programmable Technology EProClock® is the world’s first non-volatile programmable clock. The EProClock ® technology allows board designer to promptly achieve optimum compliance and clock signal integrity; historically, attainable typically through device and/or board redesigns. EProClock ® technology can be configured through SMBus or hard coded. Features: - > 4000 bits of configurations - Can be configured through SMBus or hard coded - Custom frequency sets - Differential skew control on true or compliment or both - Differential duty cycle control on true or compliment or both - Differential amplitude control - Differential and single-ended slew rate control - Program Internal or External series resistor on single-ended clocks - Program different spread profiles and modulation rates Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Pin No. Name Type Description 1 VDD PWR 3.3V Power Supply
2 VSS GND Ground
3 NC NC No Connect. 4 NC NC No Connect. 5 VDD PWR 3.3V Power Supply 6 NC NC No Connect. 7 NC NC No Connect.
8 VSS GND Ground
9 VSS GND Ground
10 SRC0 O, DIF 100MHz True differential serial reference clock
11 SRC0# O, DIF 100MHz Complement differential serial reference clock
12 VSS GND Ground
13 SRC1 O, DIF 100MHz True differential serial reference clock
14 SRC1# O, DIF 100MHz Complement differential serial reference clock
15 VDD PWR 3.3V Power Supply 16 NC NC No Connect. 17 VDD PWR 3.3V Power Supply 18 VDD PWR 3.3V Power Supply
19 SRC2# O, DIF 100MHz Complement differential serial reference clock
20 SRC2 O, DIF 100MHz True differential serial reference clock
21 VSS GND Ground
22 SRC3# O, DIF 100MHz Complement differential serial reference clock
23 SRC3 O, DIF 100MHz True differential serial reference clock
24 VDD PWR 3.3V Power Supply 25 CKPWRGD/PD# I 3.3V LVTTL input pin. When PD# is asserted low, the device will power down.
26 VSS GND Ground
27 XOUT O, SE 25MHz Crystal output, Float XOUT if using CLKIN (Clock Input)
28 XIN/CLKIN I 25MHz Crystal input or 3.3V, 25MHz Clock input 29 VDD PWR 3.3V Power Supply 30 REF O 3.3V, 25MHz clock output.
31 SDATA I/O SMBus compatible SDATA
32 SCLK I SMBus compatible SCLOCK
byte is encoded in the command code described in Table 1. slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Table 2. Block Read and Block Write Protocol
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
19 Acknowledge from slave 19 Acknowledge from slave
28 Acknowledge from slave 27:21 Slave address–7 bits
37 Acknowledge from slave 29 Acknowledge from slave
46 Acknowledge from slave 38 Acknowledge
Table 3. Byte Read and Byte Write Protocol
29 Stop 28 Read
29 Acknowledge from slave
38 NOT Acknowledge
39 Stop
DOC#: SP-AP-0776 (Rev. 0.2) Page 5 of 16 0 1 RESERVED RESERVED Byte 2: Control Register 2 (continued) Bit @Pup Name Description Byte 3: Control Register 3 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED 4 1 RESERVED RESERVED 3 1 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 4: Control Register 4 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 1 SRC0_OE Output enable for SRC0 0 = Output Disabled, 1 = Output Enabled 5 1 SRC1_OE Output enable for SRC1 0 = Output Disabled, 1 = Output Enabled 4 0 RESERVED RESERVED 3 1 SRC3_OE Output enable for SRC3 0 = Output Disabled, 1 = Output Enabled 2 1 SRC2_OE Output enable for SRC2 0 = Output Disabled, 1 = Output Enabled 1 0 PLL1_SS_EN Enable PLL1s spread modulation, 0 = Spread Disabled, 1 = Spread Enabled 0 1 RESERVED RESERVED Byte 5: Control Register 5 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED Byte 6: Control Register 6 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED
DOC#: SP-AP-0776 (Rev. 0.2) Page 6 of 16 5 0 REF Bit1 REF slew rate control (see Byte 13 for Slew Rate Bit0 & Bit2) 0 = High, 1 = Low 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED Byte 6: Control Register 6 Byte 7: Vendor ID Bit @Pup Name Description 7 0 Rev Code Bit 3 Revision Code Bit 3 6 1 Rev Code Bit 2 Revision Code Bit 2 5 0 Rev Code Bit 1 Revision Code Bit 1 4 0 Rev Code Bit 0 Revision Code Bit 0 3 1 Vendor ID bit 3 Vendor ID Bit 3 2 0 Vendor ID bit 2 Vendor ID Bit 2 1 0 Vendor ID bit 1 Vendor ID Bit 1 0 0 Vendor ID bit 0 Vendor ID Bit 0 Byte 8: Control Register 8 Bit @Pup Name Description 7 1 Device_ID3 RESERVED 6 0 Device_ID2 RESERVED 5 0 Device_ID1 RESERVED 4 0 Device_ID0 RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED Byte 9: Control Register 9 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 1 RESERVED RESERVED 4 0 TEST _MODE_SEL Test mode select either REF/N or tri-state 0 = All outputs tri-state, 1 = All output REF/N 3 0 TEST_MODE_ENTRY Allows entry into test mode 0 = Normal Operation, 1 = Enter test mode(s)
DOC#: SP-AP-0776 (Rev. 0.2) Page 7 of 16 2 1 I2C_VOUT<2> Amplitude confi gurations differential clocks I2C_VOUT[2:0] 000 = 0.30V 001 = 0.40V 010 = 0.50V 011 = 0.60V 100 = 0.70V 101 = 0.80V (default) 110 = 0.90V 111 = 1.00V 1 0 I2C_VOUT<1> 0 1 I2C_VOUT<0> Byte 10: Control Register 10 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 11: Control Register 11 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 12: Byte Count Bit @Pup Name Description 7 0 BC7 Byte count register for block read operation. The default value for Byte count is 15. In order to read beyond Byte 15, the user should change the byte count limit.to or beyond the byte that is desired to be read.
60 B C 6
50 B C 5
40 B C 4
31 B C 3
21 B C 2
11 B C 1
01 B C 0
Byte 9: Control Register 9
is also an asynchronous input for powering up the system. and held before turning off the VCOs and the crystal oscillator.
40 O T P _ 4 O T P _ I D
21 O T P _ 2
10 O T P _ 1
00 O T P _ 0
Table 4. Output Driver Status
DOC#: SP-AP-0776 (Rev. 0.2) Page 10 of 16 IIH Input High Leakage Current Except internal pull-down resistors, 0 < V IN < VDD –5 A IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN < VDD –5 – A VOH 3.3V Output High Voltage (SE) I OH = –1 mA 2.4 – V VOL 3.3V Output Low Voltage (SE) I OL = 1 mA – 0.4 V IOZ High-impedance Output Current –10 10 A CIN Input Pin Capacitance 1.5 5 pF COUT Output Pin Capacitance 6 pF LIN Pin Inductance – 7 nH IDD_PD Power Down Current – 1 mA IDD_3.3V Dynamic Supply Current All outputs enab led. Differential clocks with 7” traces 2pF load. –6 5 m A Parameter Description C ondition Min. Max. Unit
DOC#: SP-AP-0776 (Rev. 0.2) Page 11 of 16 Parameter Description Condition Min. Max. Unit Crystal LACC Long-term Accuracy Measured at VDD/2 differential – 250 ppm Clock Input T DC CLKIN Duty Cycle Measured at VDD/2 47 53 % TR/TF CLKIN Rise and Fall Times Measured between 0.2V DD and 0.8VDD 0.5 4.0 V/ns TCCJ CLKIN Cycle to Cycle Jitter Measured at VDD/2 – 250 ps TLTJ CLKIN Long Term Jitter Measured at VDD/2 – 350 ps VIH Input High Voltage XIN / CLKIN pin 2 VDD+0.3 V VIL Input Low Voltage XIN / CLKIN pin – 0.8 V IIH Input HighCurrent XIN / CLKIN pin, VIN = VDD – 35 uA IIL Input LowCurrent XIN / CLKIN pin, 0 < VIN <0.8 -35 – uA SRC at 0.7V T DC SRC Duty Cycle Measured at 0V differential 45 55 % TPERIOD 100 MHz SRC Period Measured at 0V differential at 0.1s 9.99900 10.0010 ns TPERIODSS 100 MHz SRC Period, SSC Measured at 0V differential at 0.1s 10.02406 10.02607 ns TPERIODAbs 100 MHz SRC Absolute Period Measured at 0V differential at 1 clock 9.87400 10.1260 ns TPERIODSSAbs 100 MHz SRC Absolute Period, SSC Meas ured at 0V differential at 1 clock 9.87406 10.1762 ns TCCJ SRC Cycle to Cycle Jitter Measured at 0V differential – 125 ps RMSGEN1 Output PCIe* Gen1 REFCLK phase jitter BER = 1E-12 (including PLL BW 8 - 16 MHz, ζ = 0.54, Td=10 ns, Ftrk=1.5 MHz) 01 0 8 p s RMSGEN2 Output PCIe* Gen2 REFCLK phase jitter Includes PLL BW 8 - 16 MHz, Jitter Peaking = 3dB, ζ = 0.54, Td=10 ns), Low Band, F < 1.5MHz 03 . 0 p s RMSGEN2 Output PCIe* Gen2 REFCLK phase jitter Includes PLL BW 8 - 16 MHz, Jitter Peaking = 3dB, ζ = 0.54, Td=10 ns), Low Band, F < 1.5MHz 03 . 1 p s RMSGEN3 Output phase jitter impact – PCIe* Gen3 Includes PLL BW 2 - 4 MHz, CDR = 10MHz) 01 . 0 p s LACC SRC Long Term Accuracy Measured at 0V differential – 100 ppm TR / TF SRC Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV REF at 3.3V T DC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Period Measurement at 1.5V 39.996 40.004 ns TPERIODAbs Absolute Period Measurement at 1.5V 39.32360 40.67640 ns TR / TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 250 ps LACC Long Term Accuracy Measured at 1.5V – 100 ppm
DOC#: SP-AP-0776 (Rev. 0.2) Page 12 of 16 ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up – 1.8 ms TSS Stopclock Set-up Time 10.0 – ns Parameter Description Condition Min. Max. Unit
DOC#: SP-AP-0776 (Rev. 0.2) Page 15 of 16
Ordering Information
Part Number Package Type Product Flow Lead-free SL28PCIe25ALC 32-pin QFN Commercial, 0 to 85C SL28PCIe25ALCT 32-pin QFN–Tape and Reel Commercial, 0 to 85C SL28PCIe25ALI 32-pin QFN Industrial, -40 to 85C SL28PCIe25ALIT 32-pin QFN–Tape and Reel Industrial, -40 to 85C Package Diagrams 32-Lead QFN 5x 5mm
DOC#: SP-AP-0776 (Rev. 0.2) Page 16 of 16 Document History Page Document Title: SL28PCIe25 PC EProClock® PCI Express Gen 2 & Gen 3 Generator DOC#: SP-AP-0776 (Rev. 0.2) REV. Issue Date Orig. of Change Description of Change 1.0 9/17/09 JMA Initial Release 1.1 10/13/09 JMA Updated mi scellanous text content AA 05/17/10 JMA 1. Added CLKINFeatures. 2. Updated default spread to be non-spread PCI-Express 3. Updated I2C registers 4. Updated IDD Spec AA 10/21/10 TRP Updated mi scellanous text content AA 11/17/10 TRP 1. Updated spread percentage in Byte1 bit6 2. Updated IDD condition on trace lenght to 7”
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