SL28PCIE10 SILABS | Alldatasheet
Document overview
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Technical content
Features
- One Programmable Spreadable Single-ended Clock
- PCI-Express Gen 2 Compliant
- Low power push-pull type differential output buffers
- Integrated voltage regulator
- Integrated resistors on differential clocks
- Scalable low voltage VDD_IO (3.3V to 1.05V)
- Wireless friendly 3-bits slew rate control on single-ended clocks.
- Four 100MHz Differential clocks
- 27MHz Video clock
- Buffered Reference Clock 25MHz
- EProClock ® Programmable Technology
- I 2C support with readback capabilities
- Triangular Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction
- Industrial Temperature -40oC to 85oC
- 3.3V Power supply
- 32-pin QFN package 100Mhz 48M REF 27M Programmable Single-ended Clock x4 x1 x1 x1 x1 Block Diagram Pin Configuration SCLOCK SDATA REF VDD_REF XIN XOUT VSS_REF CKPWRGD/PD# 32 31 30 29 28 27 26 25 VDD 12 4 VDD_SRC VSS 22 3 SRC3 NC 32 2 SRC3# NC 42 1 VSS_SRC VDD_27 52 0 SRC2 27M_NSS 61 9 SRC2# Prog_SE 71 8 VDD_SRC_IO VSS_27 81 7 VDD_SRC 9 1 01 11 21 31 41 51 6VSS_SRC SRC0 SRC0# VSS_SRC SRC1 SRC1# VDD_SRC_IO OE#_SRC2_SRC3 SL28PCIe10
Programmable Single ended clock SL28PCIe10 allows flexibility of programming any frequency at single ended output Prog_SE. Prog_SE can be factory programmed to any frequency as required by the end user with a 3.3V swing single ended output. This clock can have a f eature of Spread Spectrum to reduce EMI. Pin No. Name Type Description 1 VDD PWR 3.3V Power supply
2 VSS GND Ground
3 NC NC No Connect. 4 NC NC No Connect. 5 VDD_27 PWR 3.3V Power supply 6 27M_NSS O,SE Non-spread 27MHz video clock output
7 Prog_SE O, SE Spreadable Programmable Single-Ended clock output
8 VSS_27 GND Ground
9 VSS_SRC GND Ground
10 SRC0 O, DIF 100MHz True differential serial reference clock
11 SRC0# O, DIF 100MHz Complement differential serial reference clock
12 VSS_SRC GND Ground
13 SRC1 O, DIF 100MHz True differential serial reference clock
14 SRC1# O, DIF 100MHz Complement differential serial reference clock
15 VDD_SRC_IO PWR Scalable 3.3V to 1.05V power supply for output buffer 16 OE#_SRC2_SRC3 I 3.3V tolerance input to disable Output on Pin 7 and Pin 8 17 VDD_SRC PWR 3.3V Power supply 18 VDD_SRC_IO PWR Scalable 3.3V to 1.05V power supply for output buffer
19 SRC2# O, DIF 100MHz True differential serial reference clock
20 SRC2 O, DIF 100MHz Complement differential serial reference clock
21 VSS_SRC GND Ground
22 SRC3# O, DIF 100MHz True differential serial reference clock
23 SRC3 O, DIF 100MHz Complement differential serial reference clock
24 VDD_SRC PWR 3.3V Power supply 25 CK_PWRGD/PD# I 3.3V LVTTL input. After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input for asserting power down (active LOW)
26 VSS_REF GND Ground
27 XOUT O, SE 25MHz Crystal output
28 XIN I 25MHz Crystal input
29 VDD_REF PWR 3.3V Power supply for outputs and also maintains SMBUS registers during power-down
30 REF PD, I/O Reference 25MHz clock output
31 SDATA I/O SMBus compatible SDATA
32 SCLK I SMBus compatible SCLOCK
byte is encoded in the command code described in Table 1. slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Table 2. Block Read and Block Write Protocol
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
19 Acknowledge from slave 19 Acknowledge from slave
28 Acknowledge from slave 27:21 Slave address–7 bits
37 Acknowledge from slave 29 Acknowledge from slave
46 Acknowledge from slave 38 Acknowledge
Table 3. Byte Read and Byte Write Protocol
29 Stop 28 Read
29 Acknowledge from slave
38 NOT Acknowledge
39 Stop
Table 2. Block Read and Block Write Protocol (continued)
Byte 0: Control Register 0 Bit @Pup Name Description
7 HW RESERVED RESERVED
0 1 PD_Restore Save configuration when PD# is asserted 0 = Config. cleared, 1 = Config. saved Byte 1: Control Register 1 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 0 PLL1_SS_DC Select for down or center SS 0 = Down spread, 1 = Center spread 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 1 RESERVED RESERVED 1 0 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 2: Control Register 2 Bit @Pup Name Description 7 1 REF_OE Output enable for REF 0 = Output Disabled, 1 = Output Enabled 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED 4 1 RESERVED RESERVED 3 1 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 3: Control Register 3 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED 4 1 RESERVED RESERVED 3 1 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 RESERVED RESERVED
Byte 3: Control Register 3 Byte 4: Control Register 4 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 1 SRC0_OE Output enable for SRC0 0 = Output Disabled, 1 = Output Enabled 5 1 SRC1_OE Output enable for SRC1 0 = Output Disabled, 1 = Output Enabled 4 1 RESERVED RESERVED 3 1 SRC3_OE Output enable for SRC3 0 = Output Disabled, 1 = Output Enabled 2 1 SRC2_OE Output enable for SRC2 0 = Output Disabled, 1 = Output Enabled 1 1 PLL1_SS_EN Enable PLL1s spread modulation, 0 = Spread Disabled, 1 = Spread Enabled 0 1 RESERVED RESERVED Byte 5: Control Register 5 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED Byte 6: Control Register 6 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 REF Bit1 REF slew rate control (see Byte 13 for Slew Rate Bit 0 and Bit 2) 0 = High, 1 = Low 4 0 RESERVED RESERVED 3 0 27MHz Bit 1 27MHz slew rate control (see Byte 13 for Slew Rate Bit 0 and Bit 2) 0 = High, 1 = Low 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED Byte 7: Vendor ID Bit @Pup Name Description 7 0 Rev Code Bit 3 Revision Code Bit 3 6 1 Rev Code Bit 2 Revision Code Bit 2
5 0 Rev Code Bit 1 Revision Code Bit 1 4 0 Rev Code Bit 0 Revision Code Bit 0 3 1 Vendor ID bit 3 Vendor ID Bit 3 2 0 Vendor ID bit 2 Vendor ID Bit 2 1 0 Vendor ID bit 1 Vendor ID Bit 1 0 0 Vendor ID bit 0 Vendor ID Bit 0 Byte 7: Vendor ID Byte 8: Control Register 8 Bit @Pup Name Description 7 1 Device_ID3 RESERVED 6 0 Device_ID2 RESERVED 5 0 Device_ID1 RESERVED 4 0 Device_ID0 RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 1 27M_non-SS_OE Output enable for 27M_non-SS 0 = Output Disabled, 1 = Output Enabled 0 1 Prog_SE_OE Output enable for Prog_SE 0 = Output Disabled, 1 = Output Enabled Byte 9: Control Register 9 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 1 RESERVED RESERVED 4 0 TEST _MODE_SEL Test mode select either REF/N or tri-state 0 = All outputs tri-state, 1 = All output REF/N 3 0 TEST_MODE_ENTRY Allows entry into test mode 0 = Normal Operation, 1 = Enter test mode(s) 2 1 I2C_VOUT<2> Amplitude confi gurations differential clocks I2C_VOUT[2:0] 000 = 0.30V 001 = 0.40V 010 = 0.50V 011 = 0.60V 100 = 0.70V 101 = 0.80V (default) 110 = 0.90V 111 = 1.00V 1 0 I2C_VOUT<1> 0 1 I2C_VOUT<0> Byte 10: Control Register 10 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED
Byte 13: Control Register 13 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 10: Control Register 10 (continued) Bit @Pup Name Description Byte 11: Control Register 11 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 12: Byte Count Bit @Pup Name Description 7 0 BC7 Byte count register for block read operation. The default value for Byte count is 15. In order to read beyond Byte 15, the user should change the byte count limit.to or beyond the byte that is desired to be read.
60 B C 6
50 B C 5
40 B C 4
31 B C 3
21 B C 2
11 B C 1
01 B C 0
Bit @Pup Name Description 7 1 REF_Bit2 Drive Strength Control - Bit[2:0], Note: See Byte 6 Bit 5 for REF Slew Rate Bit 1 and Byte 6 Bit 3 for 27MHz Slew Rate Bit 1 Normal mode default ‘101’ Wireless Friendly Mode default to ‘111’
61 R E F _ B i t 0
5 1 27MHz_NSS_Bit2 4 1 27MHz_NSS_Bit0 3 1 Prog_SE_Bit2 2 1 Prog_SE_Bit0 1 0 RESERVED RESERVED 0 0 Wireless Friendly mode Wireless Friendly Mode 0 = Disabled, Default all single-ended clocks slew rate config bits to ‘101’ 1 = Enabled, Default all single-ended clocks slew rate config bits to ‘111’
VCOs and the crystal oscillator. LOW on their next HIGH-to-LOW transition. first rising edge of CKPWRGD. CPU signals are CPUT = HIGH and CPUC = LOW. more than two SRC clock cycles.
40 O T P _ 4 O T P _ I D
20 O T P _ 2
10 O T P _ 1
00 O T P _ 0
Table 4. Output Driver Status during OE#_SRC2_SRC3 Table 5. Output Driver Status
Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD_3.3V Main Supply Voltage – 4.6 V VDD_IO IO Supply Voltage 4.6 V VIN Input Voltage Relative to V SS –0.5 4.6 V DC TS Temperature, Storage Non-functional –65 150 °C TA Temperature, Operating Ambient Functional -40 85 °C TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case MIL-STD-883E Method 1012.1 – 20 °C/ W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/ W ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V UL-94 Flammability Rating At 1/8 in. V–0 Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Parameter Description Condition Min. Max. Unit VDD core 3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V VIH 3.3V Input High Voltage (SE) 2.0 V DD + 0.3 V VIL 3.3V Input Low Voltage (SE) V SS – 0.3 0.8 V VIHI2C Input High Voltage SDATA, SCLK 2.2 – V VILI2C Input Low Voltage SDATA, SCLK – 1.0 V VIH_FS FS Input High Voltage 0.7 VDD+0.3 V VIL_FS FS Input Low Voltage V SS – 0.3 0.35 V IIH Input High Leakage Current Except internal pull-down resistors, 0 < V IN < VDD –5 A IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN < VDD –5 – A VOH 3.3V Output High Voltage (SE) I OH = –1 mA 2.4 – V VOL 3.3V Output Low Voltage (SE) I OL = 1 mA – 0.4 V VDD IO Low Voltage IO Supply Voltage 1 3.465 V IOZ High-impedance Output Current –10 10 A CIN Input Pin Capacitance 1.5 5 pF COUT Output Pin Capacitance 6p F LIN Pin Inductance – 7 nH IDD_PD Power Down Current – 1 mA IDD_3.3V Dynamic Supply Current All outputs enabled. SE clocks with 8” traces and 4pF load. Differential clocks with 7” traces and 2pF load. –6 5 m A IDD_VDD_IO Dynamic Supply Current All outputs enabled. SE clocks with 8” traces and 4pF load. Differential clocks with 7” traces and 2pF load. –2 5 m A
Parameter Description Condition Min. Max. Unit Crystal LACC Long-term Accuracy Measured at VDD/2 differential – 250 ppm Clock Input TDC CLKIN Duty Cycle Measured at VDD/2 47 53 % TR/TF CLKIN Rise and Fall Times Measured between 0.2V DD and 0.8VDD 0.5 4.0 V/ns TCCJ CLKIN Cycle to Cycle Jitter Measured at VDD/2 – 250 ps TLTJ CLKIN Long Term Jitter Measured at VDD/2 – 350 ps VIH Input High Voltage XIN / CLKIN pin 2 VDD+0.3 V VIL Input Low Voltage XIN / CLKIN pin – 0.8 V IIH Input High Current XIN / CLKIN pin, VIN = VDD – 35 uA IIL Input Low Current XIN / CLKIN pin, 0 < VIN <0.8 -35 – uA SRC at 0.7V T DC SRC Duty Cycle Measured at 0V differential 45 55 % TPERIOD 100 MHz SRC Period Measured at 0V differential at 0.1s 9.99900 10.0010 ns TPERIODSS 100 MHz SRC Period, SSC Measured at 0V differential at 0.1s 10.02406 10.02607 ns TPERIODAbs 100 MHz SRC Absolute Period Measured at 0V differential at 1 clock 9.87400 10.1260 ns TPERIODSSAbs 100 MHz SRC Absolute Period, SSC Measured at 0V differential at 1 clock 9.87406 10.1762 ns TSKEW(window) Any SRC Clock Skew from the earliest bank to the latest bank Measured at 0V differential – 3.0 ns TCCJ SRC Cycle to Cycle Jitter Measured at 0V differential – 125 ps RMSGEN1 Output PCIe* Gen1 REFCLK phase jitter BER = 1E-12 (including PLL BW 8 - 16 MHz, ζ = 0.54, Td=10 ns, Ftrk=1.5 MHz) 01 0 8 p s RMSGEN2 Output PCIe* Gen2 REFCLK phase jitter Includes PLL BW 8 - 16 MHz, Jitter Peaking = 3dB, ζ = 0.54, Td=10 ns), Low Band, F < 1.5MHz 03 . 0 p s RMSGEN2 Output PCIe* Gen2 REFCLK phase jitter Includes PLL BW 8 - 16 MHz, Jitter Peaking = 3dB, ζ = 0.54, Td=10 ns), Low Band, F < 1.5MHz 03 . 1 p s LACC SRC Long Term Accuracy Measured at 0V differential – 100 ppm TR / TF SRC Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV 27M_NSS at 3.3V T DC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Spread 27M Period Measurement at 1.5V 37.03594 37.03813 ns TR / TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 300 ps LACC 27_M Long Term Accuracy Measured at crossing point V OX –5 0 p p m REF T DC REF Duty Cycle Measurement at 1.5V 45 55 %
Figure 5. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number Package Type Product Flow Lead-free SL28PCIe10ALI 32-pin QFN Industrial, -40 to 85C SL28PCIe10ALIT 32-pin QFN–Tape and Reel Industrial, -40 to 85C SL28PCIe10ALC 32-pin QFN Commercial, 0 to 85C SL28PCIe10ALCT 32-pin QFN–Tape and Reel Commercial, 0 to 85C This device is Pb free and RoHS compliant. Package Diagrams 32-Lead QFN 5x 5mm (Saw Version) SL 28 PCIe10 A L I - T Temperature Designator Package Designator L : QFN Revision Number A = 1st Silicon Generic Part Number Designated Family Number Company Initials Packaging Designator for Tape and Reel
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil- icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre- sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli- cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Document History Page Document Title: SL28PCIe10 PC EProClock®PCI-Express Gen 2 Clock Generator Document #: SP-AP-0212 (Rev. AA) REV. Issue Date Orig. of Change Description of Change 1.0 10/15/10 TRP Initial Release AA 10/22/10 TRP 1. Updated miscellaneous text content 2. Updated absolute maximum value of VDD_IO AA 12/2/10 TRP 1. Updated PD# Assertion, OE# _SRC2_SRC3 Assertion descriptions AA 12/7/10 TRP 1. Added Crystal and Clock Input AC specifications 2. Removed redundant VIXH and VIXL from DC specifications AA 12/15/10 TRP 1. Updated Power Down description