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Technical content
Features
- Intel CK505 Clock Revision 1.0 Compliant
- Hybrid Video Support - Simultaneous DOT96, 27MHz_SS and 27MHz_NSS video clocks
- PCI-Express Gen 2 Compliant
- Low power push-pull type differential output buffers
- Integrated voltage regulator
- Integrated resistors on differential clocks
- Scalable low voltage VDD_IO (3.3V to 1.05V)
- Wireless friendly 3-bits slew rate control on single-ended clocks.
- Differential CPU clocks with selectable frequency
- 100MHz Differential SRC clocks
- 100MHz Differential SATA clocks
- 96MHz Differential DOT clock
- 27MHz Video clock
- Buffered Reference Clock 14.318MHz
- PC EProClock ® Programmable Technology
- I 2C support with readback capabilities
- Industrial Temperature -40oC to 85oC
- Triangular Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction
- 3.3V Power supply
- 32-pin QFN package CPU SRC SATA DOT96 REF 27M x2 x1 x 1 x 1 x1 x2 Block Diagram Pin Configuration Internal 100K-ohm Pull-Down Resistor SCLK SDATA REF0/ FS VDD_REF XTAL_IN XTAL_OUT VSS_REF CKPWRGD/ PD# 32 31 30 29 28 27 26 25 VDD_DOT 12 4 VDD_CPU VSS_DOT 22 3 CPU0 DOT96 32 2 CPU#0 DOT96# 42 1 VSS_CPU VDD_27 52 0 CPU1 27_NSS 61 9 CPU#1 27_SS 71 8 VDD_CPU_IO VSS_27 81 7 VDD_SRC 9 1 01 11 21 31 41 51 6VSS_SATA SRC0 / SATA SRC0# / SATA# VSS_SRC SRC1 SRC1# VDD_SRC_IO 27_OE#
Pin No. Name Type Description 1 VDD_DOT PWR 3.3V Power supply for outputs and PLL
2 VSS_DOT GND Ground for outputs
3 DOT96 O, DIF Fixed true 96MHz clock output
4 DOT96# O, DIF Fixed complement 96MHz clock output
5 VDD_27 PWR 3.3V Power supply for 27MHz PLL 6 27M_NSS O,SE Non-spread 27MHz video clock output 7 27M_SS O, SE Spread 27MHz video clock output
8 VSS_27 GND Ground for 27MHz PLL
9 VSS_SATA GND Ground for outputs
10 SRC0 / SATA O, DIF 100MHz True differential serial reference clock
11 SRC0# / SATA# O, DIF 100MHz Complement differential serial reference clock
12 VSS_SRC GND Ground for PLL
13 SRC1 O, DIF 100MHz True differential serial reference clock
14 SRC1# O, DIF 100MHz Complement differential serial reference clock
15 VDD_SRC_IO PWR Scalable 3.3V to 1.05V power supply for output buffer 16 27_OE# I 3.3V tolerance input pin to enable and disable both 27_NSS and 27_SS 17 VDD_SRC PWR 3.3V Power supply for PLL 18 VDD_CPU_IO PWR Scalable 3.3V to 1.05V power supply for output buffer
19 CPU1# O, DIF Complement diff erential CPU clock output
20 CPU1 O, DIF True differential CPU clock output
21 VSS_CPU GND Ground for PLL
22 CPU0# O, DIF Complement diff erential CPU clock output
23 CPU0 O, DIF True differential CPU clock output
24 VDD_CPU PWR 3.3V Power supply for CPU PLL 25 CKPWRGD/PD# I 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS. After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for asserting power down (active LOW)
26 VSS_REF GND Ground for outputs
27 XOUT O, SE 14.318MHz Crystal output 28 XIN I 14.318MHz Crystal input 29 VDD_REF PWR 3.3V Power supply for outputs and also maintains SMBUS registers during power-down 30 REF/FS** PD, I/O 3.3V tolerant input for Graphi c clock selection/fixed 14.318MHz clock output. (Internal 100K-ohm pull-down resistor on FS pin) Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
31 SDATA I/O SMBus compatible SDATA
32 SCLK I SMBus compatible SCLOCK
and CKPWRGD transitions are ignored except in test mode. byte is encoded in the command code described in Table 1. slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Table 2. Block Read and Block Write Protocol
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
19 Acknowledge from slave 19 Acknowledge from slave
28 Acknowledge from slave 27:21 Slave address–7 bits
37 Acknowledge from slave 29 Acknowledge from slave
46 Acknowledge from slave 38 Acknowledge
Table 3. Byte Read and Byte Write Protocol
29 Stop 28 Read
29 Acknowledge from slave
38 NOT Acknowledge
39 Stop
Table 2. Block Read and Block Write Protocol (continued)
Byte 0: Control Register 0 Bit @Pup Name Description
7 HW FS CPU Frequency Select Bit, set by HW
0 = 133MHz, 1= 100MHz 6 0 RESERVED RESERVED 5 1 RESERVED RESERVED 4 0 iAMT_EN iAMT Enable 0 = Legacy Mode, 1 = iAMT Enabled 3 0 RESERVED RESERVED 2 0 SRC_Main_SEL Select source for SRC clock 0 = SRC_MAIN = PLL1, PLL3_CFG Table applies 1 = SRC_MAIN = PLL3, PLL3_CFG Table does not apply 1 0 SATA_SEL Select source of SATA clock 0 = SATA = SRC_MAIN, 1= SATA = PLL4 0 1 PD_Restore Save configuration when PD# is asserted 0 = Config. cleared, 1 = Config. saved Byte 1: Control Register 1 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 0 PLL1_SS_DC Select for down or center SS 0 = Down spread, 1 = Center spread 5 0 PLL3_SS_DC Select for down or center SS 0 = Down spread, 1 = Center spread 4 0 PLL3_CFB3 CFB Bit [4:1] only applies when SRC_Main_SEL = 0 (Byte 0, bit 2 =0) See Table 4 on page 9 for Configuration.3 0 PLL3_CFB2 2 1 PLL3_CFB1 1 0 PLL3_CFB0 0 1 RESERVED RESERVED Byte 2: Control Register 2 Bit @Pup Name Description 7 1 REF_OE Output enable for REF 0 = Output Disabled, 1 = Output Enabled 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED 4 1 RESERVED RESERVED 3 1 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 3: Control Register 3 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED
Byte 3: Control Register 3 Byte 4: Control Register 4 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 1 SATA_OE Output enable for SATA 0 = Output Disabled, 1 = Output Enabled 5 1 SRC_OE Output enable for SRC 0 = Output Disabled, 1 = Output Enabled 4 1 DOT96_OE Output enable for DOT96 0 = Output Disabled, 1 = Output Enabled 3 1 CPU1_OE Output enable for CPU1 0 = Output Disabled, 1 = Output Enabled 2 1 CPU0_OE Output enable for CPU0 0 = Output Disabled, 1 = Output Enabled 1 1 PLL1_SS_EN Enable PLL1s spread modulation, 0 = Spread Disabled, 1 = Spread Enabled 0 1 PLL3_SS_EN Enable PLL3s spread modulation 0 = Spread Disabled, 1 = Spread Enabled Byte 5: Control Register 5 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED Byte 6: Control Register 6 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 REF Bit1 REF slew rate control (see Byte 13 for Slew Rate Bit 0 and Bit 2) 0 = High, 1 = Low 4 0 RESERVED RESERVED 3 0 27MHz Bit 1 27MHz slew rate control (see Byte 13 for Slew Rate Bit 0 and Bit 2) 0 = High, 1 = Low 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED
Byte 7: Vendor ID Bit @Pup Name Description 7 0 Rev Code Bit 3 Revision Code Bit 3 6 1 Rev Code Bit 2 Revision Code Bit 2 5 0 Rev Code Bit 1 Revision Code Bit 1 4 0 Rev Code Bit 0 Revision Code Bit 0 3 1 Vendor ID bit 3 Vendor ID Bit 3 2 0 Vendor ID bit 2 Vendor ID Bit 2 1 0 Vendor ID bit 1 Vendor ID Bit 1 0 0 Vendor ID bit 0 Vendor ID Bit 0 Byte 8: Control Register 8 Bit @Pup Name Description 7 1 Device_ID3 RESERVED 6 0 Device_ID2 RESERVED 5 0 Device_ID1 RESERVED 4 0 Device_ID0 RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 1 27M_non-SS_OE Output enable for 27M_non-SS 0 = Output Disabled, 1 = Output Enabled 0 1 27M_SS_OE Output enable for 27M_SS 0 = Output Disabled, 1 = Output Enabled Byte 9: Control Register 9 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 1 RESERVED RESERVED 4 0 TEST _MODE_SEL Test mode select either REF/N or tri-state 0 = All outputs tri-state, 1 = All output REF/N 3 0 TEST_MODE_ENTRY Allows entry into test mode 0 = Normal Operation, 1 = Enter test mode(s) 2 1 I2C_VOUT<2> Amplitude confi gurations differential clocks I2C_VOUT[2:0] 000 = 0.30V 001 = 0.40V 010 = 0.50V 011 = 0.60V 100 = 0.70V 101 = 0.80V (default) 110 = 0.90V 111 = 1.00V 1 0 I2C_VOUT<1> 0 1 I2C_VOUT<0> Byte 10: Control Register 10 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED
Byte 13: Control Register 13 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 10: Control Register 10 (continued) Bit @Pup Name Description Byte 11: Control Register 11 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 1 CPU1_iAMT_EN CPU1 iAMT Clock Enabled 0 = Disabled, 1 = Enabled 1 1 PCI-e_GEN2 PCI-e_Gen2 Compliant 0 = non Gen2, 1= Gen2 Compliant 0 1 RESERVED RESERVED Byte 12: Byte Count Bit @Pup Name Description 7 0 BC7 Byte count register for block read operation. The default value for Byte count is 15. In order to read beyond Byte 15, the user should change the byte count limit.to or beyond the byte that is desired to be read.
60 B C 6
50 B C 5
40 B C 4
31 B C 3
21 B C 2
11 B C 1
01 B C 0
Bit @Pup Name Description 7 1 REF_Bit2 Drive Strength Control - Bit[2:0], Note: See Byte 6 Bit 5 for REF Slew Rate Bit 1 and Byte 6 Bit 3 for 27MHz Slew Rate Bit 1 Normal mode default ‘101’ Wireless Friendly Mode default to ‘111’
61 R E F _ B i t 0
5 1 27MHz_NSS_Bit2 4 1 27MHz_NSS_Bit0 3 1 27MHz_SS_Bit2 2 1 27MHz_SS_Bit0 1 0 RESERVED RESERVED
Table 4. Pin 6 and 7 Configuration Table
40 O T P _ 4 O T P _ I D
20 O T P _ 2
10 O T P _ 1
00 O T P _ 0
0000 N / A N / AN / A
0001 N / A N / AN / A
1011 N / A N / AN / A
1100 N / A N / AN / A
1101 N / A N / AN / A
1110 N / A N / AN / A
1111 N / A N / AN / A
Table 5. Output Driver Status during 27_OE# Table 6. Output Driver Status
Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD_3.3V Main Supply Voltage – 4.6 V VDD_IO IO Supply Voltage 3.465 V VIN Input Voltage Relative to V SS –0.5 4.6 V DC TS Temperature, Storage Non-functional –65 150 °C TA Temperature, Operating Ambient Functional -40 85 °C TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case MIL-STD-883E Method 1012.1 – 20 °C/ W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/ W ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V UL-94 Flammability Rating At 1/8 in. V–0 MSL Moisture Sensitivity Level 1 Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Parameter Description Condition Min. Max. Unit VDD core 3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V V IH 3.3V Input High Voltage (SE) 2.0 V DD + 0.3 V VIL 3.3V Input Low Voltage (SE) V SS – 0.3 0.8 V VIHI2C Input High Voltage SDATA, SCLK 2.2 – V VILI2C Input Low Voltage SDATA, SCLK – 1.0 V VIH_FS FS Input High Voltage 0.7 VDD+0.3 V VIL_FS FS Input Low Voltage V SS – 0.3 0.35 V IIH Input High Leakage Current Except internal pull-down resistors, 0 < V IN < VDD –5 A IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN < VDD –5 – A VOH 3.3V Output High Voltage (SE) I OH = –1 mA 2.4 – V VOL 3.3V Output Low Voltage (SE) I OL = 1 mA – 0.4 V VDD IO Low Voltage IO Supply Voltage 1 3.465 V IOZ High-impedance Output Current –10 10 A CIN Input Pin Capacitance 1.5 5 pF COUT Output Pin Capacitance 6p F LIN Pin Inductance – 7 nH VXIH Xin High Voltage 0.7V DD VDD V VXIL Xin Low Voltage 0 0.3V DD V IDD_PD Power Down Current – 1 mA IDD_3.3V Dynamic Supply Current All outputs enabled. SE clocks with 8” traces. Differential clocks with 7” traces. Loading per CK505 spec. –6 5 m A IDD_VDD_IO Dynamic Supply Current All outputs enabled. SE clocks with 8” traces. Differential clocks with 7” traces. Loading per CK505 spec. –2 5 m A
Parameter Description Condition Min. Max. Unit Crystal TDC XIN Duty Cycle The device operates reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification 47.5 52.5 % TPERIOD XIN Period When XIN is dr iven from an external clock source 69.841 71.0 ns TR/TF XIN Rise and Fall Times Measured between 0.3V DD and 0.7VDD –1 0 . 0 n s TCCJ XIN Cycle to Cycle Jitter As an average over 1- s duration – 500 ps CPU at 0.7V TDC CPUT and CPUC Duty Cycle Measured at 0V differential 45 55 % TPERIOD 100 MHz CPUT and CPUC Period Measur ed at 0V differential at 0.1s 9.99900 10.00100 ns TPERIOD 133 MHz CPUT and CPUC Period Measur ed at 0V differential at 0.1s 7.49925 7.50075 ns TPERIODSS 100 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s 10.02406 10.02607 ns TPERIODSS 133 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s 7.51804 7.51955 ns TPERIODAbs 100 MHz CPUT and CPUC Absolute period Measured at 0V differential at 1 clock 9.91400 10.0860 ns TPERIODAbs 133 MHz CPUT and CPUC Absolute period Measured at 0V differential at 1 clock 7.41425 7.58575 ns TPERIODSSAbs 100 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential at1 clock 9.914063 10.1362 ns TPERIODSSAbs 133 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential at1 clock 7.41430 7.62340 ns TCCJ CPU Cycle to Cycle Jitter Measured at 0V differential – 85 ps Skew CPU0 to CPU1 skew Measured at 0V differential – 100 ps LACC Long-term Accuracy Measured at 0V differential – 100 ppm TR / TF CPU Rising/Falling Slew rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV SRC at 0.7V TDC SRC Duty Cycle Measured at 0V differential 45 55 % TPERIOD 100 MHz SRC Period Measured at 0V differential at 0.1s 9.99900 10.0010 ns TPERIODSS 100 MHz SRC Period, SSC Measured at 0V differential at 0.1s 10.02406 10.02607 ns TPERIODAbs 100 MHz SRC Absolute Period Measured at 0V differential at 1 clock 9.87400 10.1260 ns TPERIODSSAbs 100 MHz SRC Absolute Period, SSC Meas ured at 0V differential at 1 clock 9.87406 10.1762 ns TSKEW(window) Any SRC Clock Skew from the earliest bank to the latest bank Measured at 0V differential – 3.0 ns TCCJ SRC Cycle to Cycle Jitter Measured at 0V differential – 125 ps LACC SRC Long Term Accuracy Measured at 0V differential – 100 ppm TR / TF SRC Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV DOT96 at 0.7V
TDC DOT96 Duty Cycle Measured at 0V differential 45 55 % TPERIOD DOT96 Period Measured at 0V differential at 0.1s 10.4156 10.4177 ns TPERIODAbs DOT96 Absolute Period Measured at 0V differential at 0.1s 10.1656 10.6677 ns TCCJ DOT96 Cycle to Cycle Jitter Measured at 0V differential at 1 clock – 250 ps LACC DOT96 Long Term Accuracy Measured at 0V differential at 1 clock – 100 ppm TR / TF DOT96 Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV 27M_NSS/27_SS at 3.3V T DC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Spread 27M Period Measurem ent at 1.5V 37.03594 37.03813 ns Spread Enabled 27M Period Measur ement at 1.5V 37.12986 37.13172 ns TR / TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 300 ps LACC 27_M Long Term Accuracy Measured at crossing point V OX –5 0 p p m REF TDC REF Duty Cycle Measurement at 1.5V 45 55 % TPERIOD REF Period Measurement at 1.5V 69.82033 69.86224 ns TPERIODAbs REF Absolute Period Measurement at 1.5V 68.83429 70.84826 ns THIGH REF High time Measurement at 2V 29.97543 38.46654 ns TLOW REF Low time Measurement at 0.8V 29.57543 38.26654 ns TR / TF REF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TSKEW REF Clock to REF Clock Measurement at 1.5V – 500 ps TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 1000 ps LACC Long Term Accuracy Measurement at 1.5V – 100 ppm ENABLE/DISABLE and SET-UP T STABLE Clock Stabilization from Power-up – 1.8 ms TSS Stopclock Set-up Time 10.0 – ns Parameter Description Condition Min. Max. Unit
Ordering Information
Part Number Package Type Product Flow Lead-free SL28774ELI 32-pin QFN Industrial, -40 to 85C SL28774ELIT 32-pin QFN–Tape and Reel Industrial, -40 to 85C This device is Pb free and RoHS compliant. Package Diagrams 32-Lead QFN 5x 5mm (Saw Version) SL 28 774 EL I - T Temperature Designator Package Designator L : QFN Revision Number A = 1 st Silicon Generic Part Number Designated Family Number Company Initials Packaging Designator for Tape and Reel
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, an d disclaims responsibility for any consequences resulting fr om the use of information included herein. Additionally, Silicon Laboratories as sumes no responsibility for the functioning of undescribed fe atures or param- eters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Document Title: SL28774 PC EProClock® Generator for Intel Calpella Chipset REV. Issue Date Orig. of Change Description of Change 1.0 07/22/08 JMA Initial Release 1.1 09/08/09 JMA Removed Preliminary 1.2 10/02/09 JMA Updated note in package diagram 1.3 01/05/10 JMA 1. Added Note in package diagram 2. Updated text content 3. Added information on trace length in Figure 8 4. Removed CPU Driven Figures 5. Updated VDD_IO spec to 3.465 maximum value 6. Edited CK_PWRGD to CKPWRGD