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Document overview
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Technical content
Features
- I n t e l® CK505 Rev. 1.0 Compliant
- Low power push-pull type differential output buffers
- PCI-Express Gen 2 Compliant SRC clocks (exclude SRC0 and SRC1)
- 8-step programmable drive strength for single-ended clocks
- Differential CPU clocks with selectable frequency
- 100 MHz Differential SRC clocks
- 100 MHz Differential LCD clock
- 96 MHz Differential DOT clock
- 48 MHz USB clock
- 33 MHz PCI clocks
- 27MHz non-spread Video clock
- 25 MHz Video clocks
- 1396 Firewire clock
- Buffered Reference Clock 14.318 MHz
- 14.318 MHz Crystal Input or Clock Input
- Low-voltage frequency select input 2C support with readback capabilities
- Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction
- Industrial Temperature -40°C to 85°C
- 3.3V Power supply
- 56-pin TSSOP packages CPU SRC PCI REF DOT96 USB_48 LCD SE x2 / x3 x4/9 x6 x 1 x 1 x 1 x1 x2 Block Diagram Pin Configuration * 100K-ohm Internal Pull Down
56 TSSOP Pin Definition
Pin No. Name Type Description 1 PCI0/OE#_0/2_A I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC0 or SRC2. (Default PCI0, 33MHz clock) 2 VDD_PCI PWR 3.3V Power supply for PCI PLL. 3 PCI1/OE#_1/4_B I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC1 or SRC4. (Default PCI1, 33MHz clock) 4 PCI2/TME I/O, SE 3.3V tolerance input for overclocking enable pin/3.3V, 33MHz clock. (Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)
5 PCI3/CFG0 I/O, SE,
3.3V tolerant input for CPU frequency selection/3.3V 33MHz clock. (Refer to DC Electrical Specifications table for Vil_PCI3/CFG0 and Vih_PCI3/CFG0 specifications). 6 PCI4/SRC5_EN I/O, SE 3.3V tolerant input to enable SRC5/3.3V, 33MHz clock. (Sampled on the CKPWRGD assertion) 1 = SRC5, 0 = CPU_STP# 7 PCIF/ITP_EN I/O, SE 3.3V LVTTL input to ena ble SRC8 or CPU2_ITP/3.3V, 33MHz clock. (Sampled on the CKPWRGD assertion) 1 = CPU2_ITP, 0 = SRC8 8 VSS_PCI GND Ground for outputs. 9 VDD_48 PWR 3.3V Power supply for outputs and PLL. 10 USB_48/FSA I/O 3.3V tolerant input for CPU fre quency selection/fixed 3.3V, 48MHz clock output. (Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications) 11 VSS_48 GND Ground for outputs. 12 VDD_IO PWR 0.7V Power supply for outputs. 13 SRC0/DOT96 O, DIF 100MHz Diff erential serial reference clocks/Fixed 96MHz clock output. (Selected via I2C default is SRC0) 14 SRC0#/DOT96# O, DIF 100MHz Di fferential serial reference clocks/Fixed 96MHz clock output. (Selected via I2C default is SRC0) 15 VSS_IO GND Ground for PLL2. 16 VDD_PLL3 PWR 3.3V Power supply for PLL3
17 SRC1/LCD100/SE1 O, DIF,
100MHz Differential serial reference clocks/100MHz LCD video clock/SE1 clocks. (Default SRC1, 100MHz clock)
18 SRC1#/LCD100#/SE2 O, DIF,
100MHz Differential serial reference clocks/100MHz LCD video clock/SE2 clocks. (Default SRC1, 100MHz clock) 19 VSS_PLL3 GND Ground for PLL3. 20 VDD_PLL3_IO PWR IO Power supply for PLL3 outputs. 21 SRC2/SATA O, DIF 100MHz Differen tial serial reference clocks. 22 SRC2#/SATA# O, DIF 100MHz Differen tial serial reference clocks. 23 VSS_SRC GND Ground for outputs.
24 SRC3/OE#_0/2_B I/O,
100MHz Differential serial reference clocks / 3.3V OE#_0/2_B, input, mappable via I2C to control either SRC0 or SRC2. (Default SRC3, 100MHz clock)
25 SRC3#OE#_1/4_B I/O,
100MHz Differential serial reference clocks / 3.3V OE#_1/4_B input, mappable via I2C to control either SRC1 or SRC4. (Default SRC3, 100MHz clock)
26 VDD_SRC_IO PWR IO power supply for SRC outputs. 27 SRC4 O, DIF 100MHz Differenti al serial reference clocks. 28 SRC4# O, DIF 100MHz Differenti al serial reference clocks.
29 SRC5#CPU_STP# I/O,
3.3V tolerant input for stopping CPU outputs/100MHz Differential serial reference clocks.
30 SRC5/PCI_STP# I/O,
3.3V tolerant input for stopping PCI and SRC outputs/100MHz Differential serial reference clocks. 31 VDD_SRC PWR 3.3V Power supply for SRC PLL. 32 SRC6# O, DIF 100MHz Differenti al serial reference clocks. 33 SRC6 O, DIF 100MHz Differenti al serial reference clocks. 34 VSS_SRC GND Ground for outputs.
35 SRC7#/OE#_6 I/O,
100MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6. (Default SRC7, 100MHz clock).
36 SRC7/OE#_8 I/O,
100MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8. (Default SRC7, 100MHz clock). 37 VDD_SRC_IO PWR 0.7V power supply for SRC outputs. 38 SRC8#/CPU2#_ITP# O, DIF Selectable differential CP U or SRC clock output. ITP_EN = 0 at CKPWRGD assertion = SRC8 ITP_EN = 1 @ CKPWRGD assertion = CPU2 (Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2) 39 SRC8/CPU2_ITP O, DIF Selectable differential CP U or SRC clock output. ITP_EN = 0 at CKPWRGD assertion = SRC8 ITP_EN = 1 @ CKPWRGD assertion = CPU2 (Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2) 40 IO_VOUT PWR Integrated Li near Regulator Control. 41 VDD_CPU_IO PWR IO Power supply for CPU outputs. 42 CPU1# O, DIF Differential CPU clock outputs. ( Note: CPU1 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2) 43 CPU1 O, DIF Differential CPU clock outputs. ( Note: CPU1 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2) 44 VSS_CPU GND Ground for outputs. 45 CPU#0 O, DIF Differential CPU clock outputs. 46 CPU0 O, DIF Differential CPU clock outputs. 47 VDD_CPU PWR 3.3V Power supply for CPU PLL. 48 CKPWRGD/PD# I 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN. After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for asserting power down (active LOW). 49 FSB/TEST_MODE I 3.3V tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when in test mode 0 = Tri-state, 1 = Ref/N. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 50 VSS_REF GND Ground for outputs. 51 XOUT O, SE 14.318MHz Crystal output. (Float XOUT if using CLKIN) 52 XIN/CLKIN I 14.318MHz Crystal input or 3.3V, 14.318MHz input clock signal. 53 VDD_REF PWR 3.3V Power supply for outputs and also maintains SMBUS registers during power-down.
56 TSSOP Pin Definition (continued)
Pin No. Name Type Description
CKPWRGD transitions are ignored except in test mode. byte is encoded in the command code described in Table 2. slave receiver address is 11010010 (D2h). 54 REF0/FSC/TEST_SEL I/O 3.3V tolerant input for CPU frequency selection/fixed 14.318MHz clock output. to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications. 55 SMB_DATA I/O SMBus compatible SDATA. 56 SMB_CLK I SMBus compatible SCLOCK. Table 1. Frequency Select Pin (FSA, FSB and FSC) Table 2. Command Code Definition Table 3. Block Read and Block Write Protocol
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
19 Acknowledge from slave 19 Acknowledge from slave
28 Acknowledge from slave 27:21 Slave address–7 bits
37 Acknowledge from slave 29 Acknowledge from slave
46 Acknowledge from slave 38 Acknowledge
Table 4. Byte Read and Byte Write Protocol
29 Stop 28 Read
29 Acknowledge from slave
38 NOT Acknowledge
39 Stop
Table 3. Block Read and Block Write Protocol (continued)
Byte 0: Control Register 0 Bit @Pup Name Description
7 HW FS_C CPU Frequency Select Bit, set by HW
6 HW FS_B CPU Frequency Select Bit, set by HW
5 HW FS_A CPU Frequency Select Bit, set by HW
4 0 iAMT_EN Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP 0 = Legacy Mode, 1 = iAMT Enabled, Sticky 1 3 0 RESERVED RESERVED 2 0 SRC_MAIN_SEL Select source for SRC clock, 0 = SRC_MAIN = PLL1, PLL3_CFB Table applies 1 = SRC_MAIN = PLL3, PLL3_CFB Table does not apply 1 0 SATA_SEL Select source of SATA clock 0 = SATA SRC_MAIN, 1= SATA PLL2 0 1 PD_Restore Save Config. In powerdown 0 = Config. Cleared, 1 = Config. Saved Byte 1: Control Register 1 Bit @Pup Name Description 7 0 SRC0_SEL Select for SRC0 or DOT96, 0 = SRC0, 1 = DOT96 6 0 PLL1_SS_DC Select for down or center SS, 0 = Down spread, 1 = Center spread 5 0 PLL3_SS_DC Select for down or center SS, 0 = Down spread, 1 = Center spread 4 0 PLL3_CFB3 Bit 4:1 only apply when SRC_SEL=0 0000 = PLL3 Disable Default PLL3 OFF, SRC1 = SRC_MAIN 0001 = 100 MHz 0.5% SSC Stby PLL3 ON, SRC1 = SRC_MAIN 0010 = 100 MHz 0.5% SSC Only SRC1 sourced from PLL3 0011 = 100 MHz 1.0% SSC Only SRC1 sourced from PLL3 0100 = 100 MHz 1.5% SSC Only SRC1 sourced from PLL3 0101 = 100 MHz 2.0% SSC Only SRC1 sourced from PLL3 0110 = RESERVED Note: SE clocks required to be 0111 = RESERVED enabled through Byte 8 Bit[1:0] 1000 = 1394A(24.576M) on SE1 and SE2 1001 = 1394A(24.576M) on SE1 and 1394B (98.304M) on SE2 1010 = 1394B on SE1 and SE2 1011 = 27MHz_NSS on SE1 and SE2 1100 = 25MHz on SE1 and SE2 1101 = 25MHz on SE1 and SE2 Disabled (set whenPCI3/CFB0 is set high to config to HW mode 3) 1110 = RESERVED 1111 = RESERVED 3 0 PLL3_CFB2 2 0 PLL3_CFB1 1 1 PLL3_CFB0 0 1 PCI_SEL Select PCI Clock sour ce from PLL1 or SRC_MAIN 0 = PLL1, 1 = SRC_MAIN Byte 2: Control Register 2 Bit @Pup Name Description 7 1 REF_OE Output enable for REF 0 = Output Disabled, 1 = Output Enabled 6 1 USB_OE Output enable for USB 0 = Output Disabled, 1 = Output Enabled
5 1 PCIF0_OE Output enable for PCIF0 0 = Output Disabled, 1 = Output Enabled 4 1 PCI4_OE Output enable for PCI4 0 = Output Disabled, 1 = Output Enabled 3 1 PCI3_OE Output enable for PCI3 0 = Output Disabled, 1 = Output Enabled 2 1 PCI2_OE Output enable for PCI2 0 = Output Disabled, 1 = Output Enabled 1 1 PCI1_OE Output enable for PCI1 0 = Output Disabled, 1 = Output Enabled 0 1 PCI0_OE Output enable for PCI0 0 = Output Disabled, 1 = Output Enabled Byte 2: Control Register 2 (continued) Bit @Pup Name Description Byte 3: Control Register 3 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED 4 1 SRC8/ITP_OE Output enable for SRC8 or ITP, 0 = Output Disabled, 1 = Output Enabled 3 1 SRC7_OE Output enable for SRC7 0 = Output Disabled, 1 = Output Enabled 2 1 SRC6_OE Output enable for SRC6 0 = Output Disabled, 1 = Output Enabled 1 1 SRC5_OE Output enable for SRC5 0 = Output Disabled, 1 = Output Enabled 0 1 SRC4_OE Output enable for SRC4 0 = Output Disabled, 1 = Output Enabled Byte 4: Control Register 4 Bit @Pup Name Description 7 1 SRC3_OE Output enable for SRC3 0 = Output Disabled, 1 = Output Enabled 6 1 SRC2/SATA_OE Output enable for SATA/SRC2 0 = Output Disabled, 1 = Output Enabled 5 1 SRC1_OE Output enable for SRC 0 = Output Disabled, 1 = Output Enabled 4 1 SRC0/DOT96_OE Output enable for SRC0/DOT96 0 = Output Disabled, 1 = Output Enabled 3 1 CPU1_OE Output enable for CPU1 0 = Output Disabled, 1 = Output Enabled 2 1 CPU0_OE Output enable for CPU0 0 = Output Disabled, 1 = Output Enabled 1 1 PLL1_SS_EN Enable PLL1’s spread modulation, 0 = Spread Disabled 1 = Spread Enabled 0 1 PLL3_SS_EN Enable PLL3’s spread modulation 0 = Spread Disabled, 1 = Spread Enabled
Byte 5: Control Register 5 Bit @Pup Name Description 7 0 OE#_0/2_EN_A Enable OE#_0/2 (clk req) 0 = Disabled OE#_0/2, 1 = Enabled OE#_0/2, 6 0 OE#_0/2_SEL_A Set OE#_0/2 SRC0 or SRC2 0 = OE#_0/2SRC0, 1 = OE#_0/2SRC2 5 0 OE#_1/4_EN_A Enable OE#_1/4 (clk req) 0 = Disabled OE#_1/4, 1 = Enabled OE#_1/4, 4 0 OE#_1/4_SEL_A Set OE#_1/4 SRC1 or SRC4 0 = OE#_1/4SRC1, 1 = OE#_1/4SRC4 3 0 OE#_0/2_EN_B Enable OE#_0/2 (clk req) 0 = Disabled OE#_0/2 1 = Enabled OE#_0/2 2 0 OE#_0/2_SEL_B Set OE#_0/2 SRC0 or SRC2 0 = OE#_0/2SRC0, 1 = OE#_0/2SRC2 1 0 OE#_1/4_EN_B Enable OE#_1/4 (clk req) 0 = Disabled OE#_1/4, 1 = Enabled OE#_1/4, 0 0 OE#_1/4_SEL_B Set OE#_1/4 SRC1 or SRC4 0 = OE#_1/4SRC1, 1 = OE#_1/4SRC4 Byte 6: Control Register 6 Bit @Pup Name Description 7 0 OE#_6_EN Enable OE#_6 (clk req) SRC6 6 0 OE#_8_EN Enable OE#_8 (clk req) SRC8 5 0 OE#_9_EN Enable OE#_9 (clk req) SRC9 4 0 OE#_10_EN Enable OE#_10 (clk req) SRC10 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 LCD_100_STP_CTRL Allows control of LCD_100 with assertion of PCI_STP# 0 = Free runningLCD_100, 1 = Stopped with PCI_STP# 0 0 SRC_STP_CTRL Allows control of SRC with assertion of PCI_STP# 0 = Free running SRC 1 = Stopped with PCI_STP# Byte 7: Vendor ID Bit @Pup Name Description 7 0 Rev Code Bit 3 Revision Code Bit 3 6 0 Rev Code Bit 2 Revision Code Bit 2 5 0 Rev Code Bit 1 Revision Code Bit 1 4 1 Rev Code Bit 0 Revision Code Bit 0 3 1 Vendor ID bit 3 Vendor ID Bit 3 2 0 Vendor ID bit 2 Vendor ID Bit 2 1 0 Vendor ID bit 1 Vendor ID Bit 1 0 0 Vendor ID bit 0 Vendor ID Bit 0
Byte 8: Control Register 8 Bit @Pup Name Description 7 0 Device_ID3 0000 = CK505 Yellow Cover Device, 56-pin TSSOP 0001 = CK505 Yellow Cover Device, 64-pin TSSOP 0010 = CK505 Yellow Cover Device, 48-pin QFN (reserved) 0011 = CK505 Yellow Cover Device, 56-pin QFN (reserved) 0100 = CK505 Yellow Cover Device, 64-pin QFN (reserved) 0101 = CK505 Yellow Cover Device, 72-pin QFN (reserved) 0110 = CK505 Yellow Cover Device, 48-pin SSOP (reserved) 0111 = CK505 Yellow Cover Device, 56-pin SSOP (reserved) 1000 = Reserved 1001 = Reserved 1010 = Reserved 1011 = Reserved 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved 6 0 Device_ID2 5 0 Device_ID1 4 0 Device_ID0 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 SE1_OE SE1 Output enable 0 = Output Disabled, 1 = Output Enabled 0 0 SE2_OE SE2 Output enable 0 = Output Disabled, 1 = Output Enabled Byte 9: Control Register 9 Bit @Pup Name Description 7 0 PCIF0_STP_CTRL Allows control of PCIF0 with assertion of PCI_STP# 0 = Free running PCIF, 1 = Stopped with PCI_STP#
6 HW TME_STRAP Trusted mode enable strap status, 0 = normal, 1 = no overclocking
5 1 REF_Bit1 REF drive strength control, See Byte 18 for more setting 0 = Low, 1 = High 4 0 TEST_MODE_SEL Mode select either REF/N or tri-state 0 = All output tri-state, 1 = All output REF/N 3 0 TEST_MODE_ENTRY Allow entry into test mode 0=Normal operation, 1=Enter test mode 2 1 IO_VOUT2 IO_VOUT[2,1,0] 000 = 0.3V 001 = 0.4V 010 = 0.5V 011 = 0.6V 100 = 0.7V 101 = 0.8V, Default 110 = 0.9V 111 = 1.0V
10 I O _ V O U T 1
01 I O _ V O U T 0Byte 10: Control Register 10
Bit @Pup Name Description
7 HW SRC5_EN_STRAP Read only bit for SRC5_EN_STRAP
0 = CPU/PCI_STP enabled, 1 = SRC5 pair enabled 6 1 PLL3_EN PLL3 Enabled 0 = PLL3 disabled, 1 = PLL3 enabled 5 1 PLL2_EN PLL2 Enabled 0 = PLL2 disabled, 1 = PLL2 enabled 4 1 SRC_DIV_EN SRC Divider Enabled 0 = SRC Divider disabled, 1 = SRC Divider enabled
3 1 PCI_DIV_EN PCI Divider Enabled 0 = PCI Divider disabled, 1 = PCI Divider enabled 2 1 CPU_DIV_EN CPU Divider Enabled 0 = CPU Divider disabled, 1 = CPU Divider enabled 1 1 CPU1_STP_CRTL Allow control of CPU1 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# 0 1 CPU0_STP_CRTL Allow control of CPU0 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Byte 10: Control Register 10 (continued) Bit @Pup Name Description Byte 11: Control Register 11 Bit @Pup Name Description
7 HW PCI3_CFG1
6 HW PCI3_CFG0
5 0 25MHz_EN_SE1 25MHz Output Enabled applies to Powerdown / M1 (Only applies when PCI3/CGFG0 strap is set high to enter HW mode 3) 0 = 25MHz disabled in Powerdown / M1 1 = 25MHz enabled in Powerdown / M1; Sticky 1 4 1 RESERVED RESERVED 3 0 CPU2_AMT_EN 2 1 CPU1_AMT_EN 1 1 PCI-E_GEN2 PCI-E_Gen2 Compliant ( Read Only bit) 0 = non Gen2, 1= Gen2 Compliant 0 1 CPU2_STP_CRTL Allow control of CPU2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Output SSC Output SSC 00 x Low 0 -Def CPU / SRC / PCI33 Dow n USB NA 01 x Mid 1 CPU Dow n USB NA 10 0 High 2 CPU Center USB NA PLL2CFG [1:0] PCI3/ CGF0 Mode PLL1PCI2/T ME PCIF0/ITP_EN AMT_EN CPU2_AMT_EN CPU1_AMT_EN Description x1 0 0 R e s e r v e d x 1 0 1 CPU1 = M1 Clock 1 1 1 0 CPU2 - M1 Clock 1 1 1 1 CPU1 and CPU2 = M1 Clock Byte 12: Byte Count Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 BC5 Byte count 4 0 BC4 Byte count 3 1 BC3 Byte count 2 1 BC2 Byte count 1 0 BC1 Byte count 0 1 BC0 Byte count
Byte 13: Control Register 13 Bit @Pup Name Description 7 1 USB_Bit1 USB drive strength control, See Byte 18 for more setting 0 = Low, 1= High 6 1 PCI/PCIF_Bit1 PCI drive strength control, See Byte 18 for more setting 0 = Low, 1 = High 5 0 PLL1_Spread Select percentage of spread for PLL1 0 = 0.5%, 1=0.45% 4 0 SATA_SS_EN Enable SATA spread modulation, 0 = Spread Disabled 1 = Spread Enabled 3 1 EN_CFG0_SET By defalult CFG0 pin strap sets the SMBus initial values to select the HW mode. When this bit is written0, subsequent SMBus accesses is the Lathes Open state, can overwrite the CFG0 pin setting into the SMBus bits and set the mode before the M0 state: specifically B0b2, B1b[6,4,3], B9b1, B11b5 2 1 SE1/SE2_Bit1 SE1 and SE2 drive strength control, See Byte 18 for more setting 0 = Low, 1 = High 1 1 RESERVED RESERVED 0 1 SW_PCI SW PCI_ STP# Function 0 = SW PCI_STP assert, 1 = SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. Byte 14: Control Register 14 Bit @Pup Name Description 7 0 CPU_DAF_N7 If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[C:A] register will be used. When it is set, the frequency ratio stated in the FSEL[2:0] register will be used 6 0 CPU_DAF_N6 5 0 CPU_DAF_N5 4 0 CPU_DAF_N4 3 0 CPU_DAF_N3 2 0 CPU_DAF_N2 1 0 CPU_DAF_N1 0 0 CPU_DAF_N0 Byte 15: Control Register 15 Bit @Pup Name Description 7 0 CPU_DAF_N8 See Byte 14 for description 6 0 CPU_DAF_M6 If Prog_CPU_EN is set, the va lues programmed are in CPU_FSEL_N[8:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[C:A] register will be used. When it is set, the frequency ratio stated in the FSEL[2:0] register will be used 5 0 CPU_DAF_M5 4 0 CPU_DAF_M4 3 0 CPU_DAF_M3 2 0 CPU_DAF_M2 1 0 CPU_DAF_M1 0 0 CPU_DAF_M0 Byte 16: Control Register 16 Bit @Pup Name Description
50 P C I - E _ N 5
40 P C I - E _ N 4
30 P C I - E _ N 3
20 P C I - E _ N 2
10 P C I - E _ N 1
00 P C I - E _ N 0
10 R E F _ B i t 2
00 R E F _ B i t 0
Table 5. Output Driver Status during PCI-STP# and CPU-STP#
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.
- “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively.
- “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[E:A]. See Table 1, Frequency Select Table for the Gear Constant for each Frequency selection. The PCI Express only allows user control of the N register, the M value is fixed and documented in Table 1, Frequency Select Table. In this mode, the user writes the desired N and M values into the DAF I2C registers. The user cannot change only the M value and must change both the M and the N values at the same time, if they require a change to the M value. The user may change only the N value. Associated Register Bits
- CPU_DAF Enable – This bit enables CPU DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the CPU_DAF_N register. Note that the CPU_DAF_N and M register must contain valid values before CPU_DAF is set. Default = 0, (No DAF).
- CPU_DAF_N – There are nine bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, (0000). The allowable values for N are detailed in Table 1, Frequency Select Table.
- CPU DAF M – There are 7 bits (for 128 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, the allowable values for M are detailed in Table 1, Frequency Select Table
- SRC_DAF Enable – This bit enables SRC DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the SRC_DAF_N register. Note that the SRC_DAF_N register must contain valid values before SRC_DAF is set. Default = 0, (No DAF).
- SRC_DAF_N – There are nine bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, (0000). The allowable values for N are detailed in Table 1, Frequency Select Table. Smooth Switching The device contains one smooth switch circuit that is shared by the CPU PLL and SRC PLL. The smooth switch circuit ensures that when the ou tput frequency changes by overclocking, the transition from the old frequency to the new frequency is a slow, smooth transition containing no glitches. The rate of change of output frequency when using the smooth switch circuit is less than 1 MHz/0.667 s. The frequency overshoot and undershoot is less than 2%. The Smooth Switch circuit assigns auto or manual. In Auto mode, clock generator assigns smooth switch automatically when the PLL does overclocking. For manual mode, assign the smooth switch circuit to PLL via Smbus. By default the smooth switch circuit is se t to auto mode. PLL can be over-clocked when it does not have control of the smooth switch circuit but it is not guaranteed to transition to the new frequency without large frequency glitches. Do not enable over-clocking and change the N values of both PLLs in the same SMBUS block write and use smooth switch mechanism on spread spectrum on/off. PD_RESTORE If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PD# LOW, the SL28506-2 initiates a full reset. The result of this is that the clock chip emulates a cold power on start and goes to the “Latches Open” state. If the PD_RESTORE bit is set to a ‘1’ then the configuration is stored upon PD# asserted LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then the PD_RESTORE bit must be ignored. In other words, in Intel iAMT mode, PD# reset is not allowed. PD# (Power down) Clarification The CKPWRGD/PD# pin is a dual-function pin. During initial power up, the pin functions as CKPWRGD. Once CKPWRGD has been sampled HIGH by the clock chip, the pin assumes PD# functionality. The PD# pin is an asynchronous active LOW input used to shut off all clocks cleanly before shutting off power to the device. This signal is synchronized internally to the device before powering down the clock synthesizer. PD# is also an asynchronous in put for powering up the system. When PD# is asserted LOW, clocks are driven to a LOW value and held before turning off the VCOs and the crystal oscillator. PD# (Power down) Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must held LOW. When PD mode is desired as the initial power on state, PD must be asserted HIGH in less than 10 s after asserting CKPWRGD. PD# Deassertion The power up latency is less than 1.8 ms. This is the time from the deassertion of the PD# pin or the ramping of the power supply until the time that stable clocks are generated from the clock chip. All differential outputs stopped in a three-state condition, resulting from power down are driven high in less than 300 s of PD# deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs are enabl ed within a few clock cycles of each clock. Figure 4 is an example showing the relationship of clocks coming up.
Figure 11. BSEL Serial Latching Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Parameter Description Condition Min. Max. Unit VDD core 3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V VIH 3.3V Input High Voltage (SE) 2.0 V DD + 0.3 V VIL 3.3V Input Low Voltage (SE) V SS – 0.3 0.8 V VIHI2C Input High Voltage SDATA, SCLK 2.2 – V VILI2C Input Low Voltage SDATA, SCLK – 1.0 V VIH_FS FS_[A,B] Input High Voltage 0.7 1.5 V VIL_FS FS_[A,B] Input Low Voltage V SS – 0.3 0.35 V VIHFS_C_TEST FS_C Input High Voltage 2 V DD + 0.3 V VIMFS_C_NORMAL FS_C Input Middle Voltage 0.7 1.5 V VILFS_C_NORMAL FS_C Input Low Voltage V SS – 0.3 0.35 V PCI3/CFG0_HIGH PCI3/CFG0 Input High Voltage Typ. 2.75V 2.40 VDD V PCI3/CFG0_MID PCI3/CFG0 Input Mid Voltage Typ. 1.65V 1.30 2.00 V PCI3/CFG0_LOW PCI3/CFG0 Input Low Voltage Typ. 0.550V 0 0.900 V IIH Input High Leakage Current Except internal pull-down resistors, 0 < V IN < VDD –5 A IIL Input Low Leakage Current Except internal pull-up resistors, 0 < V IN < VDD –5 – A VOH 3.3V Output High Voltage (SE) I OH = –1 mA 2.4 – V VOL 3.3V Output Low Voltage (SE) I OL = 1 mA – 0.4 V VDD IO Low Voltage IO Supply Voltage 1 1.5 V IOZ High-impedance Output Current –10 10 A CIN Input Pin Capacitance 1.5 5 pF COUT Output Pin Capacitance 6p F LIN Pin Inductance – 7 nH VXIH Xin High Voltage 0.7V DD VDD V VXIL Xin Low Voltage 0 0.3V DD V IDDPWRDWN Power Down Current 1m A IDD3.3V Dynamic Supply Current – 250 mA Parameter Description Condition Min. Max. Unit Crystal L ACC Long-term Accuracy – 300 ppm Clock Input TDC CLKIN Duty Cycle Measured at VDD/2 47 53 % TR/TF CLKIN Rise and Fall Times Measured between 0.2V DD and 0.8VDD 0.5 4.0 V/ns TCCJ CLKIN Cycle to Cycle Jitter Measured at VDD/2 – 250 ps TLTJ CLKIN Long Term Jitter Measured at VDD/2 – 350 ps VIL Input Low Voltage XIN / CLKIN pin – 0.8 V VIH Input High Voltage XIN / CLKIN pin 2 VDD+0.3 V IIL Input LowCurrent XIN / CLKIN pin, 0 < VIN <0.8 – 20 uA IIH Input HighCurrent XIN / CLKIN pin, VIN = VDD – 35 uA CPU at 0.7V TDC CPU Clock Duty Cycle Measured at 0V differential at 0.1s 45 55 %
TPERIOD 100 MHz CPU Clock Period Measured at 0V differential at 0.1s 9.99900 10.00100 ns TPERIOD 133 MHz CPU Clock Period Measured at 0V differential at 0.1s 7.49925 7.50075 ns TPERIOD 166 MHz CPU Clock Period Measured at 0V differential at 0.1s 5.99940 6.00060 ns TPERIOD 200 MHz CPU Clock Period Measured at 0V differential at 0.1s 4.99950 5.00050 ns TPERIOD 266 MHz CPU Clock Period Measured at 0V differential at 0.1s 3.74963 3.75038 ns TPERIOD 333 MHz CPU Clock Period Measured at 0V differential at 0.1s 2.99970 3.00030 ns TPERIOD 400 MHz CPU Clock Period Measured at 0V differential at 0.1s 2.49975 2.50025 ns TPERIODSS 100 MHz CPU Clock Period, SSC Measur ed at 0V differential at 0.1s 10.02406 10.02607 ns TPERIODSS 133 MHz CPU Clock Period, SSC Measur ed at 0V differential at 0.1s 7.51804 7.51955 ns TPERIODSS 166 MHz CPU Clock Period, SSC Measur ed at 0V differential at 0.1s 6.01444 6.01564 ns TPERIODSS 200 MHz CPU Clock Period, SSC Measur ed at 0V differential at 0.1s 5.01203 5.01303 ns TPERIODSS 266 MHz CPU Clock Period, SSC Measur ed at 0V differential at 0.1s 3.75902 3.75978 ns TPERIODSS 333 MHz CPU Clock Period, SSC Measur ed at 0V differential at 0.1s 3.00722 3.00782 ns TPERIODSS 400 MHz CPU Clock Period, SSC Measur ed at 0V differential at 0.1s 2.50601 2.50652 ns TPERIODAbs 100 MHz CPU Clock Absolute period Measured at 0V differential at 1 clock 9.91400 10.0860 ns TPERIODAbs 133 MHz CPU Clock Absolute period Measured at 0V differential at 1 clock 7.41425 7.58575 ns TPERIODAbs 166 MHz CPU Clock Absolute period Measured at 0V differential at 1 clock 5.91440 6.08560 ns TPERIODAbs 200 MHz CPU Clock Absolute period Measured at 0V differential at 1 clock 4.91450 5.08550 ns TPERIODAbs 266 MHz CPU Clock Absolute period Measured at 0V differential at 1 clock 3.66463 3.83538 ns TPERIODAbs 333 MHz CPU Clock Absolute period Measured at 0V differential at 1 clock 2.91470 3.08530 ns TPERIODAbs 400 MHz CPU Clock Absolute period Measured at 0V differential at 1 clock 2.41475 2.58525 ns TPERIODSSAbs 100 MHz CPU Clock Absolute period, SSC Measured at 0V differential at 1 clock 9.91406 10.1362 ns TPERIODSSAbs 133 MHz CPU Clock Absolute period, SSC Measured at 0V differential at 1 clock 7.41430 7.62340 ns TPERIODSSAbs 166 MHz CPU Clock Absolute period, SSC Measured at 0V differential at 1 clock 5.91444 6.11572 ns TPERIODSSAbs 200 MHz CPU Clock Absolute period, SSC Measured at 0V differential at 1 clock 4.91453 5.11060 ns TPERIODSSAbs 266 MHz CPU Clock Absolute period, SSC Measured at 0V differential at 1 clock 3.66465 3.85420 ns TPERIODSSAbs 333 MHz CPU Clock Absolute period, SSC Measured at 0V differential at 1 clock 2.91472 3.10036 ns TPERIODSSAbs 400 MHz CPU Clock Absolute period, SSC Measured at 0V differential at 1 clock 2.41477 2.59780 ns TCCJ CPU Cycle to Cycle Jitter Measured at 0V differential –8 5 ps TCCJ2 CPU2_ITP Cycle to Cycle Jitter Measured at 0V differential –1 2 5 ps LACC Long-term Accuracy Measured at 0V differential –1 0 0 ppm TSKEW CPU0 to CPU1 Clock Skew Measured at 0V differential –1 0 0 ps TSKEW2 CPU2_ITP to CPU0 Clock Skew Measured at 0V differential –1 5 0 ps TR / TF CPU Rising/Falling Slew rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV –2 0 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV SRC at 0.7V Parameter Description Condition Min. Max. Unit
TDC SRC Duty Cycle Measured at 0V differential 45 55 % TPERIOD 100 MHz SRC Period Measured at 0V differential at 0.1s 9.99900 10.0010 ns TPERIODSS 100 MHz SRC Period, SSC Measured at 0V differential at 0.1s 10.02406 10.02607 ns TPERIODAbs 100 MHz SRC Absolute Period Measured at 0V differential at 1 clock 9.87400 10.1260 ns TPERIODSSAbs 100 MHz SRC Absolute Period, SSC Meas ured at 0V differential at 1 clock 9.87406 10.1762 ns TSKEW(window) Any SRC Clock Skew from the earliest bank to the latest bank Measured at 0V differential –3 . 0 ns TCCJ SRC Cycle to Cycle Jitter Measured at 0V differential –1 2 5 ps LACC SRC Long Term Accuracy Measured at 0V differential –1 0 0 ppm TR / TF SRC Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV –2 0 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV DOT96 at 0.7V TDC DOT96 Duty Cycle Measured at 0V differential 45 55 % TPERIOD DOT96 Period Measured at 0V differential at 0.1s 10.4156 10.4177 ns TPERIODAbs DOT96 Absolute Period Measured at 0V differential at 0.1s 10.1656 10.6677 ns TCCJ DOT96 Cycle to Cycle Jitter Measured at 0V differential at 1 clock –2 5 0 ps LACC DOT96 Long Term Accuracy Measured at 0V differential at 1 clock –1 0 0 ppm TR / TF DOT96 Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV –2 0 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV LCD_100_SSC at 0.7V TDC LCD_100 Duty Cycle Measured at 0V differential 45 55 % TPERIOD 100 MHz LCD_100 Period Measured at 0V differential at 0.1s 9.99900 10.0010 ns TPERIODSS 100 MHz LCD_100 Period, SSC -0.5% Mea sured at 0V differential at 0.1s 10.02406 10.02607 ns TPERIODAbs 100 MHz LCD_100 Absolute Period Measur ed at 0V differential at 1 clock 9.74900 10.25100 ns TPERIODSSAbs 100 MHz LCD_100 Absolute Period, SSC Measured at 0V differential at 1 clock 9.74906 10.3012 ns TCCJ LCD_100 Cycle to Cycle Jitter Measured at 0V differential –2 5 0 ps LACC LCD_100 Long Term Accuracy Measured at 0V differential –1 0 0 ppm TR / TF LCD_100 Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV –2 0 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV PCI/PCIF at 3.3V TDC PCI Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.99700 30.00300 ns TPERIODSS Spread Enabled PCIF/PCI Period Measurement at 1.5V 30.08421 30.23459 ns TPERIODAbs Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.49700 30.50300 ns Parameter Description Condition Min. Max. Unit
TPERIODSSAbs Spread Enabled PCIF/PCI Period Measurement at 1.5V 29.56617 30.58421 ns THIGH Spread Enabled PCIF and PCI high time Measurement at 2V 12.27095 16.27995 ns TLOW Spread Enabled PCIF and PCI low time Measurement at 0.8V 11.87095 16.07995 ns THIGH Spread Disabled PCIF and PCI high time Measurement at 2.V 12.27365 16.27665 ns TLOW Spread Disabled PCIF and PCI low time Measurement at 0.8V 11.87365 16.07665 ns TR / TF PCIF/PCI Rising/Falling Slew Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TSKEW Any PCI clock to Any PCI clock Skew Measurement at 1.5V – 1000 ps TCCJ PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V –5 0 0 ps LACC PCIF/PCI Long Term Accuracy Measurement at 1.5V –1 0 0 ppm 48_M at 3.3V TDC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Period Measurement at 1.5V 20.83125 20.83542 ns TPERIODAbs Absolute Period Measurement at 1.5V 20.48125 21.18542 ns THIGH 48_M High time Measurement at 2V 8.216563 11.15198 ns TLOW 48_M Low time Measurement at 0.8V 7.816563 10.95198 ns TR / TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 2.0 V/ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V –3 5 0 ps LACC 48M Long Term Accuracy Measurement at 1.5V –1 0 0 ppm 27M_NSS/27M_SS at 3.3V TDC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Spread Disabled 27M Period Measurement at 1.5V 37.03594 37.03813 ns Spread Enabled 27M Period Measurement at 1.5V 37.01299 37.13172 ns TR / TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V –2 5 0 ps LACC 27_M Long Term Accuracy Measured at crossing point V OX –5 0 ppm REF TDC REF Duty Cycle Measurement at 1.5V 45 55 % TPERIOD REF Period Measurement at 1.5V 69.82033 69.86224 ns TPERIODAbs REF Absolute Period Measurement at 1.5V 68.83429 70.84826 ns THIGH REF High time Measurement at 2V 29.97543 38.46654 ns TLOW REF Low time Measurement at 0.8V 29.57543 38.26654 ns TR / TF REF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TSKEW REF Clock to REF Clock Measurement at 1.5V –5 0 0 ps TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 1000 ps LACC Long Term Accuracy Measurement at 1.5V –1 0 0 ppm ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up –1 . 8 ms TSS Stopclock Set-up Time 10.0 – ns Parameter Description Condition Min. Max. Unit
VMIN = 0.30V VMIN = 0.30V VcrossMIN = 300mV VcrossMAX = 550mV VcrossMIN = 300mV VcrossMAX = 550mV VMAX = 1.15V VMAX = 1.15V CLK# CLK CLK# Vcross delta = 140mV Vcross delta = 140mV CLK CLK# CLK# CLK Vcross median Vcross median Vcross median +75mV Vcross median -75mV TriseTfall CLK Figure 17. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number Package Type Product Flow Lead-free SL28506BZC-2 56-pin TSSOP Commercial, 0 to 85C SL28506BZC-2T 56-pin TSSOP–Tape and Reel Commercial, 0 to 85C SL28506BZI-2 56-pin TSSOP Industrial, -40 to 85C SL28506BZI-2T 56-pin TSSOP–Tape and Reel Industrial, -40 to 85C This device is Pb-free, Halogen-free and RoHS compliant. Parts supporting extended temperature is available upon request
56-Lead Thin Shrunk Small Outline Package
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil- icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre- sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli- cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Document History Page Document Title: SL28506-2 Clock Generator for Intel® Eaglelake Chipset DOC #: SP-AP-0021 (Rev AB) REV. ECR# Issue Date Orig. of Change Description of Change 1.0 7/12/07 JMA New data sheet 1.1 7/18/07 JMA Merged TSSOP and SSOP into one datasheet 1.2 7/19/07 JMA Changed part number ordering information 1.3 12/15/07 BSHEN Changed part number ordering information to SL28506BZC Changed Revision ID to 0001 1.4 6/18/08 JMA 1. Removed “Priliminary Confidential” wording 2. Changed operating temperature from 0C - 85C to 0C to 70C 3. Added Pb and ROHs compliant note 1.5 10/23/08 JMA 1. Changed operating temperature back to 0-85C AA 1458 4/7/10 JMA 1. Added new feature for XIN to support also CLKIN input 2. Updated revision and ordering information 3. Updated JEDEC information 4. Updated format to be ISO compliant 5. Merged commercial and industrial temperature 6. Updated TSSOP package drawing 7. Removed SSOP package AB 1458 5/17/10 JMA 1. Added Bit 0 in Byte 3 2. Updated package ID in Byte 8 to reflect package 3. Updated Feature portion to include exclusion of SRC0 and SRC1 from PCIe Gen 2 requirements 4. Updated Byte 11 Bit 1 to be a read only bit 5. Added note to specified SRC0 and SRC1 are note PCIe Gen2 compliant. 6. Specified Byte 11 bit 1 is a read only bit.