SL28504

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Document overview

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Technical content

Features

• Compliant to Intel® CK505
• Low power push-pull type differential output buffers
• Integrated voltage regulator
• Integrated resistors on differential clocks
• Scalable low voltage VDD_IO (3.3V to 1.05V)
• Differential CPU clocks with selectable frequency
• 100 MHz Differential SRC clocks
• 96 MHz Differential DOT clock
• 48 MHz USB clocks
• 33 MHz PCI clock
• 25MHz Free run for WOL
• Selectable 25MHz/24.576MHz
• Buffered Reference Clock 14.318 MHz
• Low-voltage frequency select input 2C support with readback capabilities
• Triangular Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction
• 3.3V Power supply
• 64-pin TSSOP packages CPU SRC PCI REF DOT96 USB_48 24.576M 25M x2 / x3 x8/x11 x6 x 2 x 1 x1 x1 x2 PCI_0/ CR#_A 1 64 SCLK VDD_PCI 2 63 SDATA PCI_1 / CR#_B 3 62 REF0/FSC/TEST_SEL PCI_2 / TME 4 61 VDD_REF PCI_3 5 60 XTAL_IN PCI_4 / G CLK_SEL 6 59 XTAL_OUT PCIF_0 / ITP_EN 7 58 VSS_REF VSS_PCI 8 57 FSB / TEST_MODE VDD_48 9 56 CK_PWRGD / PWRDWN# USB_48 / FSA 10 55 VDD_CPU VSS_48 11 54 CPU0 VDD_IO 12 53 CPU0# SRC0 / DOT96 13 52 VSS_CPU SRC0# / DOT96# 14 51 CPU1 VSS_IO 15 50 CPU1# VDD_PLL3 16 49 VDD_CPU_IO SRC1 / 25M0_F 17 48 *SEL_24.576M SRC1#/ 25M1_24.576M 18 47 SRC8 / CPU2_ITP VSS_PLL3 19 46 SRC8# / CPU2_ITP# VDD_PLL3_IO 20 45 VDD_SRC_IO SRC2 / SATA 21 44 SRC7 / CR#_F SRC2# / SATA# 22 43 SRC7# / CR#_E VSS_SRC 23 42 VSS_SRC SRC3 / CR#_C 24 41 SRC6 SRC3# / CR#_D 25 40 SRC6# VDD_SRC_IO 26 39 VDD_SRC SRC4 27 38 SRC5/ PCI_STOP# SRC4# 28 37 SRC5#/ CPU_STOP# VSS_SRC 29 36 VDD_SRC_IO SRCT9 30 35 SRC10# SRCC9 31 34 SRC10 SRC11# / CR#_G 32 33 SRC11 / CR#_H * Internal Pull-Down SL28504 Pin Configuration

Pin No. Name Type Description 1 PCI0 / CR#_A I/O, SE 33 MHz Clock/3.3V Clock Request # Input Mappable via I2C to control either SRC 0 or SRC 2. Default PCI0. To configure this pin to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit located in byte 5 bit 7, first disable PCI output (Hi-z) in byte 2, bit 1. 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6: 0 = CR#_A controls SRC0 pair (default) 1= CR#_A controls SRC2 pair 2 VDD_PCI PWR 3.3V Power supply for PCI PLL. 3 PCI1 / CR#_B I/O, SE 33 MHz Clock/3.3V Clock Request # Input Mappable via I2C to control either SRC 1 or SRC 4. Default PCI1. To configure this pin to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit located in byte 5, bit 5, first disable PCI output (Hi-z) in byte 2, bit 1. 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 4 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4: 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 4 PCI_2 O, SE 33 MHz clock. Block Diagram CK_PWRGD/PD# PLL Reference FSC:A] PLL1 PLL4 Divider Divider PLL2 Divider REF0 CPU[1:0] SRC8/CPU2_ITP DOT96/SRC0 Control Logic SDATA SCLK 14.318MHz Crystal Xin Xout USB_48 PCI[4:0]; PCIF0 CPU_STOP# PLL3 SRC SEL_24.576M Divider SRC_SATA 25M0_F 25M1_24.576M PCI_STOP# SATA_SEL

5 PCI_3 O, SE 33 MHz clock. 6 PCI4 /SRC5_EN I/O, SE 33 MHz clock output/3.3V-tolerant input for SRC enable (Sampled on CKPWRGD assertion) 1 = SRC5, 0 =CPU_STOP#/PCI_STOP# 7 PCIF_0/ITP_EN I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output. (sampled on the CK_PWRGD assertion) 1 = CPU2_ITP, 0 = SRC8 8 VSS_PCI GND Ground for outputs. 9 VDD_48 PWR 3.3V Power supply for outputs and PLL. 10 USB_48/FSA I/O 3.3V tolerant input for CPU frequency selection/fixed 48 MHz clock output. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 11 VSS_48 GND Ground for outputs. 12 VDD_IO PWR 3.3V-1.05V Power supply for outputs. 13 SRC0/DOT96T O, DIF 100 MHz Differe ntial serial reference clocks/Fixed 96 MHz clock output. Selected via I2C default is SRC0. 14 SRC0#/DOT96# O, DIF 100 MHz Diffe rential serial reference clocks/Fixed 96 MHz clock output. Selected via I2C default is SRC0. 15 VSS_IO GND Ground for PLL2. 16 VDD_PLL3 PWR 3.3V Power supply for PLL3

17 SRC1/25M0_F O, SE 100 MHz Diffe rential serial reference clocks/ Free run 25MHz clock output

18 SRC1#/25M1_24.576M O, SE 100 MHz Differential serial reference clocks/ 25MHz clock output/24.576MHz clock output 19 VSS_PLL3 GND Ground for PLL3. 20 VDD_PLL3_IO PWR 3.3V-1.05V power supply for PLL3 21 SRC2_SATA O, DIF 100 MHz Differe ntial serial reference clocks. 22 SRC2#_SATA# O, DIF 100 MHz Differe ntial serial reference clocks. 23 VSS_SRC GND Ground for outputs.

24 SRC3 / CR#_C I/O,

100 MHz differential serial reference clock output /3.3V Clock Request #_C/D input Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1. The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC to stop when asserted

25 SRC3# / CR#_D I/O,

100 MHz differential serial reference clock output/3.3V Clock Request #_C/D input Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1. The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC to stop when asserted 26 VDD_SRC_IO PWR 3.3V-1.05V power supply for SRC outputs. 27 SRC4 O, DIF 100 MHz Different ial serial reference clocks. 28 SRC4# O, DIF 100 MHz Different ial serial reference clocks. 29 VSS_SRC GND Ground for outputs. 30 SRC9 O, DIF 100 MHz Different ial serial reference clocks. 31 SRC9# O, DIF 100 MHz Different ial serial reference clocks.

32 SRC11#/ CR#_G I/O,

100 MHz differential serial reference clocks/3.3V CR#_G Input. Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4. When selected, CR#_G controls SRC9, CR#_H controls SRC10

33 SRC11/ CR#_H I/O,

100 MHz Differential serial reference clocks/3.3V CR#_H Input. Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4. When selected, CR#_G controls SRC9, CR#_H controls SRC10 64-TSSOP Pin Definitions Pin No. Name Type Description

34 SRC10 O, DIF 100 MHz Different ial serial reference clocks. 35 SRC#10 O, DIF 100 MHz Different ial serial reference clocks. 36 VDD_SRC_IO PWR 3.3V-1.05V power supply for SRC outputs.

37 CPU_STOP#/SRC5# I/O,

3.3V tolerant input for stopping CPU outputs./100 MHz Differential serial reference clocks. The option is selected by SRC5_EN

38 PCI_STOP#/SRC5 I/O,

3.3V tolerant input for stopping PCI and SRC outputs./ 100 MHz Differential serial reference clocks.The option is selected by SRC5_EN 39 VDD_SRC PWR 3.3V Power supply for SRC PLL. 40 SRC6# O, DIF 100 MHz Different ial serial reference clocks. 41 SRC6 O, DIF 100 MHz Different ial serial reference clocks. 42 VSS_SRC GND Ground for outputs.

43 SRC7# O, DIF 100 MHz Differential serial reference clocks

44 SRC7 O, DIF 00 MHz Differential serial reference clocks

45 VDD_SRC_IO PWR 3.3V-1.05V power supply for SRC outputs. 46 SRC8#/CPUC2_ITP# O, DIF Selectable differential CP U or SRC clock output. ITP_EN = 0 @ CK_PWRGD assertion = SRC8 ITP_EN = 1 @ CK_PWRGD assertion = CPU2 Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2. 47 SRC8/CPUT2_ITP O, DIF Selectable differential CP U or SRC clock output. ITP_EN = 0 @ CK_PWRGD assertion = SRC8 ITP_EN = 1 @ CK_PWRGD assertion = CPU2 Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2. 48 SEL_24.576M I, PD Select 25M1_24.576M output and SRC1 0 = 25M1, M= SRC1, 1 = 24.576M 49 VDD_CPU_IO PWR 3.3V-1.05V power supply for CPU outputs. 50 CPU1# O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2. 51 CPU1 O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2. 52 VSS_CPU GND Ground for outputs. 53 CPU0# O, DIF Differential CPU clock outputs. 54 CPU0 O, DIF Differential CPU clock outputs. 55 VDD_CPU PWR 3.3V Power supply for CPU PLL. 56 CK_PWRGD/PWRDWN# I 3.3V LVTTL input. This pin is a le vel sensitive strobe used to latch the FS_A, FS_B, FS_C, and ITP_EN. After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input for asserting power down (active LOW). 57 FSB/TEST_MODE I 3.3V tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when in test mode 0 = Tri-state, 1 = Ref/N. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 58 VSS_REF GND Ground for outputs. 59 XTAL_OUT O, SE 14.318 MHz Crystal output. 60 XTAL_IN I 14.318 MHz Crystal input. 61 VDD_REF PWR 3.3V Power supply for outputs and also maintains SMBUS registers during power-down. 62 REF0/FSC/TEST_SEL I/O 3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output. Selects test mode if pulled to V IHFS_C when CK_PWRGD is asserted HIGH. Refer to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications. 64-TSSOP Pin Definitions Pin No. Name Type Description

63 SMB_DATA I/O SMBus compatible SDATA. 64 SMB_CLK I SMBus compatible SCLOCK. 64-TSSOP Pin Definitions Pin No. Name Type Description

byte is encoded in the command code described in Table 1. Table 1. Command Code Definition Table 2. Block Read and Block Write Protocol

9 Write 9 Write

10 Acknowledge from slave 10 Acknowledge from slave

19 Acknowledge from slave 19 Acknowledge from slave

20 Repeat start

28 Acknowledge from slave 27:21 Slave address–7 bits

37 Acknowledge from slave 29 Acknowledge from slave

46 Acknowledge from slave 38 Acknowledge

Table 3. Byte Read and Byte Write Protocol

29 Stop 28 Read

29 Acknowledge from slave

38 NOT Acknowledge

39 Stop

Table 2. Block Read and Block Write Protocol (continued)

Byte 0: Control Register 0 Bit @Pup Name Description

7 HW FS_C CPU Frequency Select Bit, set by HW

6 HW FS_B CPU Frequency Select Bit, set by HW

5 HW FS_A CPU Frequency Select Bit, set by HW

4 0 iAMT_EN Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP 0 = Legacy Mode, 1 = iAMT Enabled 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 SATA_SEL Select source of SATA clock 0 = PLL3, 1= PLL4 0 1 PD_Restore Save Config. In powerdown 0 = Config. Cleared, 1 = Config. Saved Byte 1: Control Register 1 Bit @Pup Name Description 7 0 SRC0_SEL Select for SRC0 or DOT96 0 = SRC0, 1 = DOT96 6 0 PLL1_SS_DC Select for down or center SS 0 = Down spread, 1 = Center spread 5 0 PLL3_SS_DC Select for down or center SS 0 = Down spread, 1 = Center spread 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 1 Reserved Reserved 0 1 PCI_SEL Select sour ce of PCI clocks 0=PLL1, 1=PLL3 Byte 2: Control Register 2 Bit @Pup Name Description 7 1 REF0_OE Output enable for REF0 0 = Output Disabled, 1 = Output Enabled 6 1 USB48_OE Output enable for USB48 0 = Output Disabled, 1 = Output Enabled 5 1 PCIF0_OE Output enable for PCIF5 0 = Output Disabled, 1 = Output Enabled 4 1 PCI4_OE Output enable for PCI4 0 = Output Disabled, 1 = Output Enabled 3 1 PCI3_OE Output enable for PCI3 0 = Output Disabled, 1 = Output Enabled 2 1 PCI2_OE Output enable for PCI2 0 = Output Disabled, 1 = Output Enabled 1 1 PCI1_OE Output enable for PCI1 0 = Output Disabled, 1 = Output Enabled 0 1 PCI0_OE Output enable for PCI0 0 = Output Disabled, 1 = Output Enabled

Byte 3: Control Register 3 Bit @Pup Name Description 7 1 SRC11_OE Output enable for SRC11 0 = Output Disabled, 1 = Output Enabled 6 1 SRC10_OE Output enable for SRC10 0 = Output Disabled, 1 = Output Enabled 5 1 SRC9_OE Output enable for SRC9 0 = Output Disabled, 1 = Output Enabled 4 1 SRC8/CPU2_ITP_OE Output enable for SRC8 or CPU2_ITP 0 = Output Disabled, 1 = Output Enabled 3 1 SRC7_OE Output enable for SRC7 0 = Output Disabled, 1 = Output Enabled 2 1 SRC6_OE Output enable for SRC6 0 = Output Disabled, 1 = Output Enabled 1 1 RESERVED RESERVED 0 1 SRC4_OE Output enable for SRC4 0 = Output Disabled, 1 = Output Enabled Byte 4: Control Register 4 Bit @Pup Name Description 7 1 SRC3_OE Output enable for SRC3 0 = Output Disabled, 1 = Output Enabled 6 1 SRC2/SATA_OE Output enable for SRC2/SATA 0 = Output Disabled, 1 = Output Enabled 5 1 SRC1_OE Output enable for SRC1 0 = Output Disabled, 1 = Output Enabled 4 1 SRC0/DOT96_OE Output enable for SRC0/DOT96 0 = Output Disabled, 1 = Output Enabled 3 1 CPU1_OE Output enable for CPU1 0 = Output Disabled, 1 = Output Enabled 2 1 CPU0_OE Output enable for CPU0 0 = Output Disabled, 1 = Output Enabled 1 1 PLL1_SS_EN Enable PLL1s spread modulation, 0 = Spread Disabled, 1 = Spread Enabled 0 1 PLL3_SS_EN Enable PLL3s spread modulation 0 = Spread Disabled, 1 = Spread Enabled Byte 5: Control Register 5 Bit @Pup Name Description 7 0 CR#_A_EN Enable CR#_A (clk req) 0 = Disabled, 1 = Enabled, 6 0 CR#_A_SEL Set CR#_A  SRC0 or SRC2 0 = CR#_ASRC0, 1 = CR#_ASRC2 5 0 CR#_B_EN Enable CR#_B(clk req) 0 = Disabled, 1 = Enabled, 4 0 CR#_B_SEL Set CR#_B  SRC1 or SRC4 0 = CR#_BSRC1, 1 = CR#_BSRC4 3 0 CR#_C_EN Enable CR#_C (clk req) 0 = Disabled, 1 = Enabled 2 0 CR#_C_SEL Set CR#_C  SRC0 or SRC2 0 = CR#_CSRC0, 1 = CR#_CSRC2

1 0 CR#_D_EN Enable CR#_D (clk req) 0 = Disabled, 1 = Enabled 0 0 CR#_D_SEL Set CR#_D SRC1 or SRC4 0 = CR#_DSRC1, 1 = CR#_DSRC4 Byte 5: Control Register 5 (continued) Bit @Pup Name Description Byte 6: Control Register 6 Bit @Pup Name Description 7 0 CR#_E_EN Enable CR#_E (clk req)  SRC6 0 = Disabled, 1 = Enabled 6 0 CR#_F_EN Enable CR#_F (clk req)  SRC8 0 = Disabled, 1 = Enabled 5 0 CR#_G_EN Enable CR#_G (clk req)  SRC9 0 = Disabled, 1 = Enabled 4 0 CR#_H_EN Enable CR#_H (clk req)  SRC10 0 = Disabled, 1 = Enabled 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 SRC_STP_CTRL Allows control of SRC with assertion of PCI_STOP# 0 = Free running SRC 1 = Stopped with PCI_STOP# Byte 7: Vendor ID Bit @Pup Name Description 7 0 Rev Code Bit 3 Revision Code Bit 3 6 0 Rev Code Bit 2 Revision Code Bit 2 5 0 Rev Code Bit 1 Revision Code Bit 1 4 1 Rev Code Bit 0 Revision Code Bit 0 3 1 Vendor ID bit 3 Vendor ID Bit 3 2 0 Vendor ID bit 2 Vendor ID Bit 2 1 0 Vendor ID bit 1 Vendor ID Bit 1 0 0 Vendor ID bit 0 Vendor ID Bit 0 Byte 8: Control Register 8 Bit @Pup Name Description 7 0 Device_ID3 0000 = 56-TSSOP 0001 = 64-TSSOP 0010 = Reserved 0011 = 56-QFN 0100 = 64-QFN 0101 = Reserved 0110 = Reserved 0111 = 56-SSOP 1000 = Reserved 1001 = Reserved 1010 = Reserved 1011 = Reserved 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved 6 0 Device_ID2 5 0 Device_ID1 4 1 Device_ID0

1 1 25M0 _F_OE Output enable for 25M0 _F 0 = Output Disabled, 1 = Output Enabled 0 1 25M1_24.576M_OE Output enable for 25M1_24.576M 0 = Output Disabled, 1 = Output Enabled Byte 8: Control Register 8 (continued) Bit @Pup Name Description Byte 9: Control Register 9 Bit @Pup Name Description 7 0 PCIF5_STP_CTRL Allows control of PCIF5 with assertion of PCI_STOP# 0 = Free running PCIF, 1 = Stopped with PCI_STOP# 6 0 Reserved Reserved 5 1 REF Bit1 REF drive strength Setting 1 of 3 (see Byte 13 and 14 for more settings) 0 = Low, 1 = High 4 0 TEST _MODE_SEL Test mode select either REF/N or tri-state 0 = All outputs tri-state, 1 = All output REF/N 3 0 TEST_MODE_ENTRY Allows entry into test mode 0 = Normal Operation, 1 = Enter test mode(s) 2 1 12C_VOUT<2> I2C_VOUT[2:0] 000 = 0.30V 001 = 0.40V 010 = 0.50V 011 = 060V 100 = 0.70V 101 = 0.80V (default) 110 = 0.90V 111 = 1.00V 1 0 12C_VOUT<1> 0 1 12C_VOUT<0> Byte 10: Control Register 10 Bit @Pup Name Description

7 HW SRC5_EN SRC5_EN latche status

0= CPU_STP#/PCI_STP#; 1= SRC5 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 1 CPU1_STP_CTRL Enable CPU_STOP# control of CPU1 0 = Free running, 1= Stoppable 0 1 CPU0_STP_CTRL Enable CPU_STOP# control of CPU0 0 = Free running, 1= Stoppable Byte 11: Control Register 11 Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 1 25M0_F 25M0_F Output Enabled applies to Powerdown / M1 0 = 25MHz disabled in Powerdown / M1 1 = 25MHz enabled in Powerdown / M1; Sticky 1

Byte 14: Control Register 14 4 0 Reserved Reserved 3 0 CPU2_iAMT_EN 2 1 CPU1_iAMT_EN 1 0 Reserved Reserved 0 1 CPU2_STP_CRTL Allow control of CPU2 with assertion of CPU_STOP# 0 = Free running, 1 = Stopped with CPU_STOP# Byte 11: Control Register 11 (continued) PCIF5/ITP_EN AMT_EN CPU2_AMT_EN CPU1_AMT_EN Description x1 0 0 R e s e r v e d x 1 0 1 CPU1 = M1 Clock 1 1 1 0 CPU2 - M1 Clock 1 1 1 1 CPU1 and CPU2 = M1 Clock Byte 12: Byte Count Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 BC5 Byte count 4 1 BC4 Byte count 3 0 BC3 Byte count 2 0 BC2 Byte count 1 1 BC1 Byte count 0 1 BC0 Byte count Byte 13: Control Register 13 Bit @Pup Name Description 7 0 PCIF/PCI Bit 2 Drive Strength Control - Bit[2:0] Note: REF Bit 1 is located in Byte 9 Bit 56 1 PCIF/PCI Bit 1 5 0 PCIF/PCI Bit 0 4 0 USB Bit 2 3 1 USB Bit 1 2 0 USB Bit 0

10 R E F B i t 2

00 R E F B i t 0

(Various Bytes) Bit 1 (Various Bytes) Bit 0 (Various Bytes) Buffer Strength 1 1 1 Strongest 11 0 10 1 10 0 01 1 Default 01 0 00 1 0 0 0 Weakest Bit @Pup Name Description 7 0 SE1/SE2 Bit 2 SE1/SE2 Bit 2 drive strength 0 = Low, 1 = High 6 1 SE1/SE2 Bit 1 SE1/SE2 Bit 1 drive strength 0 = Low, 1 = High 5 0 SE1/SE2 Bit 0 SE1/SE2 Bit 0 drive strength 0 = Low, 1 = High 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED

2 1 SATA_SS_EN Enable SATA spread modulation, 0 = Spread Disabled, 1 = Spread Enabled 1 1 EN_CFG0_SET By defalult CFG0 pin strap sets the SMBus initial values to select the HW mode. When this bit is written0, subsequent SMBus accesses is the Lathes Open state, can overwrite the CFG0 pin setting into the SMBus bits and set the mode before the M0 state: specifically B0b2, B1b[6,4,3], B9b1, B11b5 0 1 SW_PCI SW PCI_ STP# Function 0 = SW PCI_STP assert, 1 = SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs are stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs are resumed in a synchronous manner with no short pulses. Bit @Pup Name Description Byte 15: Control Register 15 Bit @Pup Name Description 7 0 CPU_DAF_N7 If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] are used to determine the CPU output frequency. 6 0 CPU_DAF_N6 5 0 CPU_DAF_N5 4 0 CPU_DAF_N4 3 0 CPU_DAF_N3 2 0 CPU_DAF_N2 1 0 CPU_DAF_N1 0 0 CPU_DAF_N0 Byte 16: Control Register 16 Bit @Pup Name Description 7 0 CPU_DAF_N8 See Byte 14 for description 6 0 CPU_DAF_M6 If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] are used to determine the CPU output frequency. 5 0 CPU_DAF_M5 4 0 CPU_DAF_M4 3 0 CPU_DAF_M3 2 0 CPU_DAF_M2 1 0 CPU_DAF_M1 0 0 CPU_DAF_M0 Byte 17: Control Register 17 Bit @Pup Name Description 7 0 PCI-E_N7 PCI-E Dial-A-Frequency ® Bit N7 6 0 PCI-E_N6 PCI-E Dial-A-Frequency Bit N6 5 0 PCI-E_N5 PCI-E Dial-A-Frequency Bit N5 4 0 PCI-E_N4 PCI-E Dial-A-Frequency Bit N4 3 0 PCI-E_N3 PCI-E Dial-A-Frequency Bit N3 2 0 PCI-E_N2 PCI-E Dial-A-Frequency Bit N2 1 0 PCI-E_N1 PCI-E Dial-A-Frequency Bit N1 0 0 PCI-E_N0 PCI-E Dial-A-Frequency Bit N0

using standard value trim capacitors (lead frame, bond wires, etc.) Dial-A-Frequency® (CPU and PCIEX) This feature allows the user to over-clock their system by slowly stepping up the CPU or SRC frequency. When the programmable output frequency feature is enabled, the CPU and SRC frequencies are determined by the following equation: Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.

• “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively.
• “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[E:A]. See Table , Frequency Select Table for the Gear Constant for each Frequency selection. The PCI Express only allows user control of the N register, the M value is fixed and documented in Table , Frequency Select Table. In this mode, the user writes the desired N and M values into the DAF I2C registers. The user cannot change only the M value and must change both the M and the N values at the same time, if they require a change to the M value. The user may change only the N value. Associated Register Bits
• CPU_DAF Enable – This bit enables CPU DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the CPU_DAF_N register. Note that the CPU_DAF_N and M register must contain valid values before CPU_DAF is set. Default = 0, (No DAF).
• CPU_DAF_N – There are nine bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, (0000). The allowable values for N are detailed in Table , Frequency Select Table.
• CPU DAF M – There are 7 bits (for 128 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, the allowable values for M are detailed in Table , Frequency Select Table
• SRC_DAF Enable – This bit enables SRC DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the SRC_DAF_N register. Note that the SRC_DAF_N register must contain valid values before SRC_DAF is set. Default = 0, (No DAF).
• SRC_DAF_N – There are nine bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, (0000). The allowable values for N are detailed in Table , Frequency Select Table. Smooth Switching The device contains one smooth switch circuit that is shared by the CPU PLL and SRC PLL. The smooth switch circuit ensures that when the out put frequency changes by overclocking, the transition from the old frequency to the new frequency is a slow, smooth transition containing no glitches. The rate of change of output frequency when using the smooth switch circuit is less than 1 MHz/0.667 s. The frequency overshoot and undershoot is less than 2%. The Smooth Switch circuit assigns auto or manual. In Auto mode, clock generator assigns smooth switch automatically when the PLL does overclocking. For manual mode, assign the smooth switch circuit to PLL via Smbus. By default the smooth switch circuit is se t to auto mode. PLL can be over-clocked when it does not have control of the smooth switch circuit but it is not guaranteed to transition to the new frequency without large frequency glitches. Do not enable over-clocking and change the N values of both PLLs in the same SMBUS block write and use smooth switch mechanism on spread spectrum on/off. PD_RESTORE If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PWRDWN# LOW, the SL28504 initiates a full reset. The result of this is that the clock chip emulates a cold power on start and goes to the “Latches Open” state. If the PD_RESTORE bit is set to a ‘1’ then the configuration is stored upon PWRDWN# asserted LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then the PD_RESTORE bit must be ignored. In other words, in Intel iAMT mode, PWRDWN# reset is not allowed. PWRDWN# (Power down) Clarification The CKPWRGD/PWRDWN# pin is a dual-function pin. During initial power up, the pin functions as CKPWRGD. Once CKPWRGD has been sampled HIGH by the clock chip, the pin assumes PD# functionality. The PD# pin is an asynchronous active LOW input used to shut off all clocks cleanly before shutting off power to the device. This signal is synchronized internally to the device before powering down the clock synthesizer. PD# is also an asynchronous input for powering up the system. When PD# is asserted LOW, clocks are driven to a LOW value and held before turning off the VCOs and the crystal oscillator. PWRDWN# (Power down) Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must held LOW. When PD mode is desired as the initial power on state, PD must be asserted HIGH in less than 10 s after asserting CKPWRGD. PWRDWN# Deassertion The power up latency is less than 1.8 ms. This is the time from the deassertion of the PD# pin or the ramping of the power supply until the time that stable clocks are generated from the clock chip. All differential outputs stopped in a three-state condition, resulting from power down are driven high in less than 300 s of PD# deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs are enabl ed within a few clock cycles of

Figure 5. CK_PWRGD Timing Diagram

Table 5. Output Driver Status during PCI-STOP# and CPU-STOP# Table 6. Output Driver Status Figure 12. Clock Generator Power up/Run State Diagram

Figure 13. BSEL Serial Latching

Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage – 4.6 V VDD_A Analog Supply Voltage – 4.6 V VDD_IO IO Supply Voltage 1.5 V VIN Input Voltage Relative to V SS –0.5 4.6 V DC TS Temperature, Storage Non-functional –65 150 °C TA Temperature, Operating Ambient Functional -40 85 °C TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case Mil-STD-883E Method 1012.1 – 20 °C/ W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/ W ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V UL-94 Flammability Rating At 1/8 in. V–0 MSL Moisture Sensitivity Level 1 Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Parameter Description Condition Min. Max. Unit VDD core 3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V VIH 3.3V Input High Voltage (SE) 2.0 V DD + 0.3 V VIL 3.3V Input Low Voltage (SE) V SS – 0.3 0.8 V VIHI2C Input High Voltage SDATA, SCLK 2.2 – V VILI2C Input Low Voltage SDATA, SCLK – 1.0 V VIH_FS FS_[A,B] Input High Voltage 0.7 1.5 V VIL_FS FS_[A,B] Input Low Voltage V SS – 0.3 0.35 V VIHFS_C_TEST FS_C, Input High Voltage 2 V DD + 0.3 V VIMFS_C_NORMAL FS_C, Input Middle Voltage 0.7 1.5 V VILFS_C_NORMAL FS_C, Input Low Voltage V SS – 0.3 0.35 V IIH Input High Leakage Current Except internal pull-down resistors, 0 < V IN < VDD –5 A SEL_24.576M_HI GH SEL_24.576M Input High Voltage Typ. 2.75V 2.40 VDD V SEL_24.576M_MI D SEL_24.576M Input Mid Voltage Typ. 1.65V 1.30 2.00 V SEL_24.576M_LO W SEL_24.576M Input Low Voltage Typ. 0.550V 0 0.900 V IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN < VDD –5 – A VOH 3.3V Output High Voltage (SE) I OH = –1 mA 2.4 – V VOL 3.3V Output Low Voltage (SE) I OL = 1 mA – 0.4 V VDD IO Low Voltage IO Supply Voltage 1 3.465 VOH 3.3V Input High Voltage (DIFF) 0.70 0.90 V VOL 3.3V Input Low Voltage (DIFF) 0.40 V IOZ High-impedance Output Current –10 10 A CIN Input Pin Capacitance 1.5 5 pF COUT Output Pin Capacitance 6p F

LIN Pin Inductance – 7 nH VXIH Xin High Voltage 0.7V DD VDD V VXIL Xin Low Voltage 0 0.3V DD V IDD3.3V Dynamic Supply Current – 250 mA Parameter Description Condition Min. Max. Unit

Parameter Description Condition Min. Max. Unit Crystal TDC XIN Duty Cycle The device operates reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification 47.5 52.5 % TPERIOD XIN Period When XIN is dr iven from an external clock source 69.841 71.0 ns TR/TF XIN Rise and Fall Times Measured between 0.3V DD and 0.7VDD –1 0 . 0 n s TCCJ XIN Cycle to Cycle Jitter As an average over 1- s duration – 500 ps CPU at 0.7V TDC CPUT and CPUC Duty Cycle Measure d at 0V differential at 0.1s 45 55 % TPERIOD 100 MHz CPUT and CPUC Period Measur ed at 0V differential at 0.1s 9.99900 10.0100 ns TPERIOD 133 MHz CPUT and CPUC Period Measur ed at 0V differential at 0.1s 7.49925 7.50075 ns TPERIOD 166 MHz CPUT and CPUC Period Measur ed at 0V differential at 0.1s 5.99940 6.00060 ns TPERIOD 200 MHz CPUT and CPUC Period Measur ed at 0V differential at 0.1s 4.99950 5.00050 ns TPERIOD 266 MHz CPUT and CPUC Period Measur ed at 0V differential at 0.1s 3.74963 3.75038 ns TPERIOD 333 MHz CPUT and CPUC Period Measured at 0V differential at 0.1s 2.99970 3.00030 ns TPERIOD 400 MHz CPUT and CPUC Period Measur ed at 0V differential at 0.1s 2.49975 2.50025 ns TPERIODSS 100 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s 10.02406 10.02607 ns TPERIODSS 133 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s 7.51804 7.51955 ns TPERIODSS 166 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s 6.01444 6.01564 ns TPERIODSS 200 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s 5.01203 5.01303 ns TPERIODSS 266 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s 3.75902 3.75978 ns TPERIODSS 333 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s 3.00722 3.00782 ns TPERIODSS 400 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s 2.50601 2.50652 ns TPERIODAbs 100 MHz CPUT and CPUC Absolute period Measured at 0V differential at 1 clock 9.91400 10.0860 ns TPERIODAbs 133 MHz CPUT and CPUC Absolute period Measured at 0V differential at 1 clock 7.41425 7.58575 ns TPERIODAbs 166 MHz CPUT and CPUC Absolute period Measured at 0V differential @ 1 clock 5.91440 6.08560 ns TPERIODAbs 200 MHz CPUT and CPUC Absolute period Measured at 0V differential @ 1 clock 4.91450 5.08550 ns TPERIODAbs 266 MHz CPUT and CPUC Absolute period Measured at 0V differential @ 1 clock 3.66463 3.83538 ns TPERIODAbs 333 MHz CPUT and CPUC Absolute period Measured at 0V differential @ 1 clock 2.91470 3.08530 ns TPERIODAbs 400 MHz CPUT and CPUC Absolute period Measured at 0V differential @ 1 clock 2.41475 2.58525 ns TPERIODSSAbs 100 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock 9.91406 10.1362 ns TPERIODSSAbs 133 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock 7.41430 7.62340 ns TPERIODSSAbs 166 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock 5.91444 6.11572 ns TPERIODSSAbs 200 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock 4.91453 5.11060 ns TPERIODSSAbs 266 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock 3.66465 3.85420 ns

TPERIODSSAbs 333 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock 2.91472 3.10036 ns TPERIODSSAbs 400 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock 2.41477 2.59780 ns TCCJ CPU Cycle to Cycle Jitter Measured at 0V differential – 85 ps TCCJ2 CPU2_ITP Cycle to Cycle Jitter Me asured at 0V differential – 125 ps LACC Long-term Accuracy Measured at 0V differential – 100 ppm TSKEW CPU0 to CPU1 Clock Skew Measured at 0V differential – 100 ps TSKEW2 CPU2_ITP to CPU0 Clock Skew Meas ured at 0V differential – 150 ps TR / TF CPU Rising/Falling Slew rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV SRC at 0.7V TDC SRC Duty Cycle Measured at 0V differential 45 55 % TPERIOD 100 MHz SRC Period Measured at 0V differential @ 0.1s 9.99900 10.0010 ns TPERIODSS 100 MHz SRC Period, SSC Measured at 0V differential @ 0.1s 10.02406 10.02607 ns TPERIODAbs 100 MHz SRC Absolute Period Measured at 0V differential @ 1 clock 9.87400 10.1260 ns TPERIODSSAbs 100 MHz SRC Absolute Period, SSC Meas ured at 0V differential @ 1 clock 9.87406 10.1762 ns TSKEW(window) Any SRC Clock Skew from the earliest bank to the latest bank Measured at 0V differential – 3.0 ns TCCJ SRC Cycle to Cycle Jitter Measured at 0V differential – 125 ps LACC SRC Long Term Accuracy Measured at 0V differential – 100 ppm TR / TF SRC Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV DOT96 at 0.7V TDC DOT96 Duty Cycle Measured at 0V differential 45 55 % TPERIOD DOT96 Period Measured at 0V differential at 0.1s 10.4156 10.4177 ns TPERIODAbs DOT96 Absolute Period Measured at 0V differential at 0.1s 10.1656 10.6677 ns TCCJ DOT96 Cycle to Cycle Jitter Measured at 0V differential at 1 clock – 250 ps LACC DOT96 Long Term Accuracy Measured at 0V differential at 1 clock – 100 ppm TR / TF DOT96 Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV PCI/PCIF at 3.3V Parameter Description Condition Min. Max. Unit

TDC PCI Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.99700 30.00300 ns TPERIODSS Spread Enabled PCIF/PCI Period Measurement at 1.5V 30.08421 30.23459 ns TPERIODAbs Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.49700 30.50300 ns TPERIODSSAbs Spread Enabled PCIF/PCI Period Measurement at 1.5V 29.56617 30.58421 ns THIGH Spread Enabled PCIF and PCI high timeMeasurement at 2V 12.27095 16.27995 ns TLOW Spread Enabled PCIF and PCI low time Measurement at 0.8V 11.87095 16.07995 ns THIGH Spread Disabled PCIF and PCI high time Measurement at 2.V 12.27365 16.27665 ns TLOW Spread Disabled PCIF and PCI low time Measurement at 0.8V 11.87365 16.07665 ns TR / TF PCIF/PCI Rising/Falling Slew Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TSKEW Any PCI clock to Any PCI clock Skew Measurement at 1.5V – 1000 ps TCCJ PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V – 500 ps LACC PCIF/PCI Long Term Accuracy Measurement at 1.5V – 100 ppm 48_M at 3.3V T DC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Period Measurement at 1.5V 20.83125 20.83542 ns TPERIODAbs Absolute Period Measurement at 1.5V 20.48125 21.18542 ns THIGH 48_M High time Measurement at 2V 8.216563 11.15198 ns TLOW 48_M Low time Measurement at 0.8V 7.816563 10.95198 ns TR / TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 2.0 V/ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 350 ps LACC 48M Long Term Accuracy Measurement at 1.5V – 100 ppm 25_M T DC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Period Measurement at 1.5V 39.996 40.004 ns TR/TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 500 ps LACC 25M Long Term Accuracy Measurement at 1.5V – 50 ppm 1394A - 24.576M T DC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Period Measurement at 1.5V 40.686 40.694 ns TR/TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 200 ps LACC 24M Long Term Accuracy Measurement at 1.5V –30 30 ppm REF T DC REF Duty Cycle Measurement at 1.5V 45 55 % TPERIOD REF Period Measurement at 1.5V 69.82033 69.86224 ns TPERIODAbs REF Absolute Period Measurement at 1.5V 68.83429 70.84826 ns THIGH REF High time Measurement at 2V 29.97543 38.46654 ns TLOW REF Low time Measurement at 0.8V 29.57543 38.26654 ns TR / TF REF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TSKEW REF Clock to REF Clock Measurement at 1.5V – 500 ps TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 1000 ps Parameter Description Condition Min. Max. Unit

Ordering Information

Part Number Package Type Product Flow Lead-free SL28504BZC 64-pin TSSOP Commercial, 0  to 85C SL28504BZCT 64-pin TSSOP–Tape and Reel Commercial, 0  to 85C SL28504BZI 64-pin TSSOP Industrial, -40  to 85C SL28504BZIT 64-pin TSSOP–Tape and Reel Industrial, -40  to 85C Packaging Designator for Tape and Reel Temperature Designator Package Designator C : Commercial spec; I: Industrial spec Revision Number Generic Part Number Designated Family Number Company Initials SL 28 504 B ZC T Z: TSSOP; L: QFN Package Diagrams 64-Lead Thin Shrunk Small Outline Package (6 mm x 17 mm) Z64

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil- icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre- sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli- cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Document History Page Document Title: SL28504 Clock Generator for IntelEaglelake Chipset REV. ECR# Issue Date Orig. of Change Description of Change 1.0 10/5/07 BSHEN Initial Release 1.1 10/19/07 BSHEN Add SRC1 to pin 17/1 8. and tri-level trigger at 24.576M 1.2 01/21/08 BSHEN 1. Change Revisi on ID Byte7[7:4] to be 0001 2. Updated block diagram 3. Change Byte10[6:2] and Byte11[4] to be reserved 1.3 05/26/09 BSHEN 1. Update TSSO P64 package dimension to compliant to SLI-POD spec 1.4 06/24/09 BSHEN 1. Correct the pin out with CLK request pin 2. Correct the CLK request register 3. Remove QFN package, AA 1576 04/28/10 BSHEN 1. Updated Industrial ordering information 2. Correct VDD_IO pin description 3. Updated document format for ISO compliance.