SL23EP08SC-1HT

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Technical content

Rev 1.0, May 18, 2006 Page 1 of 15 2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com SL23EP08 Key Features

• 10 to 220 MHz operating frequency range
• Low output clock skew: 45ps-typ
• Low output clock jitter:  25 ps-typ cycle-to-cycle jitter  15 ps-typ period jitter
• Low part-to-part output skew: 90 ps-typ
• Wide 2.5 V to 3.3 V power supply range
• Low power dissipation:  20 mA-max at 66 MHz and VDD=3.3 V  18 mA-max at 66 MHz and VDD=2.5V
• One input drives 8 outputs
• Multiple configurations and drive options
• Select mode to bypass PLL or tri-state outputs
• SpreadThru™ PLL that allows use of SSCG
• Available in 16-pin SOIC and TSSOP packages
• Available in Commercial and Industrial grades

Applications

• Printers, MFPs and Digital Copiers
• PCs and Work Stations
• Routers, Switchers and Servers
• Datacom and Telecom
• High-SpeedDigital Embeded Systems

Description

The SL23EP08 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. The product has an on- chip PLL and a feedback pin (FBK) which can be used to obtain feedback from any one of the output clocks. The SL23EP08 has two (2) clock driver banks each with four (4) clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, four (4) bank -B output clock buffers can be tri-stated to reduce power dissipation and jitter. The select inputs can also be used to tri -state both banks A and B or drive them directly from the input bypassing the PLL and making the product behave like a Non-Zero Delay Buffer (NZDB). The product also offers various 1X, 2X and 4X frequency options at the output clocks. Refer to the “Product Configuration Table” for the details. The high-drive version operates up to 220MHz and 200MHz at 3.3V and 2.5V power supplies respectively. Benefits

• Up to eight (8) distribution of input clock
• Standard and High-Dirive levels to control impedance level, frequency range and EMI
• Low power dissipation, jitter and skew
• Low cost Block Diagram Low Power and Low Jitter PLL MUX Input Selection Decoding Logic VDD GND CLKIN FBK CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 (Divider for -3 and -4 only) (Divider for -5H only) (Divider for -2 and -3 only) Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)

Rev 1.0, May 18, 2006 Page 2 of 15 SL23EP08 Pin Configuration CLKA1 FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 CLKIN CLKA2 VDD GND CLKB1 CLKB2 Pin Description 16-Pin SOIC and TSSOP Pin Number Pin Name Pin Type Pin Description 1 CLKIN Input Reference Frequency Clock Input. 5V tolerant input. Weak pull-down (250kΩ). 2 CLKA1 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 3 CLKA2 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 4 VDD Power 3.3V or 2.5V Power Supply. 5 GND Power Power Ground. 6 CLKB1 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 7 CLKB2 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 8 S2 Input Select Input, select pin S2. Weak pull-up (250kΩ). 9 S1 Input Select Input, select pin S1. Weak pull-up (250kΩ). 10 CLKB3 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 11 CLKB4 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 12 GND Power Power Ground. 13 VDD Power 3.3V or 2.5V Power Supply. 14 CLKA3 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 15 CLKA4 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 16 FBK Output PLL Feedback input.

with very low operating current. systems requiring clock distribution.

3.3 HIGH 10 220

3.3 STD 10 167

2.5 HIGH 10 200

2.5 STD 10 133

Table 1. Input/Output Frequency Range draws less than 25 μA supply current. source and PLL shutdown features as shown in the Table 2. clocks are driven by directly from the reference input clock. control. Refer to the AC electrical tables for the details. Table 2. Select Input Decoding

Table 3. Available SL23EP08 Configurations

1. Outputs are inverted on SL23EP08-2 and SL23EP08-3 in PLL bypass mode when S2=1 and S1=0.
2. Output phase is either 0° or 180° with respect to CLKIN input. If phase integrity is required, use the SL23EP08-2.

Figure 1. CLKIN Input to CLKA and CLKB Delay

Rev 1.0, May 18, 2006 Page 5 of 15 SL23EP08 Absolute Maximum Ratings Operating Conditions: Unless otherwise stated VDD=2.5V to 3.3V and for both C and I Grades Description Condition Min. Max. Unit Supply voltage, VDD – 0.5 4.6 V All Inputs and Outputs – 0.5 VDD+0.5 V Ambient Operating Temperature In operation, C-Grade 0 70 °C Ambient Operating Temperature In operation, I-Grade – 40 85 °C Storage Temperature No power is applied – 65 150 °C Junction Temperature In operation, power is applied – 125 °C Soldering Temperature – 260 °C ESD Rating (Human Body Model) MIL-STD-883, Method 3015 2000 – V Symbol Description Condition Min. Max. Unit TA Operating Temperature(Ambient) Commercial 0 70 °C Industrial –40 85 °C CLOAD Load Capacitance <100 MHz, 3.3V with Standard or High drive – 30 pF <100 MHz, 2.5V with High drive – 30 pF <133.3 MHz, 3.3V with Standard or High drive – 22 pF <133.3 MHz, 2.5V with High drive – 22 pF <133.3 MHz, 2.5V with Standard drive – 15 pF >133.3 MHz, 3.3V with Standard or High drive – 15 pF >133.3 MHz, 2.5V with High drive – 15 pF CIN Input Capacitance S1, S2 and CLKIN pins – 5 pF CLBW Closed-loop bandwidth 3.3V, (typical) 1.2 MHz 2.5V, (typical) 0.8 MHz ZOUT Output Impedance 3.3V, (typical), High drive 29 Ω 3.3V, (typical), Standard drive 41 Ω 2.5V, (typical), High drive 37 Ω 2.5V, (typical), Standard drive 41 Ω

Rev 1.0, May 18, 2006 Page 6 of 15 SL23EP08 Symbol Description Condition Min. Max. Unit VDD Supply Voltage 2.970 3.630 V VIL Input LOW Voltage – 0.8 V VIH Input HIGH Voltage 2.0 VDD+0.3 V IIL Input Leakage Current 0 < VIN < 0.8V – ±10 µA IIH Input HIGH Current VIN = VDD – 100 µA VOL Output LOW Voltage IOL = 8 mA (standard drive) – 0.4 V IOL = 12 mA (high drive) – 0.4 V VOH Output HIGH Voltage IOH = –8 mA (standard drive) 2.4 – V IOH = –12 mA (high drive) 2.4 – V IDDPD Power Down Supply Current CLKIN<2MHz CLKIN = 0 MHz (C-Grade) – 12 µA CLKIN = 0 MHz (I-Grade) – 25 µA IDD Power Supply Current All Outputs CL=0, 66-MHz CLKIN – 20 mA Symbol Description Condition Min. Max. Unit. VDD Supply Voltage 2.3 2.7 V VIL Input LOW Voltage – 0.7 V VIH Input HIGH Voltage 1.7 VDD+ 0.3 V IIL Input Leakage Current 0<VIN < 0.8V – 10 µA IIH Input HIGH Current VIN = VDD – 100 µA VOL Output LOW Voltage IOL = 8 mA (standard drive) – 0.5 V IOL = 12 mA (high drive) – 0.5 V VOH Output HIGH Voltage IOH = –8 mA (standard drive) VDD – 0.6 – V IOH = –12 mA (high drive) VDD – 0.6 – V IDDPD Power Down Supply Current CLKIN<2MHz CLKIN = 0 MHz (C-Grade) – 12 µA CLKIN = 0 MHz (I-Grade) – 25 µA IDD Power Supply Current All Outputs CL=0, 66-MHz CLKIN – 18 mA

Rev 1.0, May 18, 2006 Page 7 of 15 SL23EP08 Symbol Description Condition Min Typ Max Unit FOUT-1 Output Frequency CL=30pf, All devices 10 - 160 MHz FOUT-2 Output Frequency CL=20pF, -1H and -5H versions 10 - 220 MHz FOUT-2 Output Frequency CL=15pF, -1,-2,-3 and -4 versions 10 - 200 MHz DC-1 Duty Cycle. -1, -2, -3,-4,-1H and -5H versions CL=30pF, FOUT=66.6MHz and Measured at VDD/2 40.0 50.0 60.0 % DC-2 Duty Cycle, -1, -2, -3,-4,-1H and -5H versions CL=15pF, FOUT<66.6MHz and Measured at VDD/2 45.0 50.0 55.0 % DC-1 Duty Cycle. -1, -2, -3,-4,-1H and -5H versions CL=30pF, FOUT=120MHz and Measured at VDD/2 TBD TBD TBD % DC-2 Duty Cycle. -1, -2, -3,-4,-1H and -5H versions CL=15pF, FOUT=120MHz and Measured at VDD/2 TBD TBD TBD % tr/f-1 Rise and Fall Times. -1, -2, - 3, and -4 versions Measured between 0.8V and 2.0V CL=30pF 1.6 ns tr/f-2 Rise and Fall Times. -1, -2, - 3, and -4 versions Measured between 0.8V and 2.0V CL=15pF 1.2 ns tr/f-3 Rise and Fall Times. -1,1H and -5H versions Measured between 0.8V and 2.0V CL=30pF 1.2 ns tr/f-3 Rise and Fall Times. -1H and -5H versions Measured between 0.8V and 2.0V CL=15pF 1.0 ns SKW-1 Output-to-Output on same bank A or B. All versions All outputs are equally loaded. Measured at VDD/2 - 60 150 ps SKW-2 Output Bank-A to Bank-B Skew. -1-4 and -5H versions All outputs are equally loaded. Measured at VDD/2 - 60 150 ps SKW-3 Output Bank-A to Bank-B Skew. -1-4 and -5H versions All outputs are equally loaded. Measured at VDD/2 - 130 300 ps SKW-4 Device-to-Device Skew. All versions All outputs are equally loaded. Measured at VDD/2 and FBK pin - 180 500 ps tCFD CLKIN to FBK Rising Edge Delay All outputs are equally loaded. Measured at VDD/2 -200 - 200 ps t2 Delay Time, CLKIN Rising Edge to CLKOUT Rising Edge (Measured at VDD/2) [2] PLL Bypass mode 1.5 – 4.4 ns PLL enabled @ 3.3V –100 – 100 ps PLL enabled @2.5V –200 – 200 ps t3 Part-to-Part Skew[2] (Measured at VDD/2) Measured at VDD/2. Any output to any output, 3.3V supply – – ±150 ps Measured at VDD/2. Any output to any output, 2.5V supply – – ±300 ps tLOCK PLL Lock Time Valid on all clock pins from VDD=2.97V - - 1.0 ms

Rev 1.0, May 18, 2006 Page 8 of 15 SL23EP08 Symbol Description Condition Min Typ Max Unit FOUT-1 Output Frequency CL=30pf, All devices 10 - 160 MHz FOUT-2 Output Frequency CL=20pF, -1H and -5H versions 10 - 220 MHz FOUT-2 Output Frequency CL=15pF, -1,-2,-3 and -4 versions 10 - 200 MHz DC-1 Duty Cycle. -1, -2, -3,-4,-1H and -5H versions CL=30pF, FOUT=66.6MHz and Measured at VD/2 40.0 50.0 60.0 % DC-2 Duty Cycle, -1, -2, -3,-4,-1H and -5H versions CL=15pF, FOUT<66.6MHz and Measured at VDD/2 45.0 50.0 55.0 % DC-1 Duty Cycle. -1, -2, -3,-4,-1H and -5H versions CL=30pF, FOUT=120MHz and Measured at VDD/2 TBD TBD TBD % DC-2 Duty Cycle. -1, -2, -3,-4,-1H and -5H versions CL=15pF, FOUT=120MHz and Measured at VDD/2 TBD TBD TBD % tr/f-1 Rise and Fall Times. -1, -2, - 3, and -4 versions Measured between 0.8V and 2.0V CL=30pF 1.6 ns tr/f-2 Rise and Fall Times. -1, -2, - 3, and -4 versions Measured between 0.8V and 2.0V CL=15pF 1.2 ns tr/f-3 Rise and Fall Times. -1,1H and -5H versions Measured between 0.8V and 2.0V CL=30pF 1.2 ns tr/f-3 Rise and Fall Times. -1H and -5H versions Measured between 0.8V and 2.0V CL=15pF 1.0 ns SKW-1 Output-to-Output on same bank A or B. All versions All outputs are equally loaded. Measured at VDD/2 - 60 150 ps SKW-2 Output Bank-A to Bank-B Skew. -1-4 and -5H versions All outputs are equally loaded. Measured at VDD/2 - 60 150 ps SKW-3 Output Bank-A to Bank-B Skew. -1-4 and -5H versions All outputs are equally loaded. Measured at VDD/2 - 130 300 ps SKW-4 Device-to-Device Skew. All versions All outputs are equally loaded. Measured at VDD/2 and FBK pin - 180 500 ps tCFD CLKIN to FBK Rising Edge Delay All outputs are equally loaded. Measured at VDD/2 -200 - 200 ps t2 Delay Time, CLKIN Rising Edge to CLKOUT Rising Edge (Measured at VDD/2) [2] PLL Bypass mode 1.5 – 4.4 ns PLL enabled @ 3.3V –100 – 100 ps PLL enabled @2.5V –200 – 200 ps t3 Part-to-Part Skew[2] (Measured at VDD/2) Measured at VDD/2. Any output to any output, 3.3V supply – – ±150 ps Measured at VDD/2. Any output to any output, 2.5V supply – – ±300 ps tLOCK PLL Lock Time Valid on all clock pins from VDD=2.97V - - 1.0 ms

Rev 1.0, May 18, 2006 Page 9 of 15 SL23EP08 Symbol Description Condition Min Typ Max Unit FOUT-1 Output Frequency CL=30pf, All devices 10 - 160 MHz FOUT-2 Output Frequency CL=20pF, -1H and -5H versions 10 - 220 MHz FOUT-2 Output Frequency CL=15pF, -1,-2,-3 and -4 versions 10 - 200 MHz DC-1 Duty Cycle. -1, -2, -3,-4,-1H and -5H versions CL=30pF, FOUT=66.6MHz and Measured at VDD/2 40.0 50.0 60.0 % DC-2 Duty Cycle, -1, -2, -3,-4,-1H and -5H versions CL=15pF, FOUT<66.6MHz and Measured at VDD/2 45.0 50.0 55.0 % DC-1 Duty Cycle. -1, -2, -3,-4,-1H and -5H versions CL=30pF, FOUT=120MHz and Measured at VDD/2 TBD TBD TBD % DC-2 Duty Cycle. -1, -2, -3,-4,-1H and -5H versions CL=15pF, FOUT=120MHz and Measured at VDD/2 TBD TBD TBD % tr/f-1 Rise and Fall Times. -1, -2, - 3, and -4 versions Measured between 0.8V and 2.0V CL=30pF 1.6 ns tr/f-2 Rise and Fall Times. -1, -2, - 3, and -4 versions Measured between 0.8V and 2.0V CL=15pF 1.2 ns tr/f-3 Rise and Fall Times. -1,1H and -5H versions Measured between 0.8V and 2.0V CL=30pF 1.2 ns tr/f-3 Rise and Fall Times. -1H and -5H versions Measured between 0.8V and 2.0V CL=15pF 1.0 ns SKW-1 Output-to-Output on same bank A or B. All versions All outputs are equally loaded. Measured at VDD/2 - 60 150 ps SKW-2 Output Bank-A to Bank-B Skew. -1-4 and -5H versions All outputs are equally loaded. Measured at VDD/2 - 60 150 ps SKW-3 Output Bank-A to Bank-B Skew. -1-4 and -5H versions All outputs are equally loaded. Measured at VDD/2 - 130 300 ps SKW-4 Device-to-Device Skew. All versions All outputs are equally loaded. Measured at VDD/2 and FBK pin - 180 500 ps tCFD CLKIN to FBK Rising Edge Delay All outputs are equally loaded. Measured at VDD/2 -200 - 200 ps t2 Delay Time, CLKIN Rising Edge to CLKOUT Rising Edge (Measured at VDD/2) [2] PLL Bypass mode 1.5 – 4.4 ns PLL enabled @ 3.3V –100 – 100 ps PLL enabled @2.5V –200 – 200 ps t3 Part-to-Part Skew[2] (Measured at VDD/2) Measured at VDD/2. Any output to any output, 3.3V supply – – ±150 ps Measured at VDD/2. Any output to any output, 2.5V supply – – ±300 ps tLOCK PLL Lock Time Valid on all clock pins from VDD=2.97V - - 1.0 ms

Rev 1.0, May 18, 2006 Page 10 of 15 SL23EP08 Symbol Description Condition Min Typ Max Unit FOUT-1 Output Frequency CL=30pf, All devices 10 - 160 MHz FOUT-2 Output Frequency CL=20pF, -1H and -5H versions 10 - 220 MHz FOUT-2 Output Frequency CL=15pF, -1,-2,-3 and -4 versions 10 - 200 MHz DC-1 Duty Cycle. -1, -2, -3,-4,-1H and -5H versions CL=30pF, FOUT=66.6MHz and Measured at VDD/2 40.0 50.0 60.0 % DC-2 Duty Cycle, -1, -2, -3,-4,-1H and -5H versions CL=15pF, FOUT<66.6MHz and Measured at VDD/2 45.0 50.0 55.0 % DC-1 Duty Cycle. -1, -2, -3,-4,-1H and -5H versions CL=30pF, FOUT=120MHz and Measured at VDD/2 TBD TBD TBD % DC-2 Duty Cycle. -1, -2, -3,-4,-1H and -5H versions CL=15pF, FOUT=120MHz and Measured at VDD/2 TBD TBD TBD % tr/f-1 Rise and Fall Times. -1, -2, - 3, and -4 versions Measured between 0.8V and 2.0V CL=30pF 1.6 ns tr/f-2 Rise and Fall Times. -1, -2, - 3, and -4 versions Measured between 0.8V and 2.0V CL=15pF 1.2 ns tr/f-3 Rise and Fall Times. -1,1H and -5H versions Measured between 0.8V and 2.0V CL=30pF 1.2 ns tr/f-3 Rise and Fall Times. -1H and -5H versions Measured between 0.8V and 2.0V CL=15pF 1.0 ns SKW-1 Output-to-Output on same bank A or B. All versions All outputs are equally loaded. Measured at VDD/2 - 60 150 ps SKW-2 Output Bank-A to Bank-B Skew. -1-4 and -5H versions All outputs are equally loaded. Measured at VDD/2 - 60 150 ps SKW-3 Output Bank-A to Bank-B Skew. -1-4 and -5H versions All outputs are equally loaded. Measured at VDD/2 - 130 300 ps SKW-4 Device-to-Device Skew. All versions All outputs are equally loaded. Measured at VDD/2 - 180 500 ps tCFD CLKIN to FBK Rising Edge Delay All outputs are equally loaded. Measured at VDD/2 -200 - 200 ps t2 Delay Time, CLKIN Rising Edge to CLKOUT Rising Edge (Measured at VDD/2) [2] PLL Bypass mode 1.5 – 4.4 ns PLL enabled @ 3.3V –100 – 100 ps PLL enabled @2.5V –200 – 200 ps t3 Part-to-Part Skew (Measured at VDD/2) Measured at VDD/2. Any output to any output, 3.3V supply – – ±150 ps Measured at VDD/2. Any output to any output, 2.5V supply – – ±300 ps tLOCK PLL Lock Time Valid on all clock pins from VDD=2.97V - - 1.0 ms

Rev 1.0, May 18, 2006 Page 11 of 15 SL23EP08 External Components & Design Considerations Typical Application Schematic SL23EP08 CL CL 0.1μF 0.1μF CLKIN FBK CLKA1 CLKB4 GND GND VDD VDD 8 5 12 VDD CLKA23 CL-4pF Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1μF must be used between VDD and VSS pins. Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. Series Termination Resistor: A series termination resistor is recommended if the distance between the output clocks and the load is over 1 ½ inch. The nominal impedance of the clock outputs is given on the page 4. Place the series termination resistors as close to the clock outputs as possible. Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay” between the CLKIN and the outputs. The CLKOUT pin is connected to CLKI N internally on-chip for feedback to PLL, and sees an additional 4 pF load with respect to Bank A and B clocks. For applications requiring zero input/output delay, the load at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the CLKOUT pin could be increased or decreased to increase or decrease the delay between Bank A and B clocks and CLKIN. For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same.

Rev 1.0, May 18, 2006 Page 13 of 15 SL23EP08 Package Drawing and Dimensions 16-Lead TSSOP (4.4mm) 0.190(0.007) 0.300(0.012) 0.090(0.003) 0.200(0.008) 6.250(0.246) 6.500(0.256) 4.300(0.169) 4.500(0.177) 2.900(0.114) 3.100(0.122) 0.850(0.033) 0.950(0.037) 0.050(0.002) 0.150(0.006) 1.100(0.043) MAX 0.076(0.003) 0 to 8° 0.500(0.020) 0.700(0.027) 0.650(0.025) BSC Gauge Plane Dimensions are in milimeters(inches). Top line: (MIN) and Bottom line: (Max) Pin-1 ID Seating Plane 0.650(0.025) BSC Thermal Characteristics Parameter Symbol Condition Min Typ Max Unit Thermal Resistance Junction to Ambient θ JA Still air - 80 - °C/W θ JA 1m/s air flow - 70 - °C/W θ JA 3m/s air flow - 68 - °C/W Thermal Resistance Junction to Case θ JC Independent of air flow - 36 - °C/W

Rev 1.0, May 18, 2006 Page 14 of 15 SL23EP08 Package Drawing and Dimensions (Cont.) 0.150(3.810) 0.157(3.987 0.230(5.842) 0.244(6.197) 0.189(4.800) 0.196(4.978) 0.050(1.270) BSC 0.004(0.102) Seating plane0.004(0.102) 0.0098(0.249) 0.061(1.549) 0.068(1.727) 0° to 8° 0.010(0.2540) 0.016(0.406) X 45° 0.016(0.406) 0.035(0.889) 0.0075(0.190) 0.0098(0.249) Pin-1 ID Dimensions are in milimeters(inches). Top line: (MIN) and Bottom line: (Max) 16-Lead SOIC (150 Mil) 916 0.0138(0.350) 0.0192(0.487) Thermal Characteristics Parameter Symbol Condition Min Typ Max Unit Thermal Resistance Junction to Ambient θ JA Still air - 120 - °C/W θ JA 1m/s air flow - 115 - °C/W θ JA 3m/s air flow - 105 - °C/W Thermal Resistance Junction to Case θ JC Independent of air flow - 60 - °C/W

Rev 1.0, May 18, 2006 Page 15 of 15 SL23EP08

Ordering Information

[3] Ordering Number Marking Shipping Package Package Temperature SL23EP08SC-1 SL23EP08SC-1 Tube 16-pin SOIC 0 to 70°C SL23EP08SC-1T SL23EP08SC-1 Tape and Reel 16-pin SOIC 0 to 70°C SL23EP08SI-1 SL23EP08SI-1 Tube 16-pin SOIC -40 to 85°C SL23EP08SI-1T SL23EP08SI-1 Tape and Reel 16-pin SOIC -40 to 85°C SL23EP08SC-1H SL23EP08SC-1H Tube 16-pin SOIC 0 to 70°C SL23EP08SC-1HT SL23EP08SC-1H Tape and Reel 16-pin SOIC 0 to 70°C SL23EP08SI-1H SL23EP08SI-1H Tube 16-pin SOIC -40 to 85°C SL23EP08SI-1HT SL23EP08SI-1H Tape and Reel 16-pin SOIC -40 to 85°C SL23EP08ZC-1H SL23EP08ZC-1H Tube 16-pin TSSOP 0 to 70°C SL23EP08ZC-1HT SL23EP08ZC-1H Tape and Reel 16-pin TSSOP 0 to 70°C SL23EP08ZI-1H SL23EP08ZI-1H Tube 16-pin TSSOP -40 to 85°C SL23EP08ZI-1HT SL23EP08ZI-1H Tape and Reel 16-pin TSSOP -40 to 85°C SL23EP08SC-2 SL23EP08SC-2 Tube 16-pin SOIC 0 to 70°C SL23EP08SC-2T SL23EP08SC-2 Tape and Reel 16-pin SOIC 0 to 70°C SL23EP08SI-2 SL23EP08SI-2 Tube 16-pin SOIC -40 to 85°C SL23EP08SI-2T SL23EP08SI-2 Tape and Reel 16-pin SOIC -40 to 85°C SL23EP08SC-3 SL23EP08SC-3 Tube 16-pin SOIC 0 to 70°C SL23EP08SC-3T SL23EP08SC-3 Tape and Reel 16-pin SOIC 0 to 70°C SL23EP08SI-3 SL23EP08SI-3 Tube 16-pin SOIC -40 to 85°C SL23EP08SI-3T SL23EP08SI-3 Tape and Reel 16-pin SOIC -40 to 85°C SL23EP08SC-4 SL23EP08SC-4 Tube 16-pin SOIC 0 to 70°C SL23EP08SC-4T SL23EP08SC-4 Tape and Reel 16-pin SOIC 0 to 70°C SL23EP08SI-4 SL23EP08SI-4 Tube 16-pin SOIC -40 to 85°C SL23EP08SI-4T SL23EP08SI-4 Tape and Reel 16-pin SOIC -40 to 85°C SL23EP08SC-5H SL23EP08SC-5H Tube 16-pin SOIC 0 to 70°C SL23EP08SC-5HT SL23EP08SC-5H Tape and Reel 16-pin SOIC 0 to 70°C Notes: 3. The SL23EP08 products are RoHS compliant. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authoriz ed for use in applications intended to support or sustain life, or for any other application in whic h the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.