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Technical content
Features
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Description
The SL23EP05 is a low skew, low jitter, and low power Zero Delay Buffer (ZDB) designed to produce up to five clock outputs from one reference input clock for high speed clock distribution applications. The product has an on- chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL23EP05 is available with two drive strength versions called –1 and –1H. The –1 is the standard-drive version and –1H is the high-drive version. The SL23EP05 high-drive version operates up to 220 MHz and 180 MHz at 3.3 V and 2.5 V power supplies, respectively. The standard drive version –1 operates up to 200 MHz and 167 MHz at 3.3 V and 2.5 V, respectively. The SL23EP05 enter into Power Down (PD) mode if the input at CLKIN is less then 2.0 MHz or there is no rising edge. In this state all five outputs are tri-stated and the PLL is turned off leading to less than 10 μA of power supply current draw. 10 to 220 MHz operating frequency range Low output clock jitter: 50 ps-typ cycle-to-cycle jitter 20 ps-typ period jitter Low output-to-output skew: 30 ps-typ Low product-to-product skew: 60 ps-typ Wide 2.5 V to 3.3 V power supply range Low power dissipation: 16 mA-max at 66 MHz and VDD = 3.3 V 14 mA-max at 66 MHz and VDD = 2.5 V One input drives five outputs organized as 4+1 SpreadThru™ PLL that allows use of SSCG Standard and High-Drive options Available in 8 pin SOIC and TSSOP packages Available in Commercial and Industrial grades Printers and MFPs Digital Copiers PCs and Work Stations Routers, Switchers and Servers Digital Embedded Systems Up to five distribution of input clock Standard and High-Drive levels to control impedance level, frequency range and EMI Low power dissipation, jitter and skew Low cost Patents pending Ordering Information: See page 14. Pin Assignments SL23EP05
2 Rev. 2.2 Functional Block Diagram
Rev. 2.2 3 TABLE OF CONTENTS Section Page
- Electrical Specifications
Table 1. DC Electrical Specifications (VDD = 3.3 V) Unless otherwise stated for both C and I Grades. Table 2. DC Electrical Specifications (VDD = 2.5 V) Unless otherwise stated for both C and I Grades.
Table 3. AC Electrical Specifications (VDD = 3.3 V and 2.5 V)
3.3 V Standard Drive 10 — 200 MHz
2.5 V High Drive 10 — 180 MHz
2.5 V Standard Drive 10 — 167 MHz
2.5 V power supply, standard drive
- For the given maximum loading conditions. See CL in Operating Conditions Table.
- Parameter is guaranteed by design and characterization. Not 100% tested in production.
Table 4. AC Electrical Specifications (VDD = 3.3 V and 2.5 V)
3.3 V supply, >66 MHz, <30 pF,
2.5 V supply, >66 MHz, <15 pF,
2.5 V supply, >66 MHz, <30 pF,
3.3 V supply, 66–100 MHz, <15 pF,
2.5 V supply, > 100 MHz, <15 pF,
2.5 V supply, 66–100 MHz, <15 pF,
*Note: Typical jitter is measured at 3.3 V or 2.5 V, 30ºC with all outputs driven into the maximum specified load.
Table 5. Operating Conditions Unless otherwise stated VDD = 2.5 V to 3.3 V and for both C and I Grades.
3.3 V, (typical), Standard Drive 41 Ω
2.5 V, (typical), High Drive 37 Ω
2.5 V, (typical), Standard Drive 41 Ω
Table 6. Thermal Characteristics Table 7. Absolute Maximum Rating
The SL23EP05 is a low skew, low jitter Zero Delay Buffer with very low operating current. output clock drivers tracking the input reference clock for systems requiring clock distribution.
- Input and Output Frequency Range
less than 10 μA supply current. spread profile and modulation frequency.
- High and Low-Drive Product Options
users to control load levels, frequency range and EMI control. Refer to the AC electrical tables for the details. of CLKOUT relative to the banks A and B clocks since CLKOUT is the feedback to the PLL. to a consistent and stable PLL electrical performance in terms of skew, and jitter and power dissipation. Table 8. Input/Output Frequency Range
3.3 HIGH 10 220
3.3 STD 10 200
2.5 HIGH 10 180
2.5 STD 10 167
- External Components and Design Considerations
Figure 1. Typical Application Schematic should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. decrease the delay between clocks and CLKIN. For minimum pin-to-pin skew, the external load at the clocks must be the same.
Figure 5. 8-Pin SOIC Table 9. Pin Descriptions 1 CLKIN Input Reference Frequency Clock Input. Weak pull-down (150 k Ω). 2 CLK2 Output Buffered Clock Output Weak pull-down (150 k Ω). 3 CLK1 Output Buffered Clock Output. Weak pull-down (150 k Ω). 5 CLK3 Output Buffered Clock Output. Weak pull-down (150 k Ω). 6 VDD Power 3.3 V or 2.5 V Power Supply. 7 CLK4 Output Buffered Clock Output. Weak pull-down (150 k Ω). 8 CLKOUT Output Buffered Clock Output. Used for Internal Feedback to PLL Input.
- Package Outline and Dimensions
Figure 6. 8-Lead SOIC (150 mm)
Table 10. Ordering Guide
- The SL23EP05 products are RoHS compliant.
- Minimum Order Quantity (MOQ) is for production orders. Silicon Labs provides lesser
quantities for pre-production samples.
Rev. 2.2 15 CONTACT INFORMATION Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: FMinfo@silabs.com Internet: www.silabs.com Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog- intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea- tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warran- ty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intend- ed to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.