SL2309

SL2309 SILABS | Alldatasheet

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Technical content

Rev 2.0, May 12, 2008 Page 1 of 12 400 West Cesar Chavez, Austin, TX 78701 1 (512) 416-8500 1 (512) 416-9669 www.silabs.com SL2309 Key Features  10 to 140 MHz operating frequency range  Low output clock jitter:  140 ps-max cycle-to-cycle jitter  Low output-to-output skew: 150 ps-max  Low product-to-product skew: 400 ps-max  3.3 V power supply range  Low power dissipation:  26 mA-max at 66 MHz  44 mA –max at 133 MHz  One input drives 9 outputs organized as 4+4+1  Select mode to bypass PLL or tri-state outputs  SpreadThru™ PLL that allows use of SSCG  Standard and High-Drive options  Available in 16-pin SOIC and TSSOP packages  Available in Commercial and Industrial grades

Applications

 Printers and MFPs  Digital Copiers  PCs and Work Stations  DTV  Routers, Switchers and Servers  Digital Embeded Systems

Description

The SL23 09 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for hig h speed clock distribution applications. The product has an on -chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL2309 has two (2) clock driver banks each with four (4) clock outputs. These outp uts are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, four (4) bank-B output clock buffers can be tri- stated to reduce power dissipation and jitter. The select inputs can also be used to tri -state both banks A an d B or drive them directly from the input bypassing the PLL and making the product behave like a Non -Zero Delay Fanout Buffer (NZDB). The high -drive (-1H) version operates up to 140 MHz and low drive (-1) version operates up to 100MHz at 3.3V. Benefits  Up to nine (9) distribution of input clock  Standard and High-Drive levels to control impedance level, frequency range and EMI  Low power dissipation, jitter and skew  Low cost Block Diagram Low Power and Low Jitter PLL MUX Input Selection Decoding Logic VDD GND CLKIN CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)

Rev 2.0, May 12, 2008 Page 2 of 12 SL2309 CLKA1 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 CLKIN CLKA2 VDD GND CLKB1 CLKB2 Pin Description Pin Configuration 16-Pin SOIC and TSSOP Pin Number Pin Name Pin Type Pin Description 1 CLKIN Input Reference Frequency Clock Input. Weak pull-down (250kΩ). 2 CLKA1 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 3 CLKA2 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 4 VDD Power 3.3V Power Supply. 5 GND Power Power Ground. 6 CLKB1 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 7 CLKB2 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 8 S2 Input Select Input, select pin S2. Weak pull-up (250kΩ). 9 S1 Input Select Input, select pin S1. Weak pull-up (250kΩ). 10 CLKB3 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 11 CLKB4 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 12 GND Power Power Ground. 13 VDD Power 3.3V Power Supply. 14 CLKA3 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 15 CLKA4 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 16 CLKOUT Output Buffered Clock Output, PLL Internal Feedback Output. Weak pull-down (250kΩ).

for systems requiring clock distribution. Table 1. Input/Output Frequency Range product draws less than 12μA-max supply current. on drive levels and load specifications. the switching electrical tables for the details. and B clocks since CLKOUT is the feedback to the PLL. of skew, jitter and power dissipation.

Figure 1. CLKIN Input to CLK A and B Delay Table 2. Select Input Decoding

Rev 2.0, May 12, 2008 Page 5 of 12 SL2309 Absolute Maximum Ratings Operating Conditions: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Description Condition Min Max Unit Supply voltage, VDD – 0.5 4.6 V All Inputs and Outputs – 0.5 VDD+0.5 V Ambient Operating Temperature In operation, C-Grade 0 70 °C Ambient Operating Temperature In operation, I-Grade – 40 85 °C Storage Temperature No power is applied – 65 150 °C Junction Temperature In operation, power is applied – 125 °C Soldering Temperature – 260 °C ESD Rating (Human Body Model) JEDEC22-A114D -4,000 4,000 V ESD Rating (Charge Device Model) JEDEC22-C101C -1,500 1,500 V ESD Rating (Machine Model) JEDEC22-A115D -250 250 V Latch-up 125°C -200 200 mA Symbol Description Condition Min Max Unit VDD 3.3V Supply Voltage 3.3V+/-10% 3.0 3.6 V TA Operating Temperature(Ambient) Commercial 0 70 °C Industrial – 40 85 °C CLOAD Load Capacitance 10 to 140 MHz, -1H high drive All active PLL modes – 15 pF 10 to 100 MHz, -1H high drive All active PLL modes – 30 pF 10 to 100MHz, -1 standard drive All active PLL modes – 15 pF 10 to 66MHz, -1 standard drive All active PLL modes – 30 pF CIN Input Capacitance S1, S2 and CLKIN pins – 7 pF tpu Power-up Time Power-up time for all VDDs to reach minimum VDD voltage (VDD=3.0V). 0.05 100 ms CLBW Closed-loop bandwidth 3.3V, (typical) 1.2 MHz ZOUT Output Impedance 3.3V, (typical), -1H high drive 22 Ω 3.3V, (typical), -1 standard drive 32 Ω

Rev 2.0, May 12, 2008 Page 6 of 12 SL2309 Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol Description Condition Min Max Unit VDD Supply Voltage 3.0 3.6 V VIL Input LOW Voltage CLKIN, S2 and S1 Pins – 0.8 V VIH Input HIGH Voltage CLKIN, S2 and S1 pins 2.0 VDD+0.3 V IIL Input LOW Current CLKIN, S2 and S1 Pins, 0 < VIN < 0.8V – 25 µA IIH Input HIGH Current CLKIN, S2 and S1 Pins, VIN = VDD – 50 µA VOL Output LOW Voltage (All outputs) IOL = 8 mA (standard drive) – 0.4 V IOL = 12 mA (high drive) – 0.4 V VOH Output HIGH Voltage (All outputs) IOH = –8 mA (standard drive) 2.4 – V IOH = –12 mA (high drive) 2.4 – V IDDPD Power Down Supply Current CLKIN=0 to VDD or floating (input will be pulled-down by 250kΩ weak pull-down on-chip resistor) C-Grade – µA I-Grade – µA IDD1 Power Supply Current All Outputs CL=0, 33MHz CLKIN S2=S1=1 (High) – 14 mA IDD2 Power Supply Current All Outputs CL=0, 66MHz CLKIN S2=S1=1 (High) – 26 mA IDD3 Power Supply Current All Outputs CL=0, 100MHz CLKIN S2=S1=1 (High) – 36 mA IDD4 Power Supply Current All Outputs CL=0, 133MHz CLKIN S2=S1=1 (High) – 44 mA RPU/D Pull-up and Pull-down Resistors Pins-1/2/3/6/7/8/9/10/11/14/15/16 250kΩ-typ 175 325 kΩ Symbol Description Condition Min Typ Max Unit FMAX1 Maximum Frequency [1] (Input=Output ) All Active PLL Modes High drive (-1H). All outputs CL=15pF 10 – 140 MHz High drive (-1H), All outputs CL=30pF 10 – 100 MHz Standard drive, (-1), All outputs CL=15pf 10 – 100 MHz Standard drive, (-1), All outputs CL=30pf 10 – 66 MHz FMAX2 Maximum Frequency [1] (Input=Output ) PLL Bypass Mode (S2=1 and S1=0) High drive (-1H). All outputs CL=15pF 0 – 140 MHz High drive (-1H), All outputs CL=30pF 0 – 100 MHz Standard drive, (-1), All outputs CL=15pf 0 – 100 MHz Standard drive, (-1), All outputs CL=30pf 0 – 66 MHz INDC Input Duty Cycle Measured at 1.4V, Fout=66MHz, CL=15pF 30 50 70 % OUTDC1 Output Duty Cycle[2] Measured at 1.4V, Fout=66MHz, CL=15pF 40 50 60 % OUTDC2 Output Duty Cycle[2] Measured at 1.4V, Fout=66MHz, CL=15pF 40 50 60 %

Rev 2.0, May 12, 2008 Page 7 of 12 SL2309 Notes: 1. For the given maximum loading conditions. See CL in Operating Conditions Table. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. tr/f Rise, Fall Time (3.3V) [2] (Measured at: 0.8 to 2.0V) High drive (-1H), CL=15pF – – 1.5 ns High drive (-1H), CL=30pF – – 1.8 ns Standard drive (-1), CL=15pF – – 2.2 ns Standard drive (-1), CL=30pF – – 2.5 ns t1 Output-to-Output Skew[2] (Measured at VDD/2) All outputs CL=0 or equally loaded, -1 or -1H drives – 70 150 ps t2 Product-to-Product Skew[2] (Measured at VDD/2) All outputs CL=0 or equally loaded, -1 or -1H drives – 180 400 ps t3 Delay Time, CLKIN Rising Edge to CLKOUT Rising Edge[2] (Measured at VDD/2) PLL Bypass mode Only when S2=1 and S1=0 1.5 5 8.7 ns PLL enabled All active PLL modes –220 – 220 ps tPLOCK PLL Lock Time[2] Time from 90% of VDD to valid clocks on all the output clocks – – 1.0 ms CCJ Cycle-to-cycle Jitter [2] Fin=Fout=66 MHz, <CL=15pF, -1H drive – 70 140 ps Fin=Fout=66 MHz, <CL=15pF, -1 drive – 75 150 ps Fin=Fout=66 MHz, <CL=30pF, -1H drive – 80 160 ps Fin=Fout=66 MHz, <CL=30pF, -1 drive – 85 170 ps

Rev 2.0, May 12, 2008 Page 8 of 12 SL2309 External Components & Design Considerations Typical Application Schematic SL2309 CL CL CL 0.1μF 0.1μF CLKIN CLKOUT CLKA1 CLKB4 GND GND VDD VDD 8 5 12 VDD Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1μF must be used between VDD and VSS pins. Place the capacitor s on the component side of the PCB as close to the VDD pin s as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. Series Termination Resistor: A series termination resistor is recommended if the distance between the output clocks and the load is over 1 ½ inch. The nominal impedance of the clock outputs is given on the page 4. Place the series termination resistors as close to the clock outputs as possible. Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Z ero Delay” between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on -chip for feedback to PLL, and sees an additional 2 pF load with respect to Bank A and B clocks. For applications requiring zero input/output delay, the load at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the CLKOUT pin could be increased or decreased to increase or decrease the delay between Bank A and B clocks and CLKIN. For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same.

Rev 2.0, May 12, 2008 Page 10 of 12 SL2309 Package Drawing and Dimensions 16-Lead TSSOP (4.4-mm) 0.190(0.007) 0.300(0.012) 0.090(0.003) 0.200(0.008) 6.250(0.246) 6.500(0.256) 4.300(0.169) 4.500(0.177) 4.900(0.193) 5.100(0.200) 0.850(0.033) 0.950(0.037) 0.050(0.002) 0.150(0.006) 1.100(0.043) MAX 0.076(0.003) 0 to 8° 0.500(0.020) 0.700(0.027) 0.650(0.025) BSC Gauge Plane Dimensions are in milimeters(inches). Top line: (MIN) and Bottom line: (Max) Pin-1 ID Seating Plane 0.650(0.025) BSC Thermal Characteristics Parameter Symbol Condition Min Typ Max Unit Thermal Resistance Junction to Ambient θ JA Still air - 80 - °C/W θ JA 1m/s air flow - 70 - °C/W θ JA 3m/s air flow - 68 - °C/W Thermal Resistance Junction to Case θ JC Independent of air flow - 36 - °C/W

Rev 2.0, May 12, 2008 Page 11 of 12 SL2309 Package Drawing and Dimensions (Cont.) 0.150(3.810) 0.157(3.987 0.230(5.842) 0.244(6.197) 0.386(9.804) 0.393(9.982) 0.050(1.270) BSC 0.004(0.102) Seating plane0.004(0.102) 0.0098(0.249) 0.061(1.549) 0.068(1.727) 0° to 8° 0.010(0.2540) 0.016(0.406) X 45° 0.016(0.406) 0.035(0.889) 0.0075(0.190) 0.0098(0.249) Pin-1 ID Dimensions are in inches(milimeters). Top line: (MIN) and Bottom line: (Max) 16-Lead SOIC (150-Mil) 916 0.0138(0.350) 0.0192(0.487) Thermal Characteristics Parameter Symbol Condition Min Typ Max Unit Thermal Resistance Junction to Ambient θ JA Still air - 120 - °C/W θ JA 1m/s air flow - 115 - °C/W θ JA 3m/s air flow - 105 - °C/W Thermal Resistance Junction to Case θ JC Independent of air flow - 60 - °C/W

Rev 2.0, May 12, 2008 Page 12 of 12 SL2309 Ordering Information [3] Ordering Number Marking Shipping Package Package Temperature SL2309BZC-1H SL2309BZC-1H Tube 16-pin TSSOP 0 to 70°C SL2309BZC-1HT SL2309BZC-1H Tape and Reel 16-pin TSSOP 0 to 70°C SL2309BZI-1H SL2309BZI-1H Tube 16-pin TSSOP -40 to 85°C SL2309BZI-1HT SL2309BZI-1H Tape and Reel 16-pin TSSOP -40 to 85°C SL2309BSC-1 SL2309BSC-1 Tube 16-pin SOIC 0 to 70°C SL2309BSC-1T SL2309BSC-1 Tape and Reel 16-pin SOIC 0 to 70°C SL2309BSC-1H SL2309BSC-1H Tube 16-pin SOIC 0 to 70°C SL2309BSC-1HT SL2309BSC-1H Tape and Reel 16-pin SOIC 0 to 70°C SL2309BSI-1 SL2309BSI-1 Tube 16-pin SOIC -40 to 85°C SL2309BSI-1T SL2309BSI-1 Tape and Reel 16-pin SOIC -40 to 85°C SL2309BSI-1H SL2309BSI-1H Tube 16-pin SOIC -40 to 85°C SL2309BSI-1HT SL2309BSI-1H Tape and Reel 16-pin SOIC -40 to 85°C Rev A part numbers below are not recommended for new designs SL2309ZC-1[4] SL2309ZC-1 Tube 16-pin TSSOP 0 to 70°C SL2309ZC-1T[4] SL2309ZC-1 Tape and Reel 16-pin TSSOP 0 to 70°C SL2309ZC-1H[4] SL2309ZC-1H Tube 16-pin TSSOP 0 to 70°C SL2309ZC-1HT[4] SL2309ZC-1H Tape and Reel 16-pin TSSOP 0 to 70°C SL2309ZI-1[4] SL2309ZI-1 Tube 16-pin TSSOP -40 to 85°C SL2309ZI-1T[4] SL2309ZI-1 Tape and Reel 16-pin TSSOP -40 to 85°C SL2309ZI-1H[4] SL2309ZI-1H Tube 16-pin TSSOP -40 to 85°C SL2309ZI-1HT[4] SL2309ZI-1H Tape and Reel 16-pin TSSOP -40 to 85°C SL2309SC-1[4] SL2309SC-1 Tube 16-pin SOIC 0 to 70°C SL2309SC-1T[4] SL2309SC-1 Tape and Reel 16-pin SOIC 0 to 70°C SL2309SC-1H[4] SL2309SC-1H Tube 16-pin SOIC 0 to 70°C SL2309SC-1HT[4] SL2309SC-1H Tape and Reel 16-pin SOIC 0 to 70°C SL2309SI-1[4] SL2309SI-1 Tube 16-pin SOIC -40 to 85°C SL2309SI-1T[4] SL2309SI-1 Tape and Reel 16-pin SOIC -40 to 85°C SL2309SI-1H[4] SL2309SI-1H Tube 16-pin SOIC -40 to 85°C SL2309SI-1HT[4] SL2309SI-1H Tape and Reel 16-pin SOIC -40 to 85°C Notes: 3. The SL2309 products are RoHS compliant. 4. Not recommended for new designs

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