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Rev 2.6, August 1, 2010 Page 1 of 8 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com SL16010DC Key Features
- Low power dissipation - 13.5mA-typ CL=15pF - 18.0mA-max CL=15pF
- 3.3V +/-10% power supply range
- 27.000MHz crystal or clock input
- 27.000MHz REFCLK
- 100MHz SSCLK with SSEL0/1 spread options
- Low CCJ Jitter
- Low LT Jitter
- Internal Voltage Regulators
- 45% to 55% Output Duty Cycle
- On-chip Crystal Oscillator
- -10 to +85 Temperature Range
- 10-pin 3x3x0.75 mm TDFN package Application
- Video Cards
- NB and DT PCs
- HDTV and DVD-R/W
- Routers, Switches and Servers
- Data Communications
- Embeded Digital Applications
Description
The SL16010DC is a low power dissipation spread spectrum clock generator using SLI proprietary low jitter PLL. The SL16010DC provides two output clocks. REFCLK (Pin-9) which is a buffered output of the 27.000MHz input crystal and SSCLK (Pin-5) which is synthesized as 100.000MHz nominal by an internal PLL using the 27.00MHz external input crystal or clock. In addition, SSEL0 (Pin-7) and SSEL1 (Pin-3) spread percent selection control inputs enable users to select from 0.0% (no spread) to -3.0% down spread at 100.000MHz SSCLK output to reduce and optimize system EMI levels. The SL16010DC operates in an extended temperature range of -10 to +85°C. Contact SLI for other programmable frequencies, Spread Spectrum Clock (SSC) options, as well as 2.5V+/-10 and 1.8V+/-5% power supply options. Benefits
- EMI Reduction
- Improved Jitter
- Low Power Dissipation
- Eleminates external Xtals or XOs Block Diagram Low Jitter PLL With Modulation Control Input Decoder 4 6 7 3 300K SSCLK 100.000MHzXIN/CLKIN XOUT VDD1 VSS1 SSEL0 SSEL1
9 REFCLK
27.000MHz 8 2 VSS2VDD2 Figure 1. Block Diagram
Figure 2. 10-Pin TDFN (3x3x0.75 mm) Table 1. Pin Description 1 XIN/CLKIN Input External crystal or clock input. Capacitance at this pin is 4 pF-typ. 2 VSS2 Power Power supply ground for 27.000MHz REFCLK output. 4 VDD1 Power Positive power supply for 100.000MHz SSCLK output. 3.3V +/-10%. spread % options by using SSEL0 and SSEL1 control pins. 6 VSS1 Power Power supply ground for 100.000MHz SSCLK output. 8 VDD2 Power Positive power supply for 27.000MHz REFCLK output. 3.3V +/-10%. 9 REFCLK Output REFCLK clock output. 27.000MHz nominal. leave this pin not connected (N/C).
Table 2. Absolute Maximum Ratings Table 3. DC Electrical Characteristics (C-Grade) Table 4. AC Electrical Characteristics (C-Grade)
Table 5. SSEL1 and SSEL0 versus Spread % Selection at SSCLK Note: Middle (VDD/2) state requires 5kΩ/5kΩ external resistors as shown in Figure 3, page 5.
Table 6. Recommended Crystal Specifications Figure 3. FSEL0 and FSEL1 Spread % Selection Logic 3-Level logic to provide 9 spread % values at SSCLK (pin 5) as given in Table 5. for M=VDD/2 Logic level as shown above in Figure 3.
Figure 4. Typical Application Schematic Cp is the parasitic capacitance of the PCB traces. the SL1610DC product. Users must verify Cp value. capacitor and the VDD1/2 pins. In addition, a 10uf capacitor should be placed between VDD and VSS. to the clock outputs as possible.
Table 7. Thermal Characteristics
Table 8. Ordering Information
- SL16010DC is RoHS compliant and Halogen Free.
Rev 0.5 12/12/2009 C. Ozdalga Original. Rev 1.0 1/30/2009 C. Ozdalga Reduce IDD-max to 18 mA from 28 mA. Change Cxin/Cxot from 4 pF to 6 pF. Rev 2.0 2/30/2009 C. Ozdalga Final production version revision number change to Rev 2.0. Rev 2.1 4/14/2009 C. Ozdalga Correct Page 7 package pin number typing error. Rev 2.2 4/22/2009 C. Ozdalga Page 3 CIN1, CXI/CXOUT pin capacitance changed to 4pF-typ from 6pF-typ. on pin description table page 2 for SSEL1 and SSEL0 rows. Rev 2.4 9/3/2009 C. Ozdalga Replace “floating” with “VDD/2” in table 5 on page 4 under SSEL1. Rev 2.6 8/1/2010 C. Ozdalga Add Halogen Free, page 8. Laboratories harmless against all claims and damages.