SI056DC1-EVB

SI3056 SILABS | Alldatasheet

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Technical content

Features

Complete DAA includes the following:

Applications

Description

The Si3056 is an integrated direct access arrangement (DAA) with a programmable line interface to meet global telephone line requirements. Available in two 16-pin small outline packages, it eliminates the need for an analog front end (AFE), isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The Si3056 dramatically reduces the nu mber of discrete components and cost required to achieve compliance with global regulatory requirements. The Si3056 interfaces directly to standard modem DSPs. Functional Block Diagram „ Programmable line interface z AC termination z DC termination z Ring detect threshold z Ringer impedance „ 80 dB dynamic range TX/RX paths „ Integrated codec and 2- to 4-wire hybrid „ Integrated ring detector „ Type I and II caller ID support „ Line voltage monitor „ Loop current monitor „ Polarity reversal detection „ Programmable digital gain „ Clock generation „ Pulse dialing support „ Overload detection „ 3.3 V power supply „ Direct interface to DSPs „ Serial interface control for up to eight devices „ >5000 V isolation „ Proprietary isolation technology „ Parallel handset detection „ +3.2 dBm TX/RX level mode „ Programmable digital hybrid for near- end echo reduction „ Low-profile SOIC packages „ Lead-free/RoHS-compliant packages available „ V.92 modems „ Voice mail systems „ Multi-function printers „ Set-top boxes „ Fax machines „ Internet appliances „ Personal digital assistants Isolation Interface Hybrid and dc Termination Ring Detect Off-Hook Isolation Interface Digital Interface Control Interface Si3056 Si3018/19/10 QE2 QE QB RNG2 RNG1 DCT3 DCT2 VREG2 VREG DCT SC IB RXMCLK SCLK FSYNC SDI SDO FC/RGDT RGDT/FSD/M1 OFHK RESET AOUT/INT US Patent # 5,870,046 US Patent # 6,061,009 Other Patents Pending

Ordering Information

See page 88. Pin Assignments Si3056 Si3018/19/10 FC/RGDT 16MCLK FSYNC SCLK VD SDO SDI RESET OFHK RGDT/FSD/M1 VA GND AOUT/INT C1A C2A

16 DCT2

2 Rev. 1.05

Rev. 1.05 3 Si3056 Si3018/19/10 TABLE OF C ONTENTS Section Page

4 Rev. 1.05

1. Electrical Specifications

Table 1. Recommended Operating Conditions

1. The Si3056 specifications are guaranteed when the typical application circuit (including component tolerance) and the

Si3056 and any Si3018 or Si3019 are used. See Figure 17 on page 18 for typical application schematic.

1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.

1. 3.3 V applies to both the digital and serial interface and the digital signals RGDT/FSD, OFHK, RESET, M0, and M.

Figure 1. Test Circuit for Loop Characteristics Table 2. Loop Characteristics

Table 3. DC Characteristics, VD =3 . 3 V

1. All inputs at 0.4 or VD – 0.4 (CMOS levels). All inputs are held static except clock and all outputs unloaded
2. RGDT is not functional in this state.

Table 4. AC Characteristics

1. See Figure 26 on page 37.
2. Measured at TIP and RING with 600 Ω termination at 1 kHz, as shown in Figure 1.
3. With FULL = 1, the transmit and receive full scale level of +3.2 dBm can be achieved with a 600Ω ac termination, while
4. Receive full scale level produces –0.9 dBFS at SDO.
5. DR = 20 x log (RMS VFS/RMS VIN).+ 20 x log (RMS VIN/RMS noise). The RMS noise measurement excludes

harmonics. VFS is the 0 dBm full-scale level.

1. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths. VIN = 1 kHz, –3 dBFS, Fs = 10300 Hz.
2. When using the Si3010 line-side, the typical DR values will be approximately 10 dB lower.
3. THD = 20 x log (RMS distortion/RMS signal). VIN = 1 kHz, –3 dBFS, Fs = 10300 Hz.
4. When using the Si3010 line-side, the typical THD values will be approximately 10 dB higher.
5. DRCID = 20 x log (RMS VCID/RMS VIN) + 20 x log(RMS VIN/RMS noise). VCID is the 6 V full-scale level for the typical
6. Available on the Si3019 line-side device only.

Table 4. AC Characteristics (Continued)

1. See Figure 26 on page 37.
2. Measured at TIP and RING with 600 Ω termination at 1 kHz, as shown in Figure 1.
3. With FULL = 1, the transmit and receive full scale level of +3.2 dBm can be achieved with a 600Ω ac termination, while
4. Receive full scale level produces –0.9 dBFS at SDO.
5. DR = 20 x log (RMS VFS/RMS VIN).+ 20 x log (RMS VIN/RMS noise). The RMS noise measurement excludes

harmonics. VFS is the 0 dBm full-scale level.

1. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths. VIN = 1 kHz, –3 dBFS, Fs = 10300 Hz.
2. When using the Si3010 line-side, the typical DR values will be approximately 10 dB lower.
3. THD = 20 x log (RMS distortion/RMS signal). VIN = 1 kHz, –3 dBFS, Fs = 10300 Hz.
4. When using the Si3010 line-side, the typical THD values will be approximately 10 dB higher.
5. DRCID = 20 x log (RMS VCID/RMS VIN) + 20 x log(RMS VIN/RMS noise). VCID is the 6 V full-scale level for the typical
6. Available on the Si3019 line-side device only.

Figure 2. General Inputs Timing Diagram Table 5. Absolute Maximum Ratings rating conditions for extended periods might affect device reliability. Table 6. Switching Characteristics—General Inputs

1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are

VIH = VD – 0.4 V, VIL = 0.4 V. Rise and fall times are referenced to the 20% and 80% levels of the waveform.

1. The minimum RESET pulse width is the greater of 250 ns or 10 MCLK cycle times.
2. M0 and M are typically connected to VD or GND and should not be changed during normal operation.

Figure 3. Serial Interface Timing Diagram (DCE = 0) Table 7. Switching Characteristics—Serial Interface (Master Mode, DCE = 0) Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH =V D – 0.4 V, VIL =0 . 4V .

Figure 4. Serial Interface Timing Diagram (DCE = 1, FSD = 0) Table 8. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 0)

1. See "5.27.Multiple Device Support" on page 38 for functional details.

32 SCLKs

16 SCLKs 16 SCLKs

Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1) Table 9. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 1)

1. See "5.27.Multiple Device Support" on page 38 for functional details.

Figure 6. Serial Interface Timing Diagram (Slave Mode, DCE = 1, FSD = 1) Table 10. Switching Characteristics—Serial Interface (Slave Mode, DCE = 1, FSD = 1) *Note: Tsu1 and Th1 are listed for applications where the controller drives the MCLK and FSYNC instead of a master DAA.

Table 11. Digital FIR Filter Characteristics—Transmit and Receive Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 7, 8, 9, and 10. Table 12. Digital IIR Filter Characteristics—Transmit and Receive group delay versus input frequency.

1. Typical Application Schematic

Figure 17. Typical Application Circuit for the Si3056 and Si3018/19/10

Rev. 1.05 19 3. Bill of Materials Component(s) Value Supplier(s) C1, C2 33 pF, Y2, X7R, ±20% Panasonic, Murata, Vishay C31 10 nF, 250 V, X7R, ±10% Venkel, SMEC C4 1.0 uF, 50 V, Elec/Tant, ±20% Panasonic C5, C6, C50, C51 0.1 uF, 16V, X7R, ±20% Venkel, SMEC C7 2.7 nF, 50V, X7R, 20% Venkel, SMEC C8, C9 680 pF, Y2, X7R, ±10% Panasonic, Murata, Vishay C10 0.01 uF, 16 V, X7R, ±20% Venkel, SMEC C30, C313 Not installed, 120 pF, 250V, X7R, ±10% Venkel, SMEC D1, D22 Dual Diode, 225 mA, 300 V, CMPD2004S Central Semiconductor FB1, FB2 Ferrite Bead, BLM18AG601SN1B Murata Q1, Q3 NPN, 300 V, MMBTA42 OnSemi, Fairchild Q2 PNP, 300 V, MMBTA92 OnSemi, Fairchild Q4, Q5 NPN, 80 V, 330 mW, MMBT2484 OnSemi, Fairchild RV1 Sidactor, 275 V, 100 A Teccor, Protek, ST Micro R1 1.07 kohm, 1/2 W, 1% Venkel, SMEC, Panasonic R2 150 ohm, 1/16 W, 5% Venkel, SMEC, Panasonic R3 3.65 kohm, 1/2 W, 1% Venkel, SMEC, Panasonic R4 2.49 kohm, 1/2 W, 1% Venkel, SMEC, Panasonic R5, R6 100 kohm, 1/16 W, 5% Venkel, SMEC, Panasonic R7, R83

20 Mohm, 1/16 W, 5% Venkel, SMEC, Panasonic

R9 1 Mohm, 1/16 W, 1% Venkel, SMEC, Panasonic R10 536 ohm, 1/4 W, 1% Venkel, SMEC, Panasonic R11 73.2 ohm, 1/2 W, 1% Venkel, SMEC, Panasonic R12, R13 56.2 ohm, 1/16 W, 1% Venkel, SMEC, Panasonic R15, R164 0 ohm, 1/16 W Venkel, SMEC, Panasonic R30, R323 Not installed, 15 Mohm,, 1/8 W, 5% Venkel, SMEC, Panasonic R31, R333 Not installed, 5.1 Mohm,, 1/8 W, 5% Venkel, SMEC, Panasonic R51, R52 4.7 kohm,, 1/10 W, 5% Venkel, SMEC, Panasonic U1 Si3056 Silicon Labs U2 Si3018/19/10 Silicon Labs Z1 Zener Diode, 43 V, 1/2 W, ZMM43 General Semiconductor 3. C30-31 and R30-33 can be substitued for R7-8 to implent the enhanced caller ID circuit. 2. Several diode bridge configurations are acceptable, parts such as a single DF-04S or four 1N4004 diodes may be used (suppliers include General Semiconductor, Diodes Inc., etc.) 4. Murata BLM18AG601SN1B may be substituted for R15-R16 (0 ohm) to decrease emissions. 1. Value for C3 above is recommended for use with the Si3018. In voice appliations, a C3 value of 3.9 nF (250 V, X7R, 20%) is recommended to improve return loss performance

Rev. 1.05 21 5. Functional Description The Si3056 is an integrated direct access arrangement (DAA) that provides a programmable line interface to meet global telephone line interface requirements. The Si3056 implements Silicon Laboratories ® patented isolation technology and offers the highest level of integration by replacing an analog front end (AFE), an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid with two 16-pin packages. The Si3056 DAA is software programmable to meet global requirements and is compliant with FCC, TBR21, JATE, and other country-spec ific PTT specifications as shown in Table 16 on page 26. In addition, the Si3056 meets the most stringent worldwide requirements for out-of-band energy, emissions, immunity, high-voltage surges, and safety, including FCC Part 15 and 68, EN55022, EN55024, and many other standards. 5.1. Upgrading from the Si3034/35/44 to Si3056 The Si3056 offers Silicon Laboratories ® customers currently using Si3034/35/44 standard serial interface DAA chipsets with an upgrade path for use in new designs. The Si3056 digital interface is similar to the Si3034/35/44 DAAs, thus the Si3056 retains the ability to connect to many widely available DSPs. This also allows customers to leverage software developed for existing Si3034/35/44 designs. More importantly, the Si3056 also offers a number of new features not provided in the Si3034/35/44 DAAs. An overview of the feature differences between the Si3044 and the Si3056 is presented in Table 14. Finally, the globally-compliant Si3056 can be implemented with roughly half the external components required in the already highly integrated Si3034/35/44 DAA application circuits. The following items have changed in the Si3056 as compared to the Si3034/35/44 DAAs: „ The pinout, the application circuit, and the bill of materials. The Si3056 is not pin compatible with Si3034/35/44 DAA chipsets. „ New features have been added to the Si3056 including more ac terminations, a programmable hybrid, finer gain/attenuation step resolution, finer resolution loop current monitoring capability, ring validation, more HW interrupts, a 200 Hz low frequency filter pole. (See the appropriate functional descriptions.) „ The secondary communication data format (see "5.26.Digital Interface" on page 37). „ The low-power sleep mode, and system requirements to support wake-on-ring. (See "5.28.Power Management" on page 39.) 5.2. Line-Side Device Support Three different line-side devices can be used with the Si3056 system-side device: „ Globally-compliant line-side device—Targets global DAA requirements. Use the Si3018 global line-side device for this configuration. This line-side device supports both FCC-compliant countries and non- FCC-compliant countries. „ Globally-compliant, enhanced features line-side device—Targets embedded and voice applications with global DAA requirements. Use the Si3019 line- side device for this configuration. The Si3019 contains all the features available on the Si3018, plus the following additional features/enhancements: z Sixteen selectable ac terminations to increase return loss and trans-hybrid loss performance. z Higher transmit and receive level mode. z Selectable 200 Hz low frequency pole. z –16 to 13.5 dB digital gain/attenuation adjustment in 0.1 dB increments for the transmit and receive paths. z Programmable line current/voltage threshold interrupt. „ Globally-compliant, low-speed only line-side device—Targets embedded 2400 bps soft modem applications. Use the Si3010 line-side device for this configuration. The Si3010 contains all the features available on the Si3018, except the transmit and receive paths are optimized and tested only for modem connect rates up to 2400 bps.

Table 14. New Si3056 Features

Table 15. Country Specific Register Settings

1. Supported for loop current ≥ 20 mA.
2. Available with Si3019 line-side only.
3. Available with Si3018 and Si3010 line-sides only.
4. See "5.11.DC Termination" on page 27 for DCV and MINI settings.
5. ACIM is 0000 for data applications and 1010 for voice applications.
6. For South Korea, set the TB3 bit in conjunction with the RZ bit. (See Register 59 description.)

Table 15. Country Specific Register Settings (Continued)

1. Supported for loop current ≥ 20 mA.
2. Available with Si3019 line-side only.
3. Available with Si3018 and Si3010 line-sides only.
4. See "5.11.DC Termination" on page 27 for DCV and MINI settings.
5. ACIM is 0000 for data applications and 1010 for voice applications.
6. For South Korea, set the TB3 bit in conjunction with the RZ bit. (See Register 59 description.)

Rev. 1.05 25 5.3. Power Supplies The Si3056 system-side device operates from a 3.0– 3.6 V power supply. The Si3056 input pins are 5 V tolerant. The Si3056 output pins only drive 3.3 V. The line-side device derives its power from two sources: The Si3056 and the telephone line. The Si3056 supplies power over the patented isolation link between the two devices, allowing the line-side device to communicate with the Si3056 while on-hook and perform other on- hook functions such as line voltage monitoring. When off-hook, the line-side device also derives power from the line current supplied from the telephone line. This feature is exclusive to DAAs from Silicon Laboratories and allows the most cost-effective implementation for a DAA while still maintaining r obust performance over all line conditions. 5.4. Initialization When the Si3056 is powered up, assert the RESET pin. When the RESET pin is deasserted, the registers have default values. This reset condition guarantees the line- side device is powered do wn without the possibility of loading the line (i.e., off-hook ). An example initialization procedure is outlined in the following list: 1. Program the PLL with registers 8 and 9 (N[7:0], M[7:0]) to the appropriate divider ratios for the supplied MCLK frequency and the sample rate in register 7 (SRC), as defined in "5.25.Clock Generation" on page 36. 2. Wait 1 ms until the PLL is locked. 3. Write a 00H into Register 6 to power up the line-side device. 4. Set the required line interface parameters (i.e., DCV[1:0], MINI[1:0], ILIM, DCR, ACT and ACT2 or ACIM[3:0], OHS, RT, RZ, ATX[2:0] or TGA2 and TXG2) as defined by “Country Specific Register Settings” shown in Table 15. When this procedure is complete, the Si3056 is ready for ring detection and off-hook. 5.5. Isolation Barrier The Si3056 achieves an isolation barrier through low- cost, high-voltage capacitors in conjunction with Silicon Laboratories ® proprietary signal processing techniques. These techniques eliminat e signal degradation from capacitor mismatches, common mode interference, or noise coupling. As shown in Figure 17 on page 18, the C1, C2, C8, and C9 capacitors isolate the Si3056 (system-side) from the line-side device. Transmit, receive, control, ring detect, and caller ID data are passed across this barrier. Y2 class capacitors can be used to achieve surge performance of 5 kV or greater. The capacitive communications link is disabled by default. To enable it, the PDL bit (Register 6, bit 4) must be cleared. No communication between the system- side and line-side can occur until this bit is cleared. The clock generator must be programmed to an acceptable sample rate before clearing the PDL bit. 5.6. Transmit/Receive Full Scale Level (Si3019 Line-Side Only) The Si3056 supports programmable maximum transmit and receive levels. The default signal level supported by the Si3056 is 0 dBm into a 600 Ω load. Two additional modes of operation offer increased transmit and receive level capability to enable use of the DAA in applications that require higher signal levels. The full scale mode is enabled by setting the FULL bit in Register 31. With FULL = 1, the full scale signal level increases to +3.2 dBm into a 600 Ω load, or 1 dBV into all reference impedances. The enhanced full scale mode (or 2X full scale) is enabled by setting the FULL2 bit in Register 30. Will FULL2 = 1, the full scale signal level increases to +6.0 dBm into a 600 Ω load, or 1.5 dBV into all reference impedances. The full scale and enhanced full scale modes provide the abilit y to trade off TX power and TX distortion for a peak signal. By using the programmable digital gain registers in conjunction with the enhanced full scale signal level mode, a specific power level (+3.2 dBm for example) could be achieved across all ACT settings. 5.7. Parallel Handset Detection The Si3056 can detect a parallel handset going off- hook. When the Si3056 is off-hook, the loop current can be monitored with the LCS bits. A significant drop in loop current signals that a parallel handset is going off- hook. If a parallel handset causes the LCS bits to read all 0s, the Drop-Out Detect (DOD) bit can be checked to verify a valid line exists. The LVS bits can be read to determine the line voltage when on-hook and off-hook. Significant drops in line voltage can signal a parallel handset. For the Si3056 to operate in parallel with another handset, the parallel handset must have a sufficiently high dc termination to support two off-hook DAAs on the same line. Improved parallel handset operation can be achieved by changing the dc impedance from 50 to 800 Ω and reducing the DCT pin voltage with the DVC[1:0] bits. 5.8. Line Voltage/Loop Current Sensing The Si3056 can measure loop current and line voltage with the Si3010, Si3018, and the Si3019 line-side devices. The 8-bit LCS2[7:0] and LCS[4:0] registers report loop current. The 8-bit LVS[7:0] register reports line voltage.

„ When on-hook, detect if a line is connected. „ When on-hook, detect if a parallel phone is off-hook. „ Detect if enough loop current is available to operate. unpredictable values at line voltages between 0 to 2 V. At 0 V, the LVS register displays all 0s. value of loop current is unpredictable. be enabled by setting the OHE bit (Register 5, bit 1). impedance has an ac and dc component. Figure 19. Typical Loop Current LCS Transfer Function Table 16. Loop Current Transfer Function

00000 Insufficient line current for normal

bit 1) to determine if a line is connected. 00100 Minimum line current for normal operation. overcurrent situation may exist.

Figure 21. TBR21 Mode I/V Characteristics, the signal level in low-voltage countries. mode may be used to satisfy both requirements. Table 17. AC Termination Settings for the Si3010 FCC part 68, JATE, and other countries. Table 18. AC Termination Settings for the

1111 Global complex impedance

Rev. 1.05 29 There are two selections that are useful for satisfying non-standard ac termination requirements. The 350 Ω + (1000 Ω || 210 nF) impedance selection is the ANSI/ EIA/TIA 464 compromise impedance network for trunks. The last ac termination se lection, ACIM[3:0] = 1111, is designed to satisfy minimum return loss requirements for every country in the world that requires a complex termination. For any of the ac termination settings, the programmable hybrid can be used to further reduce near-end echo. See “5.13.Transhybrid Balance” for more details. 5.13. Transhybrid Balance The Si3056 contains an on-c hip analog hybrid that performs the 2- to 4-wire conversion and near-end echo cancellation. This hybrid circuit is adjusted for each ac termination setting selected. The Si3056 also offers a digital filter stage for additional near-end echo cancellation. For each ac termination setting selected, the eight programmable hybrid registers (Registers 45-52) can be programmed with coefficients to provide increased cancellation of real- world line anomalies. This digital filter can produce 10 dB or greater of near-end echo cancellation in addition to the echo cancellation provided by the analog hybrid circuitry. 5.14. Ring Detection The ring signal is resistively coupled from TIP and RING to the RNG1 and RNG2 pins. The Si3056 supports either full- or half-wave ring detection. With full-wave ring detection, the designer can detect a polarity reversal of the ring signal. See “5.21.Caller ID” on page 32. The ring detection threshold is programmable with the RT bit (Register 16, bit 0). The ring detector output can be monitored in three ways. The first method uses the RGDT pin. The second method uses the register bits, RDTP , RDTN, and RDT (Register 5). The final method uses the DTX output. The ring detector mode is controlled by the RFWE bit (Register 18, bit 1). When the RFWE bit is 0 (default mode), the ring detector oper ates in half-wave rectifier mode. In this mode, only positive ring signals are detected. A positive ring signal is defined as a voltage greater than the ring threshold across RNG1-RNG2. Conversely, a negative ring signal is defined as a voltage less than the negative ring threshold across RNG1-RNG2. When the RFWE bit is 1, the ring detector operates in full-wave rectifier mode. In this mode, both positive and negative ring signals are detected. The first method to monitor ring detection output uses the RGDT pin. When the RGDT pin is used, it defaults to active low, but can be changed to active high by setting the RPOL bit (Register 14, bit 1). This pin is a standard CMOS output. If multiple RGDT pins are connected to a single input, the combined pullup or pulldown resistance should equal 4.7 k When the RFWE bit is 0, the RGDT pin is asserted when the ring signal is positive, which results in an output signal frequency equal to the actual ring frequency. When the RFWE bit is 1, the RGDT pin is asserted when the ring signal is positive or negative. The output then appears to be twice the frequency of the ring waveform. The second method to monitor ring detection uses the ring detect bits (RDTP, RDTN, and RDT). The RDTP and RDTN behavior is based on the RNG1-RNG2 voltage. When the signal on RNG1-RNG2 is above the positive ring threshold, the RDTP bit is set. When the signal on RNG1-RNG2 is below the negative ring threshold, the RDTN bit is set. When the signal on RNG1-RNG2 is between these thresholds, neither bit is set. The RDT behavior is also based on the RNG1-RNG2 voltage. When the RFWE bit is 0, a positive ring signal sets the RDT bit for a period of time. When the RFWE bit is 1, a positive or ne gative ring signal sets the RDT bit. The RDT bit acts like a one shot. When a new ring signal is detected, the one shot is reset. If no new ring signals are detected prior to the one shot counter reaching 0, then the RDT bit clears. The length of this count is approximately 5 seconds. The RDT bit is reset to 0 by an off-hook event. If the RDTM bit (Register 3, bit 7) is set, a hardware interrupt occurs on the AOUT/INT pin when RDT is triggered. This interrupt can be cleared by writing to the RDTI bit (Register 4, bit 7). When the RDI bit (Register 2, bit 2) is set, an interrupt occurs on both the beginning and end of the ring pulse. Ring validation may be enabled when using the RDI bit. The third method to monitor detection uses the DTX data samples to transmit ring data. If the communications link is active (PDL = 0) and the device is not off-hook or in on-hook line monitor mode, the ring data is presented on DTX. The waveform on DTX depends on the state of the RFWE bit. When RFWE is 0, DTX is –32768 (0x8000) while the RNG1-RNG2 voltage is between the thresholds. When a ring is detected, DTX transitions to +32767 when the ring signal is positive, then goes back to –32768 when the ring is near 0 and negative. Thus a near square wave is presented on DTX that swings from –32768 to +32767 in cadence with the ring signal. When RFWE is 1, DTX sits at approximately +1228

30 Rev. 1.05 while the RNG1-RNG2 voltage is between the thresholds. When the ring becomes positive, DTX transitions to +32767. When the ring signal goes near 0, DTX remains near 1228. As the ring becomes negative, the DTX transitions to –32768. This repeats in cadence with the ring signal. To observe the ring signal on DTX, watch the MSB of the data. The MSB toggles at the same frequency as the ring signal independent of the ring detector mode. This method is adequate for determining the ring frequency. 5.15. Ring Validation This feature prevents false triggering of a ring detection by validating the ring frequency. Invalid signals, such as a line voltage change when a parallel handset goes off- hook, pulse dialing, or a high-voltage line test are ignored. Ring validation can be enabled during normal operation and in low power sleep mode. The external MCLK signal is required in low power sleep mode for ring validation. The ring validation circuit operates by calculating the time between alternating crossings of positive and negative ring thresholds to validate that the ring frequency is within tolerance. High and low frequency tolerances are programmable in the RAS[5:0] and RMX[5:0] fields. The RCC[2:0] bits define how long the ring signal must be within tolerance. Once the duration of the ring frequency is validated by the RCC bits, the circuitry stops checking for frequency tolerance and begins checking for the end of the ring signal, which is defined by a lack of additional threshold crossings for a period of time configured by the RTO[3:0] bits. When the ring frequency is first validated, a timer defined by the RDLY[2:0] bits is started. If the RDLY[2:0] timer expires before the ring timeout, then the ring is validated and a valid ring is indicated. If the ring timeout expires before the RDLY[2:0] timer, a valid ring is not indicated. Ring validation requires five parameters: „ Timeout parameter to place a lower limit on the frequency of the ring signal on the RAS[5:0] bits (Register 24). This is measured by calculating the time between crossings of positive and negative ring thresholds. „ Minimum count to place an upper limit on the frequency on the RMX[5:0] bits (Register 22). „ Time interval over which the ring signal must be the correct frequency on the RCC[2:0] bits (Register 23). „ Timeout period that defines when the ring pulse has ended based on the most recent ring threshold crossing. „ Delay period between when the ring signal is validated and when a valid ring signal is indicated to accommodate distinctive ringing. The RNGV bit (Register 24, bit 7) enables or disables the ring validation feature in normal operating mode and low-power sleep mode. Ring validation affects the behavior of the RDT status bit, the RDTI interrupt, the INT pin, and the RGDT pin. 1. When ring validation is enabled, the status bit seen in the RDT read-only bit (r5.2), represents the detected envelope of the ring. The ring validation parameters are configurable so that this envelope may remain high throughout a distinctive-ring sequence. 2. The RDTI interrupt fires when a validated ring occurs. If RDI is zero (default), the interrupt occurs on the rising edge of RDT. If RDI is set, the interrupt occurs on both rising and falling edges of RDT. 3. The INT pin follows the RDTI bit with configurable polarity. The RGDT pin can be configured to follow the ringing signal envelope detected by the ring validation circuit by setting RFWE to 0. If RFWE is set to 1, the RGDT pin follows an unqualified ring detect one-shot signal initiated by a ring-threshold crossing and terminated by a fixed counter timeout of approximately 5 seconds. (This information is shown in Register 18). 5.16. Ringer Impedance and Threshold The ring detector in many DAAs is ac coupled to the line with a large 1 µF, 250 V decoupling capacitor. The ring detector on the Si3056 is resistively coupled to the line. This produces a high ringer impedance to the line of approximately 20 M Ω to meet the majority of country PTT specifications, including FCC and TBR21. Several countries including Poland, and South Africa, may require a maximum ringer impedance that can be met with an internally synthesized impedance by setting the RZ bit (Register 16, bit 1). Some countries also specify ringer thresholds differently. The RT bit (Register 16, bit 0) selects between two different ringer thresholds: 15 V ±10% and 21.5 V ±10%. These two settings satisfy ringer threshold requirements worldwide. The thresholds are set so that a ring signal is guaranteed to not be detected below the minimum, and a ring signal is guaranteed to be detected above the maximum.

Rev. 1.05 31 5.17. Pulse Dialing and Spark Quenching Pulse dialing results from going off- and on-hook to generate make and break pulses. The nominal rate is 10 pulses per second. Some countries have strict specifications for pulse fidelity that include make and break times, make resistance, and rise and fall times. In a traditional solid-state dc holding circuit, there are many problems in meeting these requirements. The Si3056 dc holding circuit actively controls the on- hook and off-hook transients to maintain pulse dialing fidelity. Spark quenching requirements in countries such as Italy, the Netherlands, South Africa, and Australia deal with the on-hook transition during pulse dialing. These tests provide an inductive dc feed resulting in a large voltage spike. This spike is caused by the line inductance and the sudden decrease in current through the loop when going on-hook. The traditional solution to the problem is to put a para llel resistive capacitor (RC) shunt across the hookswitch relay. However, the capacitor required is large (~1 µF, 250 V) and relatively expensive. In the Si3056, loop current can be controlled to achieve three distinct on-hook speeds to pass spark quenching tests without additional BOM components. Through settings of four bits in three registers, OHS (Register 16), OHS2 (Reg ister 31), SQ1 and SQ0 (Register 59), a slow ramp down of loop current can be achieved which induces a delay between the time OH bit is cleared and the time the DAA actually goes on- hook. To ensure proper operation of the DAA during pulse dialing, disable the automatic resistor calibration that is performed each time the DAA enters the off-hook state by setting the RCALD bit (Register 25, bit 5). 5.18. Billing Tone Protection and Receive Overload “Billing tones” or “metering pulses” generated by the Central Office can cause modem connection difficulties. The billing tone is typically either a 12 or 16 kHz signal and is sometimes used in Germany, Switzerland, and South Africa. Depending on line conditions, the billing tone might be large enough to cause major errors in the line data. The Si3056 chipset can provide feedback indicating the beginning and end of a billing tone. Billing tone detection is enabled with the BTE bit (Register 17, bit 2). Billing tones less than 1.1 V PK on the line are filtered out by the low pass digital filter on the Si3056. The ROV bit is set when a line signal is greater than 1.1 V PK, indicating a receive overload condition. The BTD bit is set when a billing tone is large enough to excessively reduce the line-derived power supply of the line-side device. The OVL bit (Register 19) can be polled following a billing tone detection. The OVL bit indicates that the billing tone has passed when it returns to 0. The BTD and ROV bits are sticky, and must be written to 0 to be reset. After the billing tone passes, the DAA initiates an auto-calibration sequence that must complete before data can be transmitted or received. Certain line events, such as an off-hook event on a parallel phone or a polarity reversal, can trigger the ROV or the BTD bits. Look for multiple events before qualifying if billing tones are present. After the billing tone passes, the DAA initia tes an auto-calibration sequence that must complete before data can be transmitted or received. Although the DAA remains off-hook during a billing tone event, the received data from the line is corrupted when a large billing tone occurs. If the user wishes to receive data through a billing tone, an external LC filter must be added. A manufacturer can provide this filter to users in the form of a dongle that connects on the phone line before the DAA. This pr events the manufacturer from having to include a costly LC filter to support multiple countries and customers. Alternatively, when a billing tone is detected, the system software notifies the user that a billing tone has occurred. Notification prompt s the user to contact the telephone company to disa ble billing tones or to purchase an external LC filter. Disturbance on the line other than billing tones can also cause a receive overload. Some conditions may result in a loop current collapse to a level below the minimum required operating current of the DAA. When this occurs, the dropout detect bit (DOD) is set, and an interrupt will be generated if the dropout detect interrupt mask bit (DODM) is set. 5.19. Billing Tone Filter (Optional) To operate withou t degradation duri ng billing tones in Germany, Switzerland, and South Africa, requires an external LC notch filter. The Si3056 can remain off-hook during a billing tone event, bu t line data is lost in the presence of large billing tone signals. The notch filter design requires two notches, one at 12 kHz and one at 16 kHz. Because these components are expensive and few countries utilize billing tone s, this filter is typically placed in an external dongle or added as a population option for these countries. Figure 22 shows an example billing tone filter.

Figure 22. Billing Tone Filter 25 dB of attenuation at both 12 kHz and 16 kHz. with and without the billing tone filter by at least 3 dB. to a caller ID decoder connected to the serial port.

1. After identifying a ring signal using one of the

29, determine when the first ring is complete.

1. Assert the ONHM bit (Register 5, bit 3) to enable
2. Clear the ONHM bit after the caller ID data is
3. Enable full wave rectifie d ring detection (RFWE,
4. Monitor the RDTP and RDTN register bits (or the
5. Assert the ONHM bit (Register 5, bit 3) to enable the
6. Clear the ONHM bit after the caller ID data is
7. The Caller Alert Signal (CAS) tone is sent from the

Table 19. Component Values—Optional Billing

Rev. 1.05 33 line data. The host processor must detect the presence of this tone. 2. The DAA must then check for another parallel device on the same line. This is accomplished by briefly going on-hook, measuring the line voltage, and then returning to an off-hook state. a. Set the CALD bit (Register 17, bit 5) to disable the calibration that automatically occurs when going off-hook. b. Set the RCALD bit (Register 25, bit 5) to disable the resistor calibration from occurring when going off-hook. c. Set the FOH[1:0] bits (Register 31, bits 6:5) to 11 to reduce the off-hook counter time to 8 ms. d. Clear the OH bit (or drive the OFHK pin to the inactive state) to put the DAA in an on-hook state. The RXM bit (Register 19, bit 3) may also be set to mute the receive path. e. Read the LVS bits to determine the state of the line. If the LVS bits read the typical on-hook line voltage, then no parallel devices are active on the line and CID data reception can be continued. If the LVS bits read well below the typical on- hook line voltage, then one or more devices are present and active on the same line that are not compliant with Type II CID. Do not continue CID data reception. f. Set the OH bit to 1 (or drive the OFHK pin to the active state) to return to an off-hook state. After returning to an off-hook state and waiting 8 ms for the off-hook counter, normal data transmission and reception can proceed. If a non-compliant parallel device is present, then a reply tone is not sent by the host tone generator and the CO does not proceed with sending the CID data. If all devices on the line are Type II CID compliant, then the host must mute its upstream data output to avoid propagation of its reply tone and the subsequent CID data. After muting its upstream data output, the host processor should then return an acknowledgement (ACK) tone to the CO to request the transmission of the CID data. 3. The CO then responds with the CID data and the host processor unmutes the upstream data output and continues with normal operation. 4. The muting of the upstream data path by the host processor mutes the handset in a telephone application so the user cannot hear the acknowledgement tone and CID data being sent. 5. The CALD and RCALD bits can be cleared to re- enable the automatic calibration when going off- hook. The FOH[1:0] bits also can be programmed to 01 to restore the default off-hook counter time. Because of the nature of the low-power ADC, the data presented on SDO could have up to a 10% dc offset. The caller ID decoder must either use a high pass or a band pass filter to accurately retrieve the caller ID data.

Figure 23. Implementing Type II Caller ID on the Si3056

1. The off-hook counter and calibrations prevent transmission or reception of data for 402.75 ms (default) for the line
2. The caller alert signal (CAS) tone transmits from the CO to signal an incoming call.
3. The device is taken on-hook to read the line voltage in the LVS bits to detect parallel handsets. In this mode, no data

is transmitted on the SDO pin.

1. When the device returns off-hook, the normal off-hook counter is reduced to 8 ms. If the CALD and RCALD bits are

set, then the automatic calibrations are not performed.

1. After allowing the off-hook counter to expire (8 ms), normal transmission and reception can continue. If CID data

reception is required, send the appropriate signal to the CO at this time.

1. This example uses the OH bit to put the Si3056 into an off-hook state. The OFHK pin can also be used to accomplish

low during the preceding sequence. This has the same effect as setting the OH bit.

when set. The FILT bit affects the receive path only. the desired standard modem sample rates. frequencies. Figure 26 illust rates the clock generator. constant frequency and no dropped pulses. „ Register 8: PLL1 N[7:0] divider. „ Register 9: PLL1 M[7:0] divider. one less than the value calculated from the equations. Table 20. MCLK Examples

for the required initial sample rate, typically 7200 Hz. Figure 26. Update Rate of PLL1

32.768 MHz

Table 21. Serial Modes

38 Rev. 1.05 provides software control of the secondary frames. As an alternative method, th e FC pin can serve as a hardware flag for requesting a secondary frame. The external DSP can turn on the 16-bit TX mode by setting the SB bit (Register 1, bit 0). In the 16-bit TX mode, the hardware FC pin must be used to request secondary transfers. Figures 29 and 30 illustrate the secondary frame read cycle and write cycle, respectively. During a read cycle, the R/W bit is high and the 7-bit address field contains the address of the register to be read. The contents of the 8-bit control register ar e placed on the SDO signal. During a write cycle, the R/W bit is low and the 7-bit address field contains the address of the register to be written. The 8-bit data to be written immediately follows the address on SDI. Only one register can be read or written during each secondary frame. See "6.Control Registers" on page 48 for the register addresses and functions. In serial mode 2, the Si3056 operates as a slave device, where MCLK is an input, SCLK is a no connect, and FSYNC is an input. In addition, the RGDT /FSD/M1 pin operates as a delayed frame sync (FSD) and the FC/ RGDT pin operates as ring detect (RGDT ). In this mode, FC operation is not supported. For details on operating the Si3056 as a slave device, see “5.27.Multiple Device Support” . 5.27. Multiple Device Support The Si3056 supports the operation of up to seven additional devices on a single serial interface. Figure 35 shows the typical connection of the Si3056 and one additional serial voice codec (Si3000). The Si3056 must be the master in this configuration. Configure the secondary codec as a slave device with the master’s SCLK used as the MCLK input to the codec, and the master’s frame sync delay signal (FSD) used as the codec’s FSYNC input. On powerup, the Si3056 master does not detect the additional codec on the serial bus. The FC/RGDT pin is an input, operating as the hardware control for secondary frames, and the RGDT/FSD/M1 pin is an output, operating as the active low ring detection signal. Program the master device for master/slave mode before enabling the isolation link, because a ring signal causes a false transition to the slave device’s FSYNC. Register 14 provides the necessary control bits to configure the Si3056 for master/slave operation. Bit 0 (DCE) sets the Si3056 in master/slave mode, also referred to as daisy-chain mode. When the DCE bit is set, the FC/RGDT pin becomes the ring detect output and the RGDT /FSD/M1 pin becomes the frame sync delay output. When using multiple devices, secondary frame communication must be requested via software in the LSB of the transmit (TX) data word. Bits 7:5 (NSLV2:NSLV0) set the number of slaves to be supported on the serial bus. For each slave, the Si3056 generates an FSYNC to the DSP . In daisy-chain mode, the polarity of the ring signal can be controlled by bit 1 (RPOL). When RPOL = 1, the ring detect signal (now an output on the FC/RGDT pin) is active high. The Si3056 supports a variety of codecs and additional Si3056s. The type of slave codec(s) used is set by the SSEL[1:0] bits (Register 14, bits 4:3) a nd determines the type of signalling used in the LSB of SDO. This assists the host in isolating which data stream is the master and which is the slave. If the LSB is used for signalling, the master devi ce has a unique setting relative to the slave devices. The DSP can use this information to dete rmine which FSYNC marks the beginning of a sequence of data transfers. The delayed frame sync (FSD) of each device is supplied as the FSYNC of each subsequent slave device in the daisy chain. The master Si3056 generates an FSYNC signal for each device every 16 or 32 SLCK periods. The delay period is set by FSD (Register 14, bit 2). Figure 31 on page 43 and Figure 34 on page 46 show the relative timing for daisy chaining operation. Primary communication frames occur in sequence, followed by secondary communication frames, if requested. When writing/re ading the master device via a secondary frame, all secondary frames of the slave devices also must be writte n. When writing/reading a slave device via a second ary frame, the secondary frames of the master and all other slaves must be written also. “No operation” writes/reads to secondary frames are accomplished by writing/reading a 0 value to address 0. If FSD is set for 16 SCLK periods between FSYNC only serial mode 1 can be used. In addition, the slave devices must delay the tri-state to active transition of their SDO sufficiently from the rising edge of SCLK to avoid bus contention. The Si3056 supports the operation of up to eight Si3056 devices on a single serial bus. The master Si3056 must be configured in serial mode 1. Configure the slave(s) Si3056 in serial mode 2. Figure 36 on page 47 shows a typical master/slave connection using three Si3056 devices. When in serial mode 2, FSYNC becomes an input, RGDT/FSD/M1 becomes the delay frame sync output, and FC/RGDT becomes the ring detection output. The serial interface runs at the MCLK input frequency fed from a master device (such as a master Si3056's SCLK output). To achieve the proper sampling frequency, the

Rev. 1.05 39 SRC[3:0] bits (Register 7, bits 3:0) must be programmed with the proper sample rate value before the sampled line data is valid. The SCLK pin of the slave is a no connect in this configuration. The delay between FSYNC input and delayed frame sync output (RGDT /FSD/M1) is 16 SCLK periods. The RGDT/FSD/M1 output has a wave form identical to the FSYNC signal in serial mode 0. In addition, the LSB of SDO is set to 0 by default for all devices in serial mode 2. 5.28. Power Management The Si3056 supports four basic power management operation modes. The modes are normal operation, reset operation, sleep mode, and full powerdown mode. PDN and PDL bits (Register 6) control the power management modes. On powerup, or following a reset, the Si3056 is in reset operation. The PDL bit is set, and the PDN bit is cleared. The Si3056 is oper ational, except for the isolation link. No communication between the Si3056 and line-side device can occur during reset operation. Bits associated with the line-side device are not valid in this mode. In typical applications, the DAA will predominantly be operated in normal mode. In this mode, the PDL and PDN bits are cleared. The Si3056 is operational and the isolation link is passing information between the Si3056 and the line-side device. The Si3056 supports a low-power sleep mode to support ring validation and wake-on-ring features. The clock generator registers 7, 8, and 9 must be programmed with valid, non-zero values and the PDL bit must be clear before enabling sleep mode. The PDN bit must then be set. When the Si3056 is in sleep mode the MCLK signal must remain active. In low-power sleep mode with MCLK ac tive, the Si3056 is non- functional except for the isolation link and the RGDT signal. To take the Si3056 out of sleep mode, pulse the reset pin (RESET ) low. In summary, the powerdown/up sequence for sleep mode is as follows: 1. Ensure that Registers 7, 8, and 9 have valid non- zero values, and ensure the PDL bit (Register 6, bit 4) is cleared. 2. Set the PDN bit (Register 6, bit 3). 3. The device is now in sleep mode. MCLK must stay active. 4. To exit sleep mode, reset the Si3056 by pulsing the RESET pin. 5. Program registers to desired settings. The Si3056 also supports an additional powerdown mode. When both the PDN (Register 6, bit 3) and PDL (Register 6, bit 4) bits are set, the chipset enters a complete powerdown mode and draws negligible current (deep sleep mode). Turn off the PLL2 before entering deep sleep mode (i.e., set Register 9 to 0 and then Register 6 to 0x18). In this mode, the Si3056 is non-functional. Normal operation is restored by the same process for taking the DAA out of sleep mode. 5.29. Calibration The Si3056 initiates two auto-calibrations by default when the device goes off-hook or experiences a loss in line power. A 17 ms resistor calibration is performed to allow circuitry internal to the DAA to adjust to the exact line conditions present at that time. This resistor calibration can be disabled by setting the RCALD bit (Register 25, bit 5). A 256 ms ADC calibration is also performed to remove offsets that might be present in the on-chip A/D converter which could affect the A/D dynamic range. The ADC auto-calibration is initiated after the DAA dc terminatio n stabilizes, and the resistor calibration completes . Because large variations in line conditions and line card behavior exist, it could be beneficial to use manual calibration instead of auto- calibration. Execute manual ADC calibration as close as possible to 256 ms before valid transmit/receive data is expected. Take the following steps to implement manual ADC calibration: 1. The CALD (auto-calibration disable—Register 17) bit must be set to 1. 2. The MCAL (manual calibration) bit must be toggled to 1 and then 0 to begin and complete the calibration. 3. The calibration is completed in 256 ms. 5.30. In-Circuit Testing With the Si3056’s advanced design the designer can determine system functionalit y during production line tests, and during support for end-user diagnostics. Four loopback modes allow thorough coverage of system components. Four of the te st modes require a line-side power source. Although a standard phone line can be used, the test circuit in Figure 1 on page 6 is adequate. In addition, an off-hook sequence must be performed to connect the power source to the line-side device. For the start-up loopback test mode, line-side power is not necessary and no off-hook sequence is required. The start-up test mode is enabled by default. When the PDL bit (Register 6, bit 4) is set (the default case), the line-side is in a powerdown mode and the DSP-side is in a digital loop-back mode. Data received on SDI

40 Rev. 1.05 passes through the internal filters and transmitted on SDO which introduces approximately 0.9 dB of attenuation on the SDI signal received. The group delay of both transmit and receive filters exists between SDI and SDO. Clearing the PDL bit disables this mode and the SDO data is switched to the receive data from the line-side. When the PDL bit is cleared, the FDT bit (Register 12, bit 6) becomes active, indicating the successful communication between the line-side and DSP-side. This can be used to verify that the isolation link is operational. The digital data loop-back mode offers a way to input data on the SDI pin and have the identical data be output on the SDO pin by bypassing the transmit and receive filters. Setting the DDL bit (Register 10, bit 0) enables this mode. No line-side power or off-hook sequence is required for this mode. The digital data loopback mode is useful to verify communication between the host processor/DSP and the DAA. The remaining test modes require an off-hook sequence to operate. The following sequence describes the off- hook procedure required for the following test modes: 1. Powerup or reset. 2. Program the clock generator to the chosen sample rate. 3. Enable line-side by clearing the PDL bit. 4. Issue an off-hook command. 5. Delay 402.75 ms to allow calibration to occur. 6. Set the desired test mode. In the communications link loopback mode, the host sends a digital input test pattern on SDI and receives that digital test pattern back on SDO. To enable this mode, set the IDL bit (Register 1, bit 1). In this mode, the communication link is tested. The digital stream is delivered across the isolation capacitors, C1 and C2 of Figure 16 on page 17, to the line-side device and returned across the same interface. In this mode, the 0.9 dB attenuation and filter group delays also exist. The final testing mode, internal analog loopback, allows the system to test the operation of the transmit and receive paths through the line-side device and the external components shown in Figure 16 on page 17. In this test mode, the host provides a digital test waveform on SDI. This data passes across the communications link, is transmitted to and received from the line, passes back across the communications link, and is presented to the host on SDO. To enable this mode, clear the HBE bit (Register 2, bit 1). When the HBE bit is cleared, this causes a dc offset that affects the signal swing of the transmit signal. Silicon Laboratories ® recommends that the transmit signal be 12 dB lower than normal tran smit levels. A lower level eliminates clipping from the dc offset that results from disabling the hybrid. It is assumed in this test that the line ac impedance is nominally 600 Note: All test modes are mutually exclusive. If more than one test mode is enabled concurrently, the results are unpredictable. 5.31. Exception Handling The Si3056 provides several mechanisms to determine if an error occurs during operation. Through the secondary frames of the se rial link, the controlling systems can read several status bits. The bit of highest importance is the frame detect bit (FDT, Register 12, bit 6), which indicates that the system-side (Si3056) and line-side devices are communicating. During normal operation, the FDT bit can be checked before reading bits for information about the line-side. If FDT is not set, the following bits related to the line-side are invalid—RDT, RDTN, RDTP , LCS[4:0], LSID[1:0], REVB[3:0], LCS2[7:0], LVS[7:0], ROV, BTD, DOD, and OVL; the RGDT operation is also non-functional. Following Powerup and reset, the FDT bit is not set because the PDL bit (Register 6 bit 4) defaults to 1. The communications link does not operate and no information about the line-side can be determined. The user must program the clock generator to a valid configuration for the system and clear the PDL bit to activate the communications link. As the system- and line-side devices are establishing communication, the system-side device does not generate FSYNC signals. Establishing communication takes less than 10 ms. Therefore, if the controlli ng DSP serial interface is interrupt driven based on the FSYNC signal, the controlling DSP does not require a special delay loop to wait for this event to complete. The FDT bit also can indicate if the line-side device executes an off-hook request successfully. If the line- side device is not connected to a phone line, the FDT bit remains cleared. The controlling DSP must provide sufficient time for the line-side to execute the off-hook request. The maximum time for FDT to be valid following an off-hook request is 10 ms. If the FDT bit is high, the LCS[4:0] bits i ndicate the amount of loop current flowing. If the FDT fails to be set following an off- hook request, the PDL bit (Register 6) must be set high for at least 1 ms to reset the line-side.

revisions not yet in existence. Figure 27. Software FC/RGDT Secondary Request Table 22. Revision Values

16 SCLKS

128 SCLKS

256 SCLKS

Figure 28. Hardware FC/RGDT Secondary Request Figure 29. Secondary Communication Data Format—Read Cycle

1 A A A A A A A

Figure 30. Secondary Communication Data Format—Write Cycle Figure 31. Daisy Chaining of a Single Slave (Pulse FSD)

0 A A A A A A A

128 SCLKs 128 SCLKs

32 SCLKs 32 SCLKs

Figure 32. Daisy Chaining of a Single Slave (Frame FSD)

16 SCLKs 16 SCLKs 16 SCLKs

Figure 33. Daisy Chaining of Eight DAAs

Figure 34. Daisy Chaining with Framed FSYNC and Framed FSD Figure 35. Typical Connection for Master/Slave Operation (e.g., Data/Fax/Voice Modem)

Figure 36. Typical Connection for Multiple DAAS

Table 23. Register Summary

1 Control 1 SR PWMM[1:0] PWME IDL SB

2 Control 2 INTE INTP WDTEN RDI HBE RXE

3 Interrupt Mask RDTM ROVM FDTM BTDM DODM LCSOM DLCSM POLM

4 Interrupt Source RDTI ROVI FDTI BTDI DODI LCSOI DLCSI POLI

5 DAA Control 1 RDTN RDTP OPOL ONHM RDT OHE OH

6 DAA Control 2 PDL PDN

7 Sample Rate Control SRC[3:0]

8 PLL Divide N N[7:0]

9 PLL Divide M M[7:0]

10 DAA Control 3 DDL

11 System-Side and Line-Side Revision LSID[3:0] REVA[3:0]

12 Line-Side Device Status FDT LCS[4:0]

13 Line-Side Device Revision 0 REVB[3:0]

14 Serial Interface Control NSLV[2:0] SSEL[1:0] FSD RPOL DCE

15 TX/RX Gain Control 1 TXM ATX[2:0] RXM ARX[2:0]

16 International Control 1 ACT2

2 OHS ACT 2 IIRE RZ RT

17 International Control 2 CALZ MCAL CALD OPE BTE ROV BTD

18 International Control 3 RFWE

19 International Control 4 OVL DOD OPD

20 Call Progress Rx Attenuation ARM[7:0]

21 Call Progress Tx Attenuation ATM[7:0]

22 Ring Validation Control 1 RDLY[1:0] RMX[5:0]

23 Ring Validation Control 2 RDLY[2] RTO[3:0] RCC[2:0]

24 Ring Validation Control 3 RNGV RAS[5:0]

25 Resistor Calibration RCALS RCALM RCALD RCAL[3:0]

26 DC Termination Control DCV[1:0] MINI[1:0] ILIM DCR

27 Reserved

28 Loop Current Status LCS2[7:0]

29 Line Voltage Status LVS[7:0]

30 AC Termination Control FULL2

1 ACIM[3:0]1

31 DAA Control 4 FULL 1 FOH[1:0] OHS2 FILT 1 LVFD1

38 TX Gain Control 2 TGA2 1 TXG2[3:0]1

39 RX Gain Control 2 RGA2 1 RXG2[3:0]1

40 TX Gain Control 3 TGA3 1 TXG3[3:0]1

41 RX Gain Control 3 RGA3 1 RXG3[3:0]1

42 Reserved

43 Line Current/Voltage Threshold

44 Line Current/Voltage Threshold

59 Spark Quenching Control TB3 SQ1 SQ0 RG1 GCE

1. Bit is available for Si3019 line-side device only.
2. Bit is available for Si3010 and Si3018 line-side device only.

Rev. 1.05 49 Reset settings = 0000_0000 Register 1. Control 1 B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name SR PWMM[1:0] PWME IDL SB Type R/W R/W R/W R/W R/W Bit Name Function 7S R Software Reset. 0 = Enables the DAA for normal operation. 1 = Sets all registers to their reset value. Note: Bit automatically clears after being set. 6 Reserved Read returns zero. 5:4 PWMM[1:0] Pulse Width Modulation Mode. Used to select the type of signal output on the call progress AOUT pin. 00 = PWM output is clocked at 16.384 MHz as a delta-sigma data stream. A local density of 1s and 0s tracks the combined transmit and receive signals. 01 = Balanced conventional PWM output signal has high and low portions of the modulated pulse that are centered on the 16 kHz sample clock. 10 = Conventional PWM output signal returns to logic 0 at regular 32 kHz intervals and rises at a time in the 32 kHz period proportional to its instantaneous amplitude. 11 = Reserved. 3P W M E Pulse Width Modulation Enable. Sums the transmit and receive audio paths and presents it as a CMOS digital-level output of PWM data. Use the circuit in “Figure 18. AOUT PWM Circuit for Call Progress” . 0 = Pulse width modulation signal for AOUT disabled. 1 = Pulse width modulation signal for call progress analog output (AOUT) enabled. 2 Reserved Read returns zero. 1I D L Isolation Digital Loopback. 0 = Digital loopback across the isolation barrier is disabled. 1 = Enables digital loopback mode across the isolation barrier. The line-side device must be enabled and off hook before setting this mode. This data path includes the TX and RX filters. 0S B Serial Digital Interface Mode. 0 = Operation is in 15-bit mode, and the LSB of the data field indicates that a secondary frame is required. 1 = The serial port is operating in 16-bit mode and requires a secondary frame sync signal, FC, to initiate control data reads/writes.

50 Rev. 1.05 Reset settings = 0000_0011 Register 2. Control 2 B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name INTE INTP WDTEN RDI HBE RXE Type R/W R/W R/W R/W R/W R/W Bit Name Function 7I N T E Interrupt Pin Enable. 0=T h e A O U T / I N T pin functions as an analog output for call progress monitoring purposes. 1=T h e A O U T / I N T pin functions as a hardware interrupt pin. 6I N T P Interrupt Polarity Select. 0=T h e A O U T / I N T pin, when used in hardware interrupt mode, is active low. 1=T h e A O U T / I N T pin, when used in hardware interrupt mode, is active high. 5 Reserved Returns to zero. 4W D T E N Watchdog Timer Enable. When set, this bit can only be cleared by a hardware reset. The watchdog timer monitors register accesses. If no register accesses occur within a 4 second window, the DAA is put into an on-hook state. A write of a DAA register restarts the watchdog timer counter. If the watchdog timer times out, the OH and OHE bits are cleared, placing the DAA into an on-hook state. Setting the OH bit or setting the OHE bit and asserting the OFHK pin places the DAA back into an off-hook state. 0 = Watchdog timer disabled. 1 = Watchdog timer enabled. 3 Reserved Returns to zero. 2R D I Ring Detect Interrupt Mode. This bit operates in conjunction with the RDTM and RDTI bits. This bit is selected if one or two interrupts are generated for every ring burst. 0 = An interrupt is generated at the beginning of every ring burst. 1 = An interrupt is generated at the beginning and end of every ring burst. The interrupt at the beginning of the ring burst must be serviced (by writing a 0 to the RDTI bit) before the end of the ring burst for both interrupts to occur. 1H B E Hybrid Enable. 0 = Disconnects hybrid in transmit path. 1 = Connects hybrid in transmit path. 0R X E Receive Enable. 0 = Receive path disabled. 1 = Enables receive path.

Rev. 1.05 51 Reset settings = 0000_0000 Register 3. Interrupt Mask B i t D 7D 6D 5D 4D 3 D 2 D 1 D 0 Name RDTM ROVM FDTM BTDM DODM LCSOM DLCSM POLM Type R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Function 7R D T M Ring Detect Mask. 0 = A ring signal does not cause an interrupt on the AOUT/INT pin. 1 = A ring signal causes an interrupt on the AOUT/INT pin. 6R O V M Receive Overload Mask. 0 = A receive overload does not cause an interrupt on the AOUT/INT pin. 1 = A receive overload causes an interrupt on the AOUT/INT pin. 5F D T M Frame Detect Mask. 0 = The communications link achieving frame lock does not cause an interrupt on the AOUT/ INT pin. 1 = The communications link achieving frame lock causes an interrupt on the AOUT/INT pin. 4B T D M Billing Tone Detect Mask. 0 = A detected billing tone does not cause an interrupt on the AOUT/INT pin. 1 = A detected billing tone causes an interrupt on the AOUT/INT pin. 3D O D M Drop Out Detect Mask. 0 = A line supply dropout does not cause an interrupt on the AOUT/INT pin. 1 = A line supply dropout causes an interrupt on the AOUT/INT pin. 2L C S O M Loop Current Sense Overload Mask. 0 = An interrupt does not occur when the LCS bits are all 1s. 1 = An interrupt occurs when the LCS bits are all 1s. 1D L C S M Delta Loop Current Sense Mask. 0 = An interrupt does not occur when the LCS bits change. 1 = An interrupt does occur when the LCS bits change. 0P O L M Polarity Reversal Detect Mask. Generated from bit 7 of the LVS register. When this bit transitions, it indicates that the polarity of TIP and RING was switched. 0 = A polarity change on TIP and RING does not cause an interrupt on the AOUT/INT pin. 1 = A polarity change on TIP and RING causes an interrupt on the AOUT/INT pin.

52 Rev. 1.05 Reset settings = 0000_0000 Register 4. Interrupt Source B i t D 7D 6D 5D 4D 3D 2 D 1 D 0 Name RDTI ROVI FDTI BTDI DODI LCSOI DLCSI POLI Type R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Function 7R D T I Ring Detect Interrupt. 0 = A ring signal is not occurring. 1 = A ring signal is detected. If the RDTM (Register 3) and INTE (Register 2) bits are set a hard- ware interrupt occurs on the AOUT/INT pin. This bit must be written to a 0 to be cleared. The RDI bit (Register 2) determines if this bit is set only at the beginning of a ring pulse, or at the end of a ring pulse as well. This bit should be cleared after clearing the PDL bit (Register 6) because pow- ering up the line-side device may cause this interrupt to be triggered. 6R O V I Receive Overload Interrupt. 0 = An excessive input level on the receive pin is not occurring. 1 = An excessive input level on the receive pin is detected. If the ROVM and INTE bits are set a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to clear it. This bit is identical in function to the ROV bit (Register 17). Clearing this bit also clears the ROV bit. 5F D T I Frame Detect Interrupt. 0 = Frame detect is established on the communications link. 1 = This bit is set when the communications link does not have frame lock. If the FDTM and INTE bits are set, a hardware interrupt occurs on the AOUT/INT pin. Once set, this bit must be written to a 0 to be cleared. 4B T D I Billing Tone Detect Interrupt. 0 = A billing tone has not occurred. 1 = A billing tone has been detected. If the BTDM and INTE bits are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to clear it. 3D O D I Drop Out Detect Interrupt. 0 = The line-side power supply has not collapsed. 1 = The line-side power supply has collapsed (The DOD bit in Register 19 has fired). If the DODM and INTE bits are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to be cleared. This bit should be cleared after clearing the PDL bit (Register 6) because powering as the line-side device can cause this interrupt to be triggered. 2L C S O I Loop Current Sense Overload Interrupt. 0 = The LCS bits have not reached max value (all ones). 1 = The LCS bits have reached max value. If the LCSOM bit (Register 3) and the INTE bit are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to be cleared. LCSOI does not necessarily imply that an overcurrent situation has occurred. An overcurrent sit- uation in the DAA is determined by the status of the OPD bit (Register 19). After the LCSOI inter- rupt fires, the OPD bit should be checked to determine if an overcurrent situation exists.

Rev. 1.05 53 Reset settings = 0000_0000

1 DLCSI Delta Loop Current Sense Interrupt

0 = The LCS bits have not changed value. 1 = The LCS bits have changed value; a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to a 0 to be cleared. 0 POLI Polarity Reversal Detect Interrupt. 0 = Bit 7 of the LVS register does not change states. 1 = Bit 7 of the LVS register changes from a 0 to a 1, or from a 1 to a 0, indicating the polarity of TIP and RING is switched. If the POLM and INTE bits are set, a hardware interrupt occurs on the AOUT/INT pin. To clear the interrupt, write this bit to 0. Register 5. DAA Control 1 B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name RDTN RDTP OPOL ONHM RDT OHE OH Type R R R/W R/W R R/W R/W Bit Name Function 7 Reserved Read returns zero. 6 RDTN Ring Detect Signal Negative. 0 = No negative ring signal is occurring. 1 = A negative ring signal is occurring. 5R D T P Ring Detect Signal Positive. 0 = No positive ring signal is occurring. 1 = A positive ring signal is occurring. 4O P O L Off-hook Polarity. 0 = Off-hook pin is active low. 1 = Off-hook pin is active high. 3O N H M On-Hook Line Monitor. 0 = Normal on-hook mode. 1 = Enables low-power on-hook monitoring mode allowing the host to receive line activity without going off-hook. This mode is used for caller-ID detection. 2 RDT Ring Detect. 0 = Reset either 5 seconds after last positive ring is detected or when the system executes an off-hook. Only a positive ring sets this bit when RFWE = 0. When RFWE = 1, either a positive or negative ring sets this bit. 1 = Indicates a ring is occurring. 1O H E Off-hook Pin Enable. 0 = Off-hook pin is ignored. 1 = Enables operation of the off-hook pin. 0O H Off-Hook. 0 = Line-side device on-hook. 1 = Causes the line-side device to go off-hook. This bit operates independently of the OHE bit and is a logic OR with the off-hook pin when enabled. Bit Name Function

54 Rev. 1.05 Reset settings = 0001_0000 Reset settings = 0000_0000 Register 6. DAA Control 2 B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name PDL PDN Type R/W R/W Bit Name Function 7:5 Reserved Read returns zero. 4P D L Powerdown Line-Side Device. 0 = Normal operation. Program the clock generator before clearing this bit. 1 = Places the line-side device in lower power mode. 3P D N Powerdown System-Side Device. 0 = Normal operation. 1 = Powers down the system-side device. A pulse on RESET is required to restore normal operation. 2:0 Reserved Read returns zero. Register 7. Sample Rate Control B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name SRC[3:0] Type R/W Bit Name Function 7:4 Reserved Read returns zero. 3:0 SRC[3:0] Sample Rate Control. Sets the sample rate of the line-side device. 0000 = 7200 Hz 0001 = 8000 Hz 0010 = 8229 Hz 0011 = 8400 Hz 0100 = 9000 Hz 0101 = 9600 Hz 0110 = 10286 Hz 0111 = 12000 Hz 1000 = 13714 Hz 1001 = 16000 Hz 1010–1111 = Reserved

Rev. 1.05 55 Reset settings = 0000_0000 (serial mode 0, 1) Reset settings = 0001_0011 (serial mode 2) Reset settings = 0000_0000 Reset settings = 0000_0000 Register 8. PLL Divide N B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name N[7:0] Type R/W Bit Name Function 7:0 N[7:0] PLL N Divider. Contains the (value –1) for determining the output frequency on PLL1. Register 9. PLL Divide M B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name M[7:0] Type R/W Bit Name Function 7:0 M[7:0] PLL M Divider. Contains the (value –1) for determining the output frequency on PLL1. Register 10. DAA Control 3 B i t D 7D 6D 5D 4 D 3 D 2 D 1 D 0 Name DDL Type R/W Bit Name Function 7:1 Reserved Read returns zero. 0 DDL Digital Data Loopback. 0 = Normal operation. 1 = Audio data received on SDI and loops it back out to SDO before the TX and RX filters. Outputted data is identical to inputted data.

56 Rev. 1.05 Reset settings = xxxx_xxxx Reset settings = 0000_0000 Register 11. System-Side and Line-Side Device Revision B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name LSID[3:0] REVA[3:0] Type RR Bit Name Function 7:4 LSID[3:0] Line-Side ID Bits. These four bits will always read one of the following values depending on which line-side device is used. LSID[3:0] Si3018 0001 Si3019 0011 Si3010 0101 3:0 REVA[3:0] System-Side Revision. Four-bit value indicating the revision of the system-side device. Register 12. Line-Side Device Status B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name FDT LCS[4:0] Type RR Bit Name Function 7 Reserved Read returns zero. 6F D T Frame Detect. 0 = Indicates the communications link has not established frame lock. 1 = Indicates the communications link frame lock is established. 5 Reserved Read returns zero. 4:0 LCS[4:0] Loop Current Sense. 5-bit value returning the loop current when the DAA is in an off-hook state. 00000 = Loop current is less than required for normal operation. 00100 = Minimum loop current for normal operation. 11111 = Loop current is >127 mA, and a current overload condition may exist.

Rev. 1.05 57 Reset settings = xxxx_xxxx Register 13. Line-Side Device Revision B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name 0 REVB[3:0] Type R Bit Name Function 7 Reserved Read returns zero. 6 0 This bit always reads a zero. 5:2 REVB[3:0] Line-Side Device Revision. Four-bit value indicating the revision of the line-side device. 1:0 Reserved Read returns zero.

58 Rev. 1.05 Reset settings = 0000_0000 (serial mode 0,1) Reset settings = 0011_1101 (serial mode 2) Register 14. Serial Interface Control B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name NSLV[2:0] SSEL[1:0] FSD RPOL DCE Type R/W R/W R/W R/W R/W Bit Name Function 7:5 NSLV[2:0] Number of Slaves devices. 000 = 0 slaves. Redefines the FC/RGDT and RGDT/FSD pins. 001 = 1 slave device 010 = 2 slave devices 011 = 3 slave devices 100 = 4 slave devices (For four or more slave devices, the FSD bit MUST be set.) 101 = 5 slave devices 110 = 6 slave devices 111 = 7 slave devices 4:3 SSEL[1:0] Slave device select. 00 = 16-bit SDO receive data 01 = Reserved 10 = 15-bit SDO receive data, LSB = 1 11 = 15-bit SDO receive data, LSB = 0 2F S D Delayed Frame Sync Control. 0 = Sets the number of SCLK periods between frame syncs to 32. 1 = Sets the number of SCLK periods between frame syncs to 16. This bit MUST be set when Si3056 devices are slaves. For the master Si3056, only serial mode 1 is allowed when this bit is set. 1R P O L Ring Detect Polarity. 0=T h e F C / R G D T pin (operating as ring detect) is active low. 1=T h e F C / R G D T pin (operating as ring detect) is active high. 0D C E Daisy-Chain Enable. 0 = Daisy-chaining disabled. 1 = Enables the Si3056 to operate with slave devices on the same serial bus. The FC/RGDT signal (pin 7) becomes the ring detect output and the RDGT/FSD signal (pin 15) becomes the delayed frame sync signal. ALL other bits in this register are ignored if DCE = 0.

Rev. 1.05 59 Reset settings = 0000_0000 Register 15. TX/RX Gain Control 1 B i t D 7D 6 D 5 D 4D 3D 2D 1D 0 Name TXM ATX[2:0] RXM ARX[2:0] Type R/W R/W R/W R/W Bit Name Function 7T X M Transmit Mute. 0 = Transmit signal is not muted. 1 = Mutes the transmit signal. 6:4 ATX[2:0] Analog Transmit Attenuation. 000 = 0 dB attenuation 001 = 3 dB attenuation 010 = 6 dB attenuation 011 = 9 dB attenuation 1xx = 12 dB attenuation Note: Write these bits to zero when using the finer resolution transmit and receive gain/attenuation registers 38–41 available only with the Si3019 line-side device. 3R X M Receive Mute. 0 = Receive signal is not muted. 1 = Mutes the receive signal. 2:0 ARX[2:0] Analog Receive Gain. 0 0 0=0d B g a i n 0 0 1=3d B g a i n 0 1 0=6d B g a i n 0 1 1=9d B g a i n 1xx = 12 dB gain Note: Write these bits to zero when using the finer resolution transmit and receive gain/attenuation registers 38–41 available only with the Si3019 line-side device.

60 Rev. 1.05 Reset settings = 0000_0000 Register 16. International Control 1 B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name ACT2 OHS ACT IIRE RZ RT Type RW R/W R/W R/W R/W R/W Bit Name Function 7 ACT2 AC Termination Select 2 (Si3018 line-side device only). Works with the ACT bit to select one of four ac terminations: ACT2 ACT AC Termination

00 R e a l , 6 0 0 Ω

0 1 Global complex impedance 1 0 Global complex impedance, except New Zealand 1 1 New Zealand complex impedance The global complex impedance meets minimum return loss requirements in countries that require a complex ac termination. For improved return loss performance, the other complex impedances can be used. 6O H S On-Hook Speed. This bit, in combination with the OHS2 bit (Register 31) and the SQ[1:0] bits (Register 59), sets the amount of time for the line-side device to go on-hook. The on-hook speeds specified are measured from the time the OH bit is cleared until loop current equals zero. OHS OHS2 SQ[1:0] Mean On-Hook Speed 0 0 00 Less than 0.5 ms 0 1 00 3 ms ±10% (meets ETSI standard)

1 X 11 26 ms ±10% (meets Australia spark quenching spec)

5 ACT

AC Termination Select. (Si3018 line-side device only). When the ACT2 bit is cleared, the ACT bit selects the following: 0 = Selects the real ac impedance (600 Ω) 1 = Selects the global complex impedance. 4 IIRE IIR Filter Enable. 0 = FIR filter enabled for transmit and receive filters. See Figures 7–10 on page 16. 1 = IIR filter enabled for transmit and receive filters. See Figures 11–16 on page 17. 3:2 Reserved Read returns zero. 1R Z Ringer Impedance. 0 = Maximum (high) ringer impedance. 1 = Synthesized ringer impedance enabled. See "5.16.Ringer Impedance and Threshold" on page 30. 0R T Ringer Threshold Select. This bit is used to satisfy country requirements on ring detection. Signals below the lower level do not generate a ring detection; signals above the upper level are guaranteed to generate a ring detection. RT RT Lower level RT Upper level 01 3 . 5 V rms 16.5 Vrms 1 19.35 V rms 23.65 Vrms

Rev. 1.05 61 Reset settings = 0000_0000 Register 17. International Control 2 B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name CALZ MCAL CALD OPE BTE ROV BTD Type R/W R/W R/W R/W R/W R/W R Bit Name Function 7C A L Z Clear ADC Calibration. 0 = Normal operation. 1 = Clears the existing calibration data. This bit must be written back to 0 after being set. 6M C A L Manual ADC Calibration. 0 = No calibration. 1 = Initiate manual ADC calibration. 5C A L D ADC Auto-Calibration Disable. 0 = Enable auto-calibration. 1 = Disable auto-calibration. 4 Reserved Read returns zero. 3O P E Overload Protect Enable. 0=D i s a b l e d . 1 = Enabled. The OPE bit should always be cleared before going off-hook. 2B T E Billing Tone Detect Enable. When set, the DAA can detect a billing tone signal on the line and maintain on off-hook state through the billing tone. If a billing tone is detected, the BTD bit (Register 17) is set to indicate the event. Writing this bit to zero clears the BTD bit. 0 = Billing tone detection disabled. The BDT bit is not function. 1 = Billing tone detection enabled. The BDT is functional. 1R O V Receive Overload. This bit is set when the receive input has an excessive input level (i.e., receive pin goes below ground). Writing a zero to this location clears this bit and the ROVI bit (Register 4, bit 6). 0 = Normal receive input level. 1 = Excessive receive input level. 0B T D Billing Tone Detected. This bit is set if a billing tone is detected. Writing a zero to BTE clears this bit. 0 = No billing tone detected. 1 = Billing tone detected.

62 Rev. 1.05 Reset settings = 0000_0000 Register 18. International Control 3 B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name RFWE Type R/W Bit Name Function 7:2 Reserved Read returns zero or one. 1R F W E Ring Detector Full-Wave Rectifier Enable. When RNGV (Register 24) is disabled, this bit controls the ring detector mode and the asser- tion of the RGDT pin. When RNGV is enabled, this bit configures the RGDT pin to either follow the ringing signal detected by the ring validation circuit, or to follow an unqualified ring detect one-shot signal initiated by a ring-threshold crossing and terminated by a fixed counter time- out of approximately five seconds. RNGV RFWE RGDT

00 H a l f - W a v e

1 0 Validated Ring Envelope 1 1 Ring Threshold Crossing One-Shot 0 Reserved Read returns zero or one.

Rev. 1.05 63 Reset settings = 0000_0000 Register 19. International Control 4 B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name OVL DOD OPD Type RRR Bit Name Function 7:3 Reserved Read returns zero. 2O V L Receive Overload Detect. This bit has the same function as ROV in Register 17, but clears itself after the overload is removed. See “5.18.Billing Tone Protection and Receive Overload” on page 31. This bit is only masked by the off-hook counter and is not affected by the BTE bit. 0 = Normal receive input level. 1 = Excessive receive input level. 1D O D Recal/Dropout Detect. When the line-side device is off-hook, it is powered from the line itself. This bit will read 1 when loop current is not flowing. For example, if the line-derived power supply collapses, such as when the line is disconnected, this bit is set to 1. Additionally, when on-hook and the line- side device is enabled, this bit is set to 1. 0 = Normal operation. 1 = Line supply dropout detected when off-hook. 0O P D Overload Protection Detect. This bit is used to indicate that the DAA has detected a loop current overload. The detector fir- ing threshold depends on the setting of the ILIM bit (Register 26). OPD ILIM Overcurrent Threshold Overcurrent Status 0 0 160 mA No overcurrent condition exists 0 1 60 mA No overcurrent condition exists 1 0 160 mA An overcurrent condition has been detected 1 1 60 mA An overcurrent condition has been detected

64 Rev. 1.05 Reset settings = 0000_0000 Reset settings = 0000_0000 Register 20. Call Progress Receive Attenuation Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ARM[7:0] Type R/W Bit Name Function 7:0 ARM[7:0] AOUT Receive Path Attenuation. When decremented from the default setting, these bits linearly attenuate the AOUT receive path signal used for call progress monitoring. Setting the bits to all 0s mutes the AOUT receive path. Attenuation = 20 log(ARM[7:0]/64) 1111_1111 = +12 dB (gain) 0111_1111 = +6 dB (gain) 0100_0000 = 0 dB 0010_0000 = –6 dB (attenuation) 0001_0000 = –12 dB 0000_0000 = Mute Register 21. Call Progress Transmit Attenuation B i tD 7 D 6 D 5D 4D 3 D 2 D 1D 0 Name ATM[7:0] Type R/W Bit Name Function 7:0 ATM[7:0] AOUT Transmit Path Attenuation. When decremented from the default settings, these bits linearly attenuate the AOUT trans- mit path signal used for call progress monitoring. Setting the bits to all 0s mutes the AOUT transmit path. Attenuation = 20 log(ATM[7:0]/64) 1111_1111 = +12 dB (gain) 0111_1111 = +6 dB (gain) 0100_0000 = 0 dB 0010_0000 = –6 dB (attenuation) 0001_0000 = –12 dB 0000_0000 = Mute

Rev. 1.05 65 Reset settings = 1001_0110 Register 22. Ring Validation Control 1 B i t D 7D 6D 5 D 4 D 3D 2 D 1 D 0 Name RDLY[1:0] RMX[5:0] Type R/W R/W Bit Name Function 7:6 RDLY[1:0] Ring Delay Bits 1 and 0. These bits, in combination with the RDLY[2] bit (Register 23), set the amount of time between when a ring signal is validated and when a valid ring signal is indicated. RDLY[2] RDLY[1:0] Delay 00 0 0 ms 00 1 2 5 6 ms 01 0 5 1 2 ms 1 11 1792 ms 5:0 RMX[5:0] Ring Assertion Maximum Count. These bits set the maximum ring frequency for a valid ring signal within a 10% margin of error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the timer value is compared to the RMX[5:0] field and if it exceeds the value in RMX[5:0] then the frequency of the ring is too high and the ring is invalidated. The difference between RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual- ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/ (2 x 20 Hz) = 25 ms. To calculate the correct RMX[5:0] value for a frequency range [f_min, f_max], the following equation should be used: To compensate for error margin and ensure a sufficient ring detection window, it is recom- mended that the calculated value of RMX[5:0] be incremented by 1. RMX 5:0[] RAS 5:0[] 1

66 Rev. 1.05 Reset settings = 0010_1101 Register 23. Ring Validation Control 2 B i t D 7 D 6D 5D 4D 3D 2D 1D 0 Name RDLY[2] RTO[3:0] RCC[2:0] Type R/W R/W R/W Bit Name Function 7 RDLY[2] Ring Delay Bit 2. This bit, in combination with the RDLY[1:0] bits (Register 22), set the amount of time between when a ring signal is validated and when a valid ring signal is indicated. RDLY[2] RDLY[1:0] Delay 00 0 0 ms 00 1 2 5 6 ms 01 0 5 1 2 ms 1 11 1792 ms 6:3 RTO[3:0] Ring Timeout. These bits set when a ring signal is determined to be over after the most recent ring thresh- old crossing. RTO[3:0] Ring Timeout 0000 80 ms 0001 128 ms 0010 256 ms 1111 1920 ms 2:0 RCC[2:0] Ring Confirmation Count. These bits set the amount of time that the ring frequency must be within the tolerances set by the RAS[5:0] bits and the RMX[5:0] bits to be classified as a valid ring signal. RCC[2:0] Ring Confir mation Count Time 000 100 ms 001 150 ms 010 200 ms 011 256 ms 100 384 ms 101 512 ms 110 640 ms 111 1024 ms

Rev. 1.05 67 Reset settings = 0001_1001 Register 24. Ring Validation Control 3 B i t D 7 D 6 D 5D 4D 3D 2D 1D 0 Name RNGV RAS[5:0] Type R/W R R/W Bit Name Function 7R N G V Ring Validation Enable. 0 = Ring validation feature is disabled. 1 = Ring validation feature is enabled in both normal operating mode and low-power mode. 6 Reserved Reserved and may read either a 1 or 0. 5:0 RAS[5:0] Ring Assertion Time. These bits set the minimum ring frequency for a valid ring signal within a 10% margin of error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the timer value is compared to the RMX[5:0] field and if it exceeds the value in RMX[5:0] then the frequency of the ring is too high and the ring is invalidated. The difference between RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual- ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/ (2 x 20 Hz) = 25 ms. To calculate the correct RMX[5:0] value for a frequency range [f_min, f_max], the following equation should be used: To compensate for error margin and ensure a sufficient ring detection window, it is recom- mended that the calculated value of RMX[5:0] be incremented by 1. RMX 5:0[] RAS 5:0[] 1

68 Rev. 1.05 Reset settings = xx0x_xxxx Register 25. Resistor Calibration B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name RCALS RCALM RCALD RCAL[3:0] Type R R/W R/W R R/W Bit Name Function 7R C A L S Resistor Auto Calibration. 0 = Resistor calibration is not in progress. 1 = Resistor calibration is in progress. 6R C A L M Manual Resistor Calibration. 0 = No calibration. 1 = Initiate manual resistor calibration. (After a manual calibration has been initiated, this bit must be cleared within 1 ms.) 5 RCALD Resistor Calibration Disable. 0 = Internal resistor calibration enabled. 1 = Internal resistor calibration disabled. 4 Reserved Do not write to this register bit. This bit always reads a zero. 3:0 RCAL[3:0] Always write back the value read.

Rev. 1.05 69 Reset settings = 0000_0000 Register 26. DC Termination Control B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name DCV[1:0] MINI[1:0] ILIM DCR Type R/W R/W R/W R/W Bit Name Function 7:6 DCV[1:0] TIP/RING Voltage Adjust. Adjust the voltage on the DCT pin of the line-side device, which affects the TIP/RING voltage on the line. Low voltage countries should use a lower TIP/RING voltage. Raising the TIP/ RING voltage improves signal headroom. DCV[1:0] DCT Pin Voltage 00 3.1 V 01 3.2 V 10 3.35 V 11 3.5 V 5:4 MINI[1:0] Minimum Operational Loop Current. Adjusts the minimum loop current so the DAA can operate. Increasing the minimum opera- tional loop current improves signal headroom at a lower TIP/RING voltage. MINI[1:0] Min Loop Current 00 10 mA 01 12 mA 10 14 mA 11 16 mA 3:2 Reserved Do not write to these register bits. 1 ILIM Current Limiting Enable. 0 = Current limiting mode disabled. 1 = Current limiting mode enabled. Limits loop current to a maximum of 60 mA per the TBR21 standard. 0 DCR DC Impedance Selection. 0=5 0 Ω dc termination is selected. Use this mode for all standard applications. 1 = 800 Ω dc termination is selected.

70 Rev. 1.05 Reset settings = xxxx_xxxx Reset settings = 0000_0000 Reset settings = 0000_0000 Register 27. Reserved B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name Type Bit Name Function 7:0 Reserved Do not read or write. Register 28. Loop Current Status B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name LCS2[7:0] Type R Bit Name Function 7:0 LCS2[7:0] Loop Current Status. Eight-bit value returning the loop current. Each bit represents 1.1 mA of loop current. 0000_0000 = Loop current is less than required for normal operation. Register 29. Line Voltage Status B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name LVS[7:0] Type R Bit Name Function 7:0 LVS[7:0] Line Voltage Status. Eight-bit value returning the loop voltage. Each bit represents 1 V of loop voltage. This regis- ter operates in on-hook and off-hook modes. Bit seven of this register indicates the polarity of the TIP/RING voltage. When this bit changes state, it indicates that a polarity reversal has occurred. The value returned is represented in 2s compliment format. 0000_0000 = No line is connected.

Rev. 1.05 71 Reset settings = 0000_0000 Register 30. AC Termination Control (Si3019 line-side device only) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name FULL2 ACIM[3:0] Type R/W R/W Bit Name Function 7:5 Reserved Read returns zero. 4F U L L 2 Enhanced Full Scale (2X) Transmit and Receive Mode (Si3019 line-side Revision E or later). 0=D e f a u l t 1 = Transmit/Receive 2X Full Scale This bit changes the full scale of the ADC and DAC from 0 min to +6 dBm into 600 Ω load (or 1.5 dBV into all reference impedances). When this bit is set, the DCV[1:0] bits (Register 26) should be set to all 1s to avoid distortion at low loop currents. 3:0 ACIM[3:0] AC Impedance Selection (Si3019 line-side device only). The off-hook ac termination is selected from the following: 0000 = 600 Ω 0001 = 900 Ω 0010 = 270 Ω + (750 Ω || 150 nF) (TBR21) and 275 Ω + (780 Ω || 150 nF) 0011 = 220 Ω + (820 Ω || 120 nF) (Australia/New Zealand) and 220 Ω + (820 Ω || 115 nF) (Slovakia/Slovenia/South Africa/Germany/Austria/Bulgaria) 0100 = 370 Ω + (620 Ω || 310 nF) (New Zealand #2/India) 0101 = 320 Ω + (1050 Ω || 230 nF) (England) 0110 = 370 Ω + (820 Ω || 110 nF) 0111 = 275 Ω + (780 Ω || 115 nF) 1000 = 120 Ω + (820 Ω || 110 nF) 1001 = 350 Ω + (1000 Ω || 210 nF) 1010 = 0 Ω + (900 Ω || 30 nF) (line-side Revision C or earlier) 1010 = 200 Ω + (680 Ω || 100 nF) (China) (line-side Revision E or later) 1011 = 600 Ω + 2.16 µF 1100 = 900 Ω + 1 µF 1101 = 900 Ω + 2.16 µF 1110 = 600 Ω + 1 µF 1111 = Global impedance

72 Rev. 1.05 Reset settings = 0010_0000 Register 31. DAA Control 3 B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name FULL FOH[1:0] OHS2 FILT LVFD Type R/W R/W R/W R/W R/W Bit Name Function 7F U L L Full Scale Transmit and Receive Mode (Si3019 line-side device only). 0=D e f a u l t . 1 = Transmit/receive full scale. This bit changes the full scale of the ADC and DAC from 0 min to +3.2 dBm into a 600Ω load (or 1 dBV into all reference impedances). When this bit is set, the DCV[1:0] bits (Register 26) should be set to all 1s to avoid distortion at low loop currents. 6:5 FOH[1:0] Fast Off-Hook Selection. These bits determine the length of the off-hook counter. The default setting is 128 ms. 00 = 512 ms. 01 = 128 ms. 10 = 64 ms. 11 = 8 ms. 4 Reserved Read returns zero. 3O H S 2 On-Hook Speed 2. This bit, in combination with the OHS bit (Register 16) and the SQ[1:0] bits on-hook speeds specified are measured from the time the OH bit is cleared until loop current equals zero. OHS OHS2 SQ[1:0] Mean On-Hook Speed 0 0 00 Less than 0.5 ms 0 1 00 3 ms ±10% (meets ETSI standard) 2 Reserved Read returns zero. 1F I L T Filter Pole Selection (Si3019 line-side device only). 0 = The receive path has a low –3 dBFS corner at 5 Hz. 1 = The receive path has a low –3 dBFS corner at 200 Hz. 0L V F D Line Voltage Force Disable (Si3019 line-side device only). 0 = Normal operation. 1 = The circuitry that forces the LVS register (Register 29) to all 0s at 3 V or less is disabled. The LVS register may display unpredictable values at voltages between 0 to 2 V. All 0s are displayed if the line voltage is 0 V.

Rev. 1.05 73 Reset settings = 0000_0000 Reset settings = 0000_0000 Register 32-37. Reserved B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name Type Bit Name Function 7:0 Reserved Read returns zero. Register 38. TX Gain Control 2 (Si3019 Line-Side Device Only) B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name TGA2 TXG2[3:0] Type R/W R/W Bit Name Function 7:5 Reserved Read returns zero. 4T G A 2 Transmit Gain or Attenuation 2. 0 = Incrementing the TXG2[3:0] bits results in gaining up the transmit path. 1 = Incrementing the TXG2[3:0] bits results in attenuating the transmit path. 3:0 TXG2[3:0] Transmit Gain 2. Each bit increment represents 1 dB of gain or attenuation, up to a maximum of +12 dB and –15 dB respectively. For example: TGA2 TXG2[3:0] Result X 0000 0 dB gain or attenuation is applied to the transmit path. 0 0001 1 dB gain is applied to the transmit path. 0 : 0 11xx 12 dB gain is applied to the transmit path. 1 0001 1 dB attenuation is applied to the transmit path. 1 : 1 1111 15 dB attenuation is applied to the transmit path.

74 Rev. 1.05 Reset settings = 0000_0000 Register 39. RX Gain Control 2 (Si3019 Line-Side Device Only) B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name RGA2 RXG2[3:0] Type R/W R/W Bit Name Function 7:5 Reserved Read returns zero. 4R G A 2 Receive Gain or Attenuation 2. 0 = Incrementing the RXG2[3:0] bits results in gaining up the receive path. 1 = Incrementing the RXG2[3:0] bits results in attenuating the receive path. 3:0 RXG2[3:0] Receive Gain 2. Each bit increment represents 1 dB of gain or attenuation, up to a maximum of +12 dB and – 15 dB respectively. For example: RGA2 RXG2[3:0] Result X 0000 0 dB gain or attenuation is applied to the receive path. 0 0001 1 dB gain is applied to the receive path. 0 : 0 11xx 12 dB gain is applie d to the receive path. 1 0001 1 dB attenuation is applied to the receive path. 1 : 1 1111 15 dB attenuation is applied to the receive path.

Rev. 1.05 75 Reset settings = 0000_0000 Register 40. TX Gain Control 3 (Si3019 Line-Side Device Only) B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name TGA3 TXG3[3:0] Type R/W R/W Bit Name Function 7:5 Reserved Read returns zero. 4T G A 3 Transmit Gain or Attenuation 3. 0 = Incrementing the TXG3[3:0] bits results in gaining up the transmit path. 1 = Incrementing the TXG3[3:0] bits results in attenuating the transmit path. 3:0 TXG3[3:0] Transmit Gain 3. Each bit increment represents 0.1 dB of gain or attenuation, up to a maximum of 1.5 dB. For example: TGA3 TXG3[3:0] Result X 0000 0 dB gain or attenuation is applied to the transmit path. 0 0001 0.1 dB gain is appli ed to the transmit path. 0 : 0 1111 1.5 dB gain is appli ed to the transmit path. 1 0001 0.1 dB attenuation is applied to the transmit path. 1 : 1 1111 1.5 dB attenuation is applied to the transmit path.

76 Rev. 1.05 Reset settings = 0000_0000 Reset settings = 0000_0000 Register 41. RX Gain Control 3 (Si3019 Line-Side Device Only) B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name RGA3 RXG3[3:0] Type R/W R/W Bit Name Function 7:5 Reserved Read returns zero. 4R G A 3 Receive Gain or Attenuation 2. 0 = Incrementing the RXG3[3:0] bits results in gaining up the receive path. 1 = Incrementing the RXG3[3:0] bits results in attenuating the receive path. 3:0 RXG3[3:0] Receive Gain 3. Each bit increment represents 0.1 dB of gain or attenuation, up to a maximum of 1.5 dB. For example: RGA3 RXG3[3:0] Result X 0000 0 dB gain or attenuation is applied to the receive path. 0 0001 0.1 dB gain is applied to the receive path. 0 : 0 1111 1.5 dB gain is applied to the receive path. 1 0001 0.1 dB attenuation is applied to the receive path. 1 : 1 1111 1.5 dB attenuation is applied to the receive path. Register 42. Reserved B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name Type Bit Name Function 7:0 Reserved Read returns zero.

Rev. 1.05 77 Reset settings = 0000_0000 Reset settings = 0000_0000 Register 43. Line Current/Voltage Threshold Interrupt (Si3019 Line-Side Device Only) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name CVT[7:0] Type R/W Bit Name Function 7:0 CVT[7:0] Current/Voltage Threshold. Determines the threshold at which an interrupt is generated from either the LCS or LVS regis- ter. Generate this interrupt to occur when the line current or line voltage rises above or drops below the value in the CVT[7:0] register. Register 44. Line Current/Voltage Threshold Interrupt Control (Si3019 Line-Side Device Only) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name CVI CVS CVM CVP Type R/W R/W R/W R/W Bit Name Function 7:4 Reserved Read returns zero. 3C V I Current/Voltage Interrupt. 0 = The current / voltage threshold has not been crossed. 1 = The current / voltage threshold is crossed. If the CVM and INTE bits are set, a hardware interrupt occurs on the AOUT/INT pin. Once set, this bit must be written to 0 to be cleared. 2C V S Current/Voltage Select. 0 = The line current shown in the LCS2 register generates an interrupt. 1 = The line voltage shown in the LVS register generates an interrupt. 1C V M Current/Voltage Interrupt Mask. 0 = The current / voltage threshold being triggered does not cause a hardware interrupt on the AOUT/INT pin. 1 = The current / voltage threshold being triggered causes a hardware interrupt on the AOUT/ INT pin. 0C V P Current/Voltage Interrupt Polarity. 0 = The current / voltage threshold is triggered by the absolute value of the number in either the LCS2 or LVS register falling below the value in the CVT[7:0] register. 1 = The current / voltage threshold is triggered by the absolute value of the number in the either the LCS2 or LVS register rising above the value in the CVT[7:0] Register.

78 Rev. 1.05 Reset settings = 0000_0000 Reset settings = 0000_0000 Register 45. Programmable Hybrid Register 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB1 [7:0] Type R/W Bit Name Function 7:0 HYB1[7:0] Programmable Hybrid Register 1. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the first tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Bal- ance" on page 29 for more information on selecting coefficients for the programmable hybrid. Register 46. Programmable Hybrid Register 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB2[7:0] Type R/W Bit Name Function 7:0 HYB2[7:0] Programmable Hybrid Register 2. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the second tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Balance" on page 29 for more information on selecting coefficients for the programmable hybrid.

Rev. 1.05 79 Reset settings = 0000_0000 Reset settings = 0000_0000 Register 47. Programmable Hybrid Register 3 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB3[7:0] Type R/W Bit Name Function 7:0 HYB3[7:0] Programmable Hybrid Register 3. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the third tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Balance" on page 29 for more information on selecting coefficients for the programmable hybrid. Register 48. Programmable Hybrid Register 4 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB4[7:0] Type R/W Bit Name Function 7:0 HYB4[7:0] Programmable Hybrid Register 4. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the fourth tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Balance" on page 29 for more information on selecting coefficients for the programmable hybrid.

80 Rev. 1.05 Reset settings = 0000_0000 Reset settings = 0000_0000 Register 49. Programmable Hybrid Register 5 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB5[7:0] Type R/W Bit Name Function 7:0 HYB5[7:0] Programmable Hybrid Register 5. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the fifth tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Bal- ance" on page 29 for more information on selecting coefficients for the programmable hybrid. Register 50. Programmable Hybrid Register 6 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB6[7:0] Type R/W Bit Name Function 7:0 HYB6[7:0] Programmable Hybrid Register 6. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the sixth tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See"5.13.Transhybrid Bal- ance" on page 29 for more information on selecting coefficients for the programmable hybrid.

Rev. 1.05 81 Reset settings = 0000_0000 Reset settings = 0000_0000 Reset settings = xxxx_xxxx Register 51. Programmable Hybrid Register 7 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB7[7:0] Type R/W Bit Name Function 7:0 HYB7[7:0] Programmable Hybrid Register 7. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the seventh tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Balance" on page 29 for more information on selecting coefficients for the programmable hybrid. Register 52. Programmable Hybrid Register 8 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HYB8[7:0] Type R/W Bit Name Function 7:0 HYB8[7:0] Programmable Hybrid Register 8. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the eighth tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Balance" on page 29 for more information on selecting coefficients for the programmable hybrid. Register 53-58 Reserved B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name Type Bit Name Function 7:0 Reserved Do not write to these register bits.

82 Rev. 1.05 Reset settings = 0000_0000 Register 59. Spark Quenching Control B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name TB3 SQ1 SQ0 RG1 GCE Type R/W R/W R/W R/W R/W Bit Name Function

7 TB3 For South Korea PTT compliance, set this bit, in addition to the RZ bit, to synthesize a ringer

impedance to meet South Korea ringer impedance requirements. This bit should only be set to meet South Korea PTT requirements and should only be set in conjunction with the RZ bit. 6S Q 1 Spark Quenching. This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets the amount of time for the line-side device to go on-hook. The on-hook speeds specified are measured from the time the OH bit is cleared until loop current equals zero. OHS OHS2 SQ[1:0] Mean On-Hook Speed 0 0 00 Less than 0.5 ms 0 1 00 3 ms ±10% (meets ETSI standard)

1 X 11 26 ms ±10% (meets Australia spark quenching

spec) 5 Reserved Always write this bit to zero. 4S Q 0 Spark Quenching. This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets the amount of time for the line-side device to go on-hook. The on-hook speeds specified are measured from the time the OH bit is cleared until loop current equals zero. OHS OHS2 SQ[1:0] Mean On-Hook Speed 0 0 00 Less than 0.5 ms 0 1 00 3 ms ±10% (meets ETSI standard) spec) 3 Reserved Always write this bit to zero. 2R G 1 Receive Gain 1 (Line-side Revision E or later). This bit enables receive path gain adjustment. 0 = No gain applied to hybrid, full scale RX on line = 0 dBm. 1 = 1 dB of gain applied to hybrid, full scale RX on line = –1 dBm. 1G C E Guarded Clear Enable (Line-side Revision E or later). This bit (in conjunction with the RZ bit set to 1), enables the Si3056 to meet BT’s Guarded Clear Spec (B5 6450, Part 1: 1993, Section 15.4.3.3). With these bits set, the DAA will draw approximately 2.5 mA of current from the line while on-hook. 0 = default, DAA does not draw loop current. 1 = Guarded Clear enabled, DAA draws 2.5 mA while on-hook to meet Guarded Clear requirement. 0 Reserved Always write this bit to zero.

Table 24. Si3056 Pin Descriptions 1M C L K Master Clock Input. 2F S Y N C Frame Sync Output. Data framing signal that indicates the start and stop of a communication/data frame. 3S C L K Serial Port Bit Clock Output. Controls the serial data on SDO and latches the data on SDI. 4V D Digital Supply Voltage. Provides the 3.3 V digital supply voltage to the Si3056. 5S D O Serial Port Data Out. Serial communication data that is provided by the Si3056 to the modem/DSP. sented as an input to the Si3056. 7 FC/RGDT Secondary Transfer Request Input/Ring Detect. ondary frame. When daisy chain is enabled, this pin becomes the ring detect output. Produces an active low rectified version of the ring signal. used to bring the Si3056 out of sleep mode. 9C 2 A Isolation Capacitor 2A. 10 C1A Isolation Capacitor 1A.

11 AOUT/INT Analog Speaker Out/Interrupt. interrupt for multiple sources of interrupts. Connects to the system digital ground. 13 V A Analog Supply Voltage. Provides the analog supply voltage for the Si3056. 15 RGDT /FSD/M1 Ring Detect/Delayed Frame Sync/Mode Select 1. selects the operation of the serial port/DSP interface when RESET is deasserted. Table 24. Si3056 Pin Descriptions (Continued)

1. Pin Descriptions: Si3018/19/10

Table 25. Si3018/19/10 Pin Descriptions Connects to the emitter of Q3. Provides dc termination to the telephone network. Serves as the receive side input from the telephone network. 4I B Isolation Capacitor 1B. 6C 2 B Isolation Capacitor 2B. Connects to an external capacitor to provide bypassing for an internal power supply. and caller ID signals to the system-side device. and caller ID signals to the system-side device. 10 VREG2 Voltage Regulator 2. Connects to an external capacitor to provide bypassing for an internal power supply. Enables transistor network. Should be tied through a 0 Ω resistor to IGND. 12 QE2 Transistor Emitter 2. Connects to the emitter of transistor Q4.

Connects to the base of transistor Q4. Provides dc termination to the telephone network. Connects to ground on the line-side interface. Provides dc termination to the telephone network. Table 25. Si3018/19/10 Pin Descriptions (Continued)

88 Rev. 1.05 9. Ordering Guide1,2 System Side Part Number Package Lead Free Temp Range Si3056-KS SOIC-16 No 0 to 70 °C Si3056-X-FS SOIC-16 Yes 0 to 70 °C Line Side Part Number Package Lead Free Temp Range Si3010-X-FS SOIC-16 Yes 0 to 70 °C Si3018-X-FS SOIC-16 Yes 0 to 70 °C Si3019-X-FS SOIC-16 Yes 0 to 70 °C Notes: 1. "X" denotes product revision. 2. Add an "R" at the end of the device to denote tape and reel option; 2500 quantity per reel.

Rev. 1.05 89 10. Evaluation Board Ordering Guide Part Number Line-Side Device Platform Intended Use Includes Platform Board? Includes DAA Daughter Card? Si3056PPT-EVB Si3018 Parallel Port Direct Connection to a PC to use with included Windows®- based SW program. Yes (PPT) Yes Si3056PPT1-EVB Si3019 Parallel Port Si3056PPT2-EVB Si3010 Parallel Port Si3056SSI-EVB Si3018 Serial Interface with Buffer Direct Connection to processor or DSP (in customer application or to another EVB). Yes (SSI) Yes Si3056SSI1-EVB Si3019 Serial Interface with Buffer Si3056SSI2-EVB Si3010 Serial Interface with Buffer Si3056DC-EVB Si3018 Daughtercard Only Direct Connection to processor or DSP (in customer applica- tion). No Yes Si3056DC1-EVB Si3019 Daughtercard Only Si3056DC2-EVB Si3010 Daughtercard Only

Rev. 1.05 91 DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.71 „ Updated list of applications on cover page, including ability to support V.92 modems. „ Updated Transmit Full Scale Level test condition and note in Table 4 (AC Characteristics) for description of VCID and DRCID. „ Updated specifications in Table 7, Table 8, and Table 9 (Switching Characteristics) and Figure 3, Figure 4, and Figure 5. „ Updated “3.Bill of Materials” with revised values for C3, (10% to 20% tolerance relaxation on same value cap) Q4-5 (voltage rating was misstated at 60 V, changed to correct 80 V value), R51-52 power rating relaxed from 1/10 W to 1/16 W, and updated recommended ferrite bead part numbers. „ Fixed several grammatical errors in functional descriptions, and globally replaced all instances of CTR21 with TBR21. „ Added new functional description “5.1.Upgrading from the Si3034/35/44 to Si3056” to describe new features and changes to consider when migrating to the Si3056. „ Updated “Power Supplies” functional description to reflect 5 V tolerance on Si3056 input pins. „ Updated “5.6.Transmit/Receive Full Scale Level (Si3019 Line-Side Only)” functional description. „ Updated“5.8.Line Voltage/Loop Current Sensing” functional description. „ Updated “5.15.Ring Validation” functional description. „ Updated “5.21.2.Type II Caller ID” functional description. „ Updated “5.23.Gain Control” functional description. „ Updated “5.26.Digital Interface” functional description and Figure 29. „ Updated “Power Management” functional description to qualify description to qualify wake-on-ring support in low-power sleep mode. „ Updated “5.30.In-Circuit Testing” functional description. „ Updated “5.6.Transmit/Receive Full Scale Level (Si3019 Line-Side Only)” functional description. „ Updated “5.8.1.Line Voltage Measurement” functional description. „ Updated “5.10.Interrupts” functional description. „ Updated “5.11.DC Termination” functional description. „ Updated “6.Control Registers” to reflect LVFD bit available exclusively with the Si3019 line-side. „ Updated the following bit descriptions: z R4.7 z R12.4–0 z R14.2 z R17.4 z R20-21 z R28 z R29 z R31.0,3,7 z R38–41 „ Updated “Ordering Guide.” „ Added list of support documentation. Revision 0.71 to Revision 1.0 „ Added Si3010 to data sheet title, and to Line-Side device support functional description, and application circuit. „ Updated Tables 2, 3, & 4 based on production test results. „ Updated Table 4 with footnotes to explain expected DR and THD when using the Si3056 with the Si3010 low-speed line-side device. „ Updated BOM. „ Updated Country Specific Register Settings. „ Updated the following functional descriptions: z Line Voltage/Loop Current Sensing z Interrupts z DC Termination z Ring Detection z Ring Validation z Ringer Impedance and Threshold z Caller ID z Overload Detection z Gain Control (added diagram) z Power Management z Revision Identification „ Updated Register Summary „ Updated the following Register Descriptions z Register 1 bit 1 z Register 3 bit 1 (added bit description) z Register 4 bit 1 (added bit description) z Register 5 bit 2 z Register 12 bits 4:0 z Register 13 bit 6 z Register 16 bit 0 z Register 18 bit 1 z Register 19 bit 1 z Register 24 bits 5:0 z Register 31 bit 7 „ Updated ordering guide „ Added Evaluation Board ordering guide

92 Rev. 1.05 Revision 1.0 to Revision 1.01 „ Removed “Confidential” watermark. Revision 1.01 to Revision 1.02 „ Updated Table 2, “Loop Characteristics,” on page 6. „ Updated Table 4, “AC Characteristics,” on page 8 „ Updated "3.Bill of Materials" on page 19 z Added optional caller ID circuit components in footnotes. z Removed R14. „ Updated Line Voltage/Loop Current Sensing functional description. „ Updated "9.Ordering Guide1,2" on page 88. „ Updated "11.Package Outline: 16-Pin SOIC" on page 90. „ Updated Table 26, “Package Diagram Dimensions,” on page 90. Revision 1.02 to Revision 1.03 „ Updated Table 4 on page 8. „ Updated Table 6 on page 10 to add MCLK jitter tolerance. „ Added Table 10 on page 14. „ Updated Table 13 on page 20. „ Updated Table 15 on page 23. z Changed recommended country settings for Australia, Austria, Bahrain, Bulgaria, China, Croatia, Cyprus, Czech Republic, Egypt, Germany, Hungary, Israel, India, Japan, Jordan, Kazakhstan, Latvia, Lebanon, Malyasia, Malta, Morocco, Nigeria, Oman, Pakistan, Philippines, Poland, Romania, Russia, Slovakia, Slovenia, South Africa, South Korea, Syria, Taiwan, Thailand. „ Updated Table 18 on page 28 (changed act for ACIM = 1010). „ Added Figure 6 on page 14. „ Updated "5.25.Clock Generation" on page 36. „ Updated Table 23, “Register Summary,” on page 48. „ Updated Table 24, “Si3056 Pin Descriptions,” on page 84. „ Updated Figure 19 on page 26. „ Updated "5.6.Transmit/Receive Full Scale Level (Si3019 Line-Side Only)" on page 25 of Functional description to include new enhanced full scale mode. „ The following bits have been added, but will only be supported with Si3018/19/10 Revision E or later line- side devices. z Added FULL2 bit on p. 73. z Added RG1 and GCE bits on p. 89. „ Updated Table 24 on page 84. „ Updated "9.Ordering Guide1,2" on page 88. „ Update “12.Product Identification”. „ Updated "3.Bill of Materials" on page 19. z Changed recommended case size of FB1, FB2. Revision 1.03 to Revision 1.05 „ Updated voltage rating from 60 to 80 V for Q4, Q5 in bill of materials. This is the actual rating of the specified component. This change only corrects the typo in the data sheet. „ Updated Figure 25 on page 35. „ Updated reset settings for R.59. „ Added support for TB3 bit to meet South Korea ringer impedance requirements. „ Updated Ordering Guide on page 88. z Removed product selection and product identification sections.

Rev. 1.05 93 SILICON LABORATORIES Si3056 SUPPORT DOCUMENTATION „ Application Note 13: Silicon DAA Software Guidelines „ Application Note 16: Multiple Device Support „ Application Note 17: Designing for International Safety Compliance „ Application Note 67: Layout Guidelines „ Application Note 72: Ring Detection/Validation with the Si305x DAAs „ Application Note 84: Digital Hybrid with the Si305x DAAs „ Si30xxPPT-EVB Data Sheet „ Si30xxSSI-EVB Data Sheet Note: Refer to www.silabs.com for a current list of support documents for this chipset.

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