SFD60N03L

SFD60N03L SEMIWELL | Alldatasheet

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■ Low RDS(on) (0.019Ω )@VGS=10V ■ Low Gate Charge (Typical 21.5nC) ■ Low Crss (Typical 130pF) ■ Improved dv/dt Capability ■ 100% Avalanche Tested ■ Maximum Junction Temperature Range (150°C) General Description This Power MOSFET is produced using SemiWell’s advanced planar stripe, DMOS technology. This latest technology has been especially designed to minimize on-state resistance, have a low gate charge with superior switching performance and rugged avalanche characteristics. This Power MOSFET is well suited for synchronous DC-DC Converters and Power Management in portable and battery operated products. SemiWell Semiconductor Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. Symbol 2. Drain 3. Source 1. Gate PRELIMINARY Logic N-Channel MOSFET D-PACK (TO-252) * When mounted on the minimum pad size recommended (PCB Mount)

Electrical Characteristics ( TC = 25 °C unless otherwise noted ) Symbol Parameter Test Co nditions Min Typ Max Units Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0V, ID = 250uA 30 - - V Δ BVDSS/ Δ TJ Breakdown Voltage Temperature coef- ficient ID = 250uA, referenced to 25 °C -0 . 0 2 -V / ° C IDSS Drain-Source Leakage Current VDS = 30V, VGS = 0V -- 1 u A VDS = 24V, TC = 125 °C - - 10 uA IGSS Gate-Source Leakage, Forward VGS = 20V, VDS = 0V - - 100 nA Gate-Source Leakage, Reverse VGS = -20V, VDS = 0V - - -100 nA On Characteristics VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250uA 1.0 - 3.0 V RDS(ON) Static Drain-Source On-state Resis- tance VGS = 10 V, ID = 20.2A VGS = 5 V, ID = 20.2A 0.013 0.017 0.019 0.024 Ω Dynamic Characteristics Ciss Input Capacitance VGS =0 V, VDS =25V, f = 1MHz - 1010 1320 pFCoss Output Capacitance - 450 585 Crss Reverse Transfer Capacitance - 130 170 Dynamic Characteristics td(on) Turn-on Delay Time VDD =15V, ID =30A, RG =50Ω ※ see fig. 13. (Note 4, 5) -2 0 5 0 ns tr Rise Time - 55 120 td(off) Turn-off Delay Time - 50 110 tf Fall Time - 75 160 Qg Total Gate Charge VDS =24V, VGS =5V, ID =60A ※ see fig. 12. (Note 4, 5) -2 1 . 5 2 8 nCQgs Gate-Source Charge - 3.6 - Qgd Gate-Drain Charge(Miller Charge) - 10.7 - Source-Drain Diode Ratings and Characteristics Symbol Parameter Test Cond itions Min. Typ. Max. Unit. IS Continuous Source Current Int egral Reverse p-n Junction Diode in the MOSFET - - 40.3 AISM Pulsed Source Current - - 161 VSD Diode Forward Voltage I S =40.3A, VGS =0V - - 1.5 V trr Reverse Recovery Time IS=60A,VGS=0V,dIF/dt=100A/us -4 0 -n s Qrr Reverse Recovery Charge - 35 - nC ※NOTES 1. Repeativity rating : pulse width limited by junction temperature 2. L = 165uH, IAS =40.3A, VDD = 15V, RG = 0Ω , Starting TJ = 25°C 3. ISD ≤ 60A, di/dt ≤ 300A/us, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse Width ≤ 300us, Duty Cycle ≤ 2% 5. Essentially independent of operating temperature. Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.

Top : 10.0 V 8.0 V 6.0 V 5.0 V 4.5 V 4.0 V 3.5 V Bottom : 3.0 V Notes :※ 1. 250µ s Pulse Test 2. T C = 25℃ ID, Drain Current [A] VDS, Drain-Source Voltage [V] 150℃ Notes :※ 1. VGS = 0V 2. 250µ s Pulse Test 25℃ IDR, Reverse Drain Current [A] VSD, Source-Drain voltage [V] 0 40 80 120 160 200 VGS = 5V VGS = 10V Note : T※ J = 25℃ RDS(ON), Drain-Source On-Resistance [mΩ ] ID, Drain Current [A] 02468 1 0 150 o C o C -55 o C Notes :※ 1. VDS = 15V 2. 250µ s Pulse Test ID, Drain Current [A] VGS, Gate-Source Voltage [V] 0 5 10 15 20 25 30 35 500 1000 1500 2000 2500 3000 Crss Coss Ciss Notes :※ 1. VGS = 0V 2. f=1MHz Ciss=Cgs+Cgd(Cds=shorted) Coss=Cds+Cgd Crss=Cgd Capacitance [pF] VDS, Drain-Source Voltage [V] 0 5 10 15 20 25 30 35 40 45 VDS = 15V VDS = 24V Note : I※ D = 60.0 A VGS, Gate-Source Voltage [V] Qg, Total Gate Charge [nC] Fig 4. On State Current vs. Allowable Case Temperature Fig 5. Capacitance Characteristics Fig 6. Gate Charge Characteristics SFD60N03L Fig 1. On-State Characteristics Fig 2. Transfer Characteristics Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. Fig 3. On Resistance Variation vs. Drain Current and Gate Voltage

100 µs Operation in This Area is Limited by R DS(on) Notes :※ 1. TC = 25 o C 2. TJ = 150 o C 3. Single Pulse ID, Drain Current [A] VDS, Drain-Source Voltage [V] 25 50 75 100 125 150 ID, Drain Current [A] TC, Case Temperature [ ]℃ -100 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 Notes :※ 1. VGS = 10 V 2. ID = 24 A RDS(ON), (Normalized) Drain-Source On-Resistance TJ, Junction Temperature [ o -100 -50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 Notes :※ 1. VGS = 0 V 2. ID = 250 µ A BVDSS, (Normalized) Drain-Source Breakdown Voltage TJ, Junction Temperature [ o Notes :※ 1. Z θ JC(t) = 2.25 /W Max.℃ 2. Duty Factor, D=t 1/t2 3. T JM - T C = P DM * Z θ JC(t) single pulse D=0.5 0.02 0.2 0.05 0.1 0.01 Zθ JC(t), Thermal Response t1, Square W ave Pulse Duration [sec] Fig 11. Transient Thermal Response Curve Fig 7. Breakdown Voltage Variation vs. Junction Temperature Fig 8. On-Resistance Variation vs. Junction Temperature SFD60N03L Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. Fig 9. Maximum Safe Operating Area Fig 10. Maximum Drain Current vs. Case Temperature

Fig 13. Switching Time Test Circuit & Waveforms Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms SFD60N03L Fig. 12. Gate Charge Test Circuit & Waveforms EAS =L L IAS 2----2 BVDSS -- VDD BVDSS EAS =L L IAS 2----2 1EAS =L L IAS 2----2 1----2 BVDSS -- VDD BVDSS VDD VDS BVDSS t p VDD IAS VDS (t) ID (t) Time BVDSS t p VDD IAS VDS (t) ID (t) Time 10V DUT RG LL I DI D Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved. Charge VGS Qg Qgs Qgd 1mA VGS DUT VDS 300nF 50KΩ 200nF12V Same Type as DUT Charge VGS V Qg Qgs Qgd Charge VGS V Qg Qgs Qgd 1mA VGS DUT VDS 300nF 50KΩ 200nF12V Same Type as DUT Charge VGS Qg Qgs Qgd Charge VGS Qg Qgs Qgd 1mA VGS DUT VDS 300nF 50KΩ 200nF12V Same Type as DUT Charge VGS V Qg Qgs Qgd Charge VGS V Qg Qgs Qgd 1mA VGS DUT VDS 300nF 50KΩ 200nF12V Same Type as DUT Vin VDS 10% 90% td(on) tr t on t off td(off) tf VDD ( 0.5 rated VDS ) VDS RL DUT Pulse Generator Vin VDS 10% 90% td(on) tr t on t off td(off) tf Vin VDS 10% 90% td(on) tr t on t off td(off) tf VDD ( 0.5 rated VDS ) V VDS RL DUT Pulse Generator RG Vin VDS 10% 90% td(on) tr t on t off td(off) tf Vin VDS 10% 90% td(on) tr t on t off td(off) tf VDD ( 0.5 rated VDS ) VDS RL DUT Pulse Generator Vin VDS 10% 90% td(on) tr t on t off td(off) tf Vin VDS 10% 90% td(on) tr t on t off td(off) tf VDD ( 0.5 rated VDS ) V VDS RL DUT Pulse Generator RG

VGS • dv/dt controlled by RG

• IS controlled by pulse period VDD LL I SI S Fig. 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms 10V VGS ( Driver ) I S ( DUT ) VDS ( DUT ) VDD Body Diode Forward Voltage Drop Vf IFM , Body Diode Forward Current Body Diode Reverse Current IRM Body Diode Recovery dv/dt di/dt D = Gate Pulse Width 10V VGS ( Driver ) I S ( DUT ) VDS ( DUT ) VDD Body Diode Forward Voltage Drop Vf IFM , Body Diode Forward Current Body Diode Reverse Current IRM Body Diode Recovery dv/dt di/dt D = Gate Pulse Width Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.

Dim. mm Inch G 2.286 0.09 H 2.286 0.09 K 0.508 0.02 L 0.762 0.03 φ 1.57 0.06 SFD60N03L TO-252(D-PAK) Package Dimension 1. Gate 2. Drain 3. Source A B C D E G F H I J K L φ