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www.sii-ic.com BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) © Seiko Instruments Inc., 2005-2015 Rev.4.2_00 Seiko Instruments Inc. 1 The S-8264A/B/C Series is used for secondary protection of lithium-ion rechargeable batteries, and incorporates a high-accuracy voltage detection circuit and a delay circuit. Short-circuiting between cells makes it possible for serial connection of two cells to four cells. Features (1) High-accuracy voltage detection circuit for each cell
- Overcharge detection voltage n (n = 1 to 4) 4.20 V to 4.80 V (in 50 mV steps) Accuracy : ±25 mV (+25°C), Accuracy : ±30 mV (−5°C to +55°C)
- Overcharge hysteresis voltage n (n = 1 to 4) (2) Delay times for overcharge detection can be set by an in ternal circuit only (external capacitors are unnecessary) (3) Output control function via CTL pin (CTL pin is pulled down internally) (S-8264A Series) Output control function via CTL pin (CTL pin is pulled up internally) (S-8264C Series) (4) Output latch function after overcharge detection (S-8264B Series) (5) Output form and logic CMOS output active “H” (6) High withstand voltage devices Absolute maximum rating : 26 V (7) Wide operating voltage range 3.6 V to 24 V (8) Wide operating temperature range −40°C to +85°C (9) Low current consumption
- At 3.5 V for each cell 5.0 μA max. (+25°C)
- At 2.3 V for each cell 4.0 μA max. (+25°C) (10) Lead-free, Sn 100%, halogen-free *1 *1. Refer to “ Product Name Structure” for details. Application
- Lithium-ion rechargeable battery packs (for secondary protection) Packages
- SNT-8A
- 8-Pin TSSOP
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) S-8264A/B/C Series Rev.4.2_00 Seiko Instruments Inc. 2 Block Diagrams (1) S-8264A Series Overcharge detection/release delay circuit VC2 VC1 CO SENSE VC3 VSS VDD Overcharge detection comparator 1 Overcharge detection comparator 2 Overcharge detection comparator 3 Overcharge detection comparator 4 Reference voltage 1 Reference voltage 2 Reference voltage 3 Reference voltage 4 CTL Oscillator Control logic Remark The diodes in the figure are parasitic diodes. Figure 1
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.2_00 S-8264A/B/C Series Seiko Instruments Inc. 3 (2) S-8264B Series Overcharge detection/release delay circuit VC2 VC1 CO +SENSE VC3 VSS VDD CTL Oscillator SR latch UVLO Overcharge detection comparator 1 Overcharge detection comparator 2 Overcharge detection comparator 3 Overcharge detection comparator 4 Reference voltage 1 Reference voltage 2 Reference voltage 3 Reference voltage 4 Control logic Remark The diodes in the figure are parasitic diodes. Figure 2
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) S-8264A/B/C Series Rev.4.2_00 Seiko Instruments Inc. 4 （3）S-8264C Series Overcharge detection/release delay circuit VC2 VC1 CO ＋SENSE VC3 VSS VDD Overcharge detection comparator 1 Overcharge detection comparator 2 Overcharge detection comparator 3 Overcharge detection comparator 4 Reference voltage 1 Reference voltage 2 Reference voltage 3 Reference voltage 4 CTL Oscillator Control logic Remark The diodes in the figure are parasitic diodes. Figure 3
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.2_00 S-8264A/B/C Series Seiko Instruments Inc. 5 Product Name Structure 1. Product Name (1) SNT-8A Serial code*2 Sequentially set from AA to AZ S-8264 x xx - I8T1 U Environmental code U : Lead-free (Sn 100%), halogen-free Package abbreviation and IC packing specification*1 I8T1 : SNT-8A, Tape Product type A : Without CO pin output latch function (CTL pin is pulled down internally) B : With CO pin output latch function C : Without CO pin output latch function (CTL pin is pulled up internally) *1. Refer to the tape drawing. *2. Refer to “3. Product Name List”. (2) 8-Pin TSSOP Serial code*2 Sequentially set from AA to AZ S-8264 x xx - T8T1 x Environmental code U : Lead-free (Sn 100%), halogen-free G : Lead-free (for details, please contact our sales office) Package abbreviation and IC packing specification*1 T8T1: 8-Pin TSSOP, Tape Product type A : Without CO pin output latch function (CTL pin is pulled down internally) B : With CO pin output latch function C : Without CO pin output latch function (CTL pin is pulled up internally) *1. Refer to the tape drawing. *2. Refer to “3. Product Name List”. 2. Packages Package Name Drawing Code Package Tape Reel Land SNT-8A PH008-A-P-SD PH008-A-C- SD PH008-A-R-SD PH008-A-L-SD 8-Pin TSSOP Environmental code = G FT008-A- P-SD FT008-E-C-SD FT008-E-R-SD ⎯ Environmental code = U FT008-A- P-SD FT008-E-C-SD FT008-E-R-S1
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) S-8264A/B/C Series Rev.4.2_00 Seiko Instruments Inc. 6 3. Product Name List (1) S-8264A Series Table 1 SNT-8A Product Name Overcharge Detection Voltage [VCU] Overcharge Hysteresis Voltage [VHC] Overcharge Detection Delay Time [tCU] Output Form Table 2 8-Pin TSSOP Product Name Overcharge Detection Voltage [VCU] Overcharge Hysteresis Voltage [VHC] Overcharge Detection Delay Time [tCU] Output Form (2) S-8264B Series Table 3 SNT-8A Product Name Overcharge Detection Voltage [VCU] Overcharge Hysteresis Voltage [VHC] Overcharge Detection Delay Time [tCU] Output Form Table 4 8-Pin TSSOP Product Name Overcharge Detection Voltage [VCU] Overcharge Hysteresis Voltage [VHC] Overcharge Detection Delay Time [tCU] Output Form
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.2_00 S-8264A/B/C Series Seiko Instruments Inc. 7 (3) S-8264C Series Table 5 SNT-8A Product Name Overcharge Detection Voltage [VCU] Overcharge Hysteresis Voltage [VHC] Overcharge Detection Delay Time [tCU] Output Form Remark 1. Please contact our sales department for the products with detection voltage value other than those specified above. 2. x: G or U 3. Please select products of environmental code = U for Sn 100%, halogen-free products.
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) S-8264A/B/C Series Rev.4.2_00 Seiko Instruments Inc. 8 Pin Configurations SNT-8A Top view VDD SENSE VC1 VC2 CO CTL VSS VC3 Table 6 Pin No. Symbol Description
1 VDD Positive power input pin
2 SENSE Positive voltage connection pin of battery 1
3 VC1 Negative voltage connection pin of battery 1
Positive voltage connection pin of battery 2
4 VC2 Negative voltage connection pin of battery 2
Positive voltage connection pin of battery 3
5 VC3 Negative voltage connection pin of battery 3
Positive voltage connection pin of battery 4
6 VSS Negative power input pin
Negative voltage connection pin of battery 4
7 CTL CO output control pin (S-8264A/C Series)
Overcharge detection latch reset pin (S-8264B Series)
8 CO FET gate connection pin for charge
Pin No. Symbol Description Positive voltage connection pin of battery 2 Positive voltage connection pin of battery 3 Positive voltage connection pin of battery 4 Negative voltage connection pin of battery 4 Overcharge detection latch reset pin (S-8264B Series)
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.2_00 S-8264A/B/C Series Seiko Instruments Inc. 9 Absolute Maximum Ratings Table 8 (Ta = 25°C unless otherwise specified) Item Symbol Applied Pins Rating Unit Input voltage between VDD and VSS V DS VDD V SS − 0.3 to VSS + 26 V Input pin voltage VIN SENSE, VC1, VC2, VC3, CTL V SS − 0.3 to VDD + 0.3 V CO output pin voltage VCO CO V SS − 0.3 to VDD + 0.3 V Power dissipation SNT-8A PD ⎯ 450*1 mW 8-Pin TSSOP 700*1 mW Operation ambient temperature Topr ⎯ −40 to +85 °C Storage temperature Tstg ⎯ −40 to +125 °C *1. When mounted on board [Mounted board] (1) Board size : 114.3 mm × 76.2 mm × t1.6 mm (2) Name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 0 50 100 150 800 Power Dissipation (PD) [mW] Ambient Temperature (Ta) [°C] 8-Pin TSSOP 400 600 200 SNT-8A Figure 6 Power Dissipation of Package (When Mounted on Board)
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) S-8264A/B/C Series Rev.4.2_00 Seiko Instruments Inc. 10 Electrical Characteristics 1. Except Detection Delay Time Table 9 (Ta = 25°C unless otherwise specified) Item Symbol Conditions Min. Typ. Max. Unit Test Condition Test Circuit DETECTION VOLTAGE Overcharge detection voltage n (n = 1, 2, 3, 4) VCUn 4.20 V to 4.80 V, adjustable, Ta = 25°C VCUn−0.025 VCUn VCUn+0.025 V 1 1 4.20 V to 4.80 V, adjustable, Ta = −5°C to +55°C*1 VCUn−0.030 VCUn VCUn+0.030 V 1 1 Overcharge hysteresis voltage n*2 (n = 1, 2, 3, 4) VHCn ⎯ V HCn−0.21 −0.52 V HCn+0.21 V 1 1 INPUT VOLTAGE Operating voltage between VDD and VSS VDSOP ⎯ 3.6 ⎯ 24 V ⎯ ⎯ CTL input “H” voltage V CTLH ⎯ VDD×0.95 ⎯ ⎯ V 6 2 CTL input “L” voltage V CTLL ⎯ ⎯ ⎯ VDD×0.4 V 6 2 INPUT CURRENT Current consumption during operation IOPE V1 = V2 = V3 = V4 = 3.5 V ⎯ 2.5 5.0 μA 7 4 Current consumption during overdischarge IOPED V1 = V2 = V3 = V4 = 2.3 V ⎯ 2.0 4.0 μA 7 4 SENSE pin current I SENSE V1 = V2 = V3 = V4 = 3.5 V ⎯ 1.5 3.2 μA 8 5 VC1 pin current I VC1 V1 = V2 = V3 = V4 = 3.5 V −0.3 0 0.3 μA 8 5 VC2 pin current I VC2 V1 = V2 = V3 = V4 = 3.5 V −0.3 0 0.3 μA 8 5 VC3 pin current I VC3 V1 = V2 = V3 = V4 = 3.5 V −0.3 0 0.3 μA 8 5 CTL pin “H” current I CTLH A/B Series V1 = V2 = V3 = V4 = 3.5 V, VCTL = VDD 1.1 1.5 1.8 μA 8 5 C Series = V2 = V3 = V4 = 3.5 V VCTL = VDD ⎯ ⎯ 0.15 μA 8 5 CTL pin “L” current I CTLL A/B Series V1 = V2 = V3 = V4 = 3.5 V, VCTL = 0 V −0.15 ⎯ ⎯ μA 8 5 C Series = V2 = V3 = V4 = 3.5 V VCTL = 0 V −150 −50 −10 μA 8 5 OUTPUT CURRENT CO pin sink current I COL VCOP = VSS+0.5 V 0.4 ⎯ ⎯ mA 9 6 CO pin source current I COH VCOP = VDD−0.5 V 20 ⎯ ⎯ μA 9 6 *1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production. release voltage is the total of the overcharge detection voltage (VCUn) and the overcharge hysteresis voltage (VHCn).
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.2_00 S-8264A/B/C Series Seiko Instruments Inc. 11 2. Detection Delay Time (1) S-8264AAA, S-8264AAB, S-8264AAC, S-8264AAE, S-8264AAH, S-8264BAA, S-8264BAB Table 10 (Ta = 25°C unless otherwise specified) Item Symbol Conditions Min. Typ. Max. Unit Test Condition Test Circuit DELAY TIME Overcharge detection delay time tCU ⎯ 3.2 4.0 4.8 s 2 1 Overcharge timer reset delay time tTR ⎯ 6 12 20 ms 3 1 Overcharge release delay time tCL ⎯ 51 64 77 ms 2 1 CTL pin response time tCTL ⎯ ⎯ ⎯ 2.5 ms 4 2 Transition time to Test mode t TST V1 = V2 = V3 = V4 = 3.5 V, VDD ≥ VSENSE + 8.5 V ⎯ ⎯ 80 ms 5 3 (2) S-8264AAD, S-8264AAF, S-8264AAG, S-8264AAI, S-8264CAA, S-8264CAB Table 11 (Ta = 25°C unless otherwise specified) Item Symbol Conditions Min. Typ. Max. Unit Test Condition Test Circuit DELAY TIME Overcharge detection delay time t CU ⎯ 1.6 2.0 2.4 s 2 1 Overcharge timer reset delay time tTR ⎯ 6 12 20 ms 3 1 Overcharge release delay time tCL ⎯ 1.6 2.0 3.0 ms 2 1 CTL pin response time tCTL ⎯ ⎯ ⎯ 2.5 ms 4 2 Transition time to Test mode t TST V1 = V2 = V3 = V4 = 3.5 V, VDD ≥ VSENSE + 8.5 V ⎯ ⎯ 80 ms 5 3 (3) S-8264AAJ, S-8264AAK, S-8264AAO, S-8264AAS, S-8264AAT Table 12 (Ta = 25°C unless otherwise specified) Item Symbol Conditions Min. Typ. Max. Unit Test Condition Test Circuit DELAY TIME Overcharge detection delay time tCU ⎯ 4.5 5.65 6.8 s 2 1 Overcharge timer reset delay time tTR ⎯ 8 17 28 ms 3 1 Overcharge release delay time tCL ⎯ 70 88 110 ms 2 1 CTL pin response time tCTL ⎯ ⎯ ⎯ 2.5 ms 4 2 Transition time to Test mode t TST V1 = V2 = V3 = V4 = 3.5 V, VDD ≥ VSENSE + 8.5 V ⎯ ⎯ 80 ms 5 3
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) S-8264A/B/C Series Rev.4.2_00 Seiko Instruments Inc. 12 Test Circuits (1) Test Condition 1, Test Circuit 1 Set V1, V2, V3, and V4 to 3.5 V. Overcharge detection voltage 1 (V CU1) is the V1 voltage when CO is “H” after the voltage of V1 has been gradually increased. The overcharge hysteresis voltage (V HC1) is the difference between V1 and VCU1 when CO is “L” after the voltage of V1 has been gradually decreased. Overcharge detection voltage VCUn (n = 2 to 4) and overcharge hysteresis V HCn (n = 2 to 4) can be determined in the same way as when n = 1. (2) Test Condition 2, Test Circuit 1 Set V1, V2, V3, and V4 to 3.5 V and in a moment of time (within 10 μs) increase V1 up to 5.0 V. The overcharge detection delay time (tCU) is the period from when V1 reached 5.0 V to when CO becomes “H”. After that, in a moment of time (within 10 μs) decrease V1 down to 3.5 V. The overcharge release delay time (tCL) is the period from when V1 has reached 3.5 V to when CO becomes “L”. (3) Test Condition 3, Test Circuit 1 Set V1, V2, V3, and V4 to 3.5 V and in a moment of time (within 10 μs) increase V1 up to 5.0 V. This is defined as the first rise. Within tCU − 20 ms after the first rise, in a moment of time (within 10 μs) decrease V1 down to 3.5 V and then in a moment of time (within 10 μs) restore up to 5.0 V. This is defined as the second rise. When the period from when V1 was fallen to the second rise is short, CO becomes “H” after tCU has elapsed since the first rise. If the period from when V1 falls to the second rise is gradually made longer, CO becomes “H” when tCU has elapsed since the second rise. The overcharge timer reset delay time (tTR) is the period from V1 fall till the second rise at that time. (4) Test Condition 4, Test Circuit 2 In the S-8264A/C Series, set V1, V2, V3, and V4 to 3.5 V and V5 to 14 V. The CTL pin response time (tCTL) is the period from when V5 reaches 0 V after V5 is in a moment of time (within 10 μs) decreased down to 0 V to when CO becomes “H”. In the S-8264B Series, set V1, V2, V3, and V4 to 3.5 V and V5 to 14 V after an overvoltage is detected and CO becomes “H”. In a moment of time (within 10 μs) raise V5 from 0 V to 14 V. The CTL pin response time (t CTL) is the period from when V5 becomes 14 V to when CO becomes “L”. (5) Test Condition 5, Test Circuit 3 After setting V1, V2, V3, and V4 to 3.5 V and V5 to 0 V, in a moment of time (within 10 μs) increase V5 up to 8.5 V and decrease V5 again down to 0 V. When the period from wh en V5 was raised to when it has fallen is short, if an overcharge detection operation is performed subsequently, the ov ercharge detection time is t CU. However, when the period from when V5 is raised to when it is fallen is gr adually made longer, the overcharge detection time during the subsequent overcharge detection operation is shorter than tCU. The transition time to test mode (tTST) is the period from when V5 was raised to when it has fallen at that time.
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.2_00 S-8264A/B/C Series Seiko Instruments Inc. 13 (6) Test Condition 6, Test Circuit 2 Set V1, V2, V3, and V4 to 3.5 V and V5 to 0 V. The CTL input “H” voltage (VCTLH) is the maximum voltage of V5 when CO is “L” after V5 has been gradually increased. Next, set V5 to 14 V. The CTL input “L” voltage (VCTLL) is the minimum voltage of V5 when CO is “H” after V5 has been gradually decreased. (7) Test Condition 7, Test Circuit 4 The current consumption during operation (I OPE) is the total of the currents that flow in the VDD pin and SENSE pin when V1, V2, V3, and V4 are set to 3.5 V. The current consumption during overdischarge (IOPED) is the total of the currents that flow in the VDD pin and SENSE pin when V1, V2, V3, and V4 are set to 2.3 V. (8) Test Condition 8, Test Circuit 5 The SENSE pin current (ISENSE) is I1, the VC1 pin current (IVC1) is I2, the VC2 pin current (IVC2) is I3, the VC3 pin current (IVC3) is I4, and the CTL pin “H” current (ICTLH) is I5 when V1, V2, V3, and V4 are set to 3.5 V, and V5 to 14 V. The CTL pin “L” current (ICTLL) is I5 when V1, V2, V3, and V4 are set to 3.5 V and V5 to 0 V. (9) Test Condition 9, Test Circuit 6 Set SW1 to OFF and SW2 to ON. The CO pin sink current (ICOL) is I2 when V1, V2, V3, and V4 are set to 3.5 V and V6 to 0.5 V. Set SW1 and SW2 to OFF. Set V1 to V5, set V2, V3, and V4 to 3.0 V, and set V5 to 0.5 V. After t CU has elapsed, set SW1 to ON and SW2 to OFF. I1 is the CO pin source current (ICOH).
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) S-8264A/B/C Series Rev.4.2_00 Seiko Instruments Inc. 14 S-8264A/B/C Series VDD SENSE VC1 VC2 CO CTL VSS VC3 V S-8264A/B/C Series VDD SENSE VC1 VC2 CO CTL VSS VC3 VV5 Test Circuit 1 Test Circuit 2 S-8264A/B/C Series VDD SENSE VC1 VC2 CO CTL VSS VC3 V S-8264A/B/C Series VDD SENSE VC1 VC2 CO CTL VSS VC3 A Test Circuit 3 Test Circuit 4 S-8264A/B/C Series VDD SENSE VC1 VC2 CO CTL VSS VC3 A A A A A SW2 SW1 S-8264A/B/C Series VDD SENSE VC1 VC2 CO CTL VSS VC3 V6 V A I1 A I2 Test Circuit 5 Test Circuit 6 Figure 7
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.2_00 S-8264A/B/C Series Seiko Instruments Inc. 15 Operation Remark Refer to “ Battery Protection IC Connection Example”. 1. Overcharge Detection When the voltage of one of the batteries exceeds the overcharge detection voltage (VCU) during charging under normal conditions and the state is retained for the overcharge detection delay time (tCU) or longer, CO becomes “H”. This state is called overcharge. Connecting FET to the CO pin provides charge control and a second protection. In the S-8264A/C Series, if the voltage of each of the batteries is lower than V CU + the overcharge hysteresis voltage (VHC) and the state is retained for the overcharge release delay time (tCL) or longer, CO becomes “L”. In the S-8264B Series, if the voltage of each of the batteries is lower than VCU + VHC and the state is retained for tCL or longer, the overcharge state is released; however, CO stays at “H”. When the CTL pin is switched from “L” to “H”, CO becomes “L”. 2. Overcharge Timer Reset When an overcharge release noise that forces the voltage of one of the batteries temporarily below VCU is input during tCU from when V CU is exceeded to when charging is stopped, t CU is continuously counted if the time the overcharge release noise persists is shorter than the overcharge timer reset delay time (tTR). Under the same conditions, if the time the overcharge release noise persists is t TR or longer, counting of t CU is reset once. After that, when V CU has been exceeded, counting tCU resumes.
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) S-8264A/B/C Series Rev.4.2_00 Seiko Instruments Inc. 16 3. CTL Pin The S-8264A/B/C Series has a control pin. The CTL pin is used to control the output voltage of the CO pin. In the S-8264A/C Series, the CTL pin takes precedence over the overcharge detection circuit. In the S-8264B Series, when the CTL pin is switched from “L” to “H”, a reset signal is output to the overcharge detection latch and CO becomes “L”. Table 13 Control via CTL Pin CTL Pin CO Pin S-8264A Series S-8264B Series S-8264C Series “H” Normal state*1 Without latch Normal state*1 Open “H” Normal state*1 Normal state*1 “H” *1. The state is controlled by the overcharge detection circuit. *2. Latch reset becomes effective when the voltage of each of the batteries is lower than the overcharge detection voltage (V CU) + the overcharge hysteresis voltage (V HC) and the overcharge release delay time (t CL) has elapsed. S-8264A/B Series S-8264C Series *1. The reverse voltage “H” to “L” or “L” to “H” of CTL pin is VDD pin voltage − 2.8 V (Typ.), does not have the hysteresis. Figure 8 Internal Equivalent Circuit of CTL Pin Caution 1. In the S-8264A/B Series, since the CTL pin implements high resistance of 8 M Ω to 12 MΩ for pull down, be careful of external noise application. If an external noise is applied, CO may become “H”. Perform thorough evaluation using the actual application. 2. In the S-8264B Series, when the CTL pin is ope n or “L”, CO latches “H”. When the VDD pin voltage is decreased to the UVLO voltage of 2 V (Typ.) or lower, the latch is reset. Pull-up resistor CTL *1 + Pull-down resistor CTL *1
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.2_00 S-8264A/B/C Series Seiko Instruments Inc. 17 4. Test Mode In the S-8264A/B/C Series, the overcharge detection delay time (tCU) can be shortened by entering the test mode. The test mode can be set by retaining the VDD pin voltage 8.5 V or more higher than the SENSE pin voltage for at least 80 ms (V1 = V2 = V3 = V4 = 3.5 V, Ta = 25°C). The status is retained by the internal latch and the test mode is retained even if the VDD pin voltage is decreased to the same voltage as that of the SENSE pin. When CO becomes “H” when the delay time has elapsed afte r overcharge detection, the latch for retaining the test mode is reset and the S-8264A/B Series exits from the test mode. VCUn Pin voltage CO pin Test mode VDD pin voltage
8.5 V or
tTST = 80 ms max. SENSE pin voltage (n = 1 to 4) tCL *1. In the product tCU = 4 s Typ. during normal mode, tCU = 64 ms Typ. In the product t CU = 2 s Typ. during normal mode, tCU = 32 ms Typ. In the product tCU = 5.65 s Typ. during normal mode, tCU = 88 ms Typ. Figure 9 Caution 1. When the VDD pin voltage is decreased to lower than the UVLO voltage of 2 V (Typ.), the S-8264A/B/C Series returns to the normal mode. 2. Set the test mode when no batteries are overcharged. 3. The overcharge release delay time (t CL) is not shortened in the test mode. 4. The overcharge timer reset delay time (t TR) is not shortened in the test mode.
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.2_00 S-8264A/B/C Series Seiko Instruments Inc. 19 2. Overcharge Timer Reset Operation VCUn Battery voltage CO pin tCU VHCn tCU or shorter tTR tTR or shorter Timer reset tTR or shortertTR or longer (n = 1 to 4) Figure 12
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) S-8264A/B/C Series Rev.4.2_00 Seiko Instruments Inc. 20 Battery Protection IC Connection Example (1) 4-serial cell SC PROTECTOR EB− EB+ BAT1 BAT2 BAT3 BAT4 FET SENSE VC1 VC2 VC3 VSS CO VDD CTL CVDD RVDD External input*1 DP S-8264A/B/C Series RCTL Figure 13 *1. Refer to Table 13 for setting on external input. Table 14 Constants for External Components No. Part Min. Typ. Max. Unit 1 R1 to R4 0.1 1 10 kΩ 2 C1 to C4, C VDD 0.01 0.1 1 μF
3 R VDD 50 100 500 Ω
4 R CTL 0 100 500 Ω
Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1 to R4 and to C1 to C4 and C VDD. 4. Set R VDD, C1 to C4, and CVDD so that the condition (RVDD) × (C1 to C4, CVDD) ≥ 5 × 10−6 is satisfied. 5. Set R1 to R4, C1 to C4, and C VDD so that the condition (R1 to R4) × (C1 to C4, CVDD) ≥ 1 × 10−4 is satisfied. 6. Since “H” may be output at CO transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff.
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.2_00 S-8264A/B/C Series Seiko Instruments Inc. 21 (2) 3-serial cell SC PROTECTOR EB− EB+ BAT1 BAT2 BAT3 FET SENSE VC1 VC2 VC3 VSS CO VDD CTL CVDD RVDD External input*1 DP S-8264A/B/C Series RCTL Figure 14 *1. Refer to Table 13 for setting on external input. Table 15 Constants for External Components No. Part Min. Typ. Max. Unit 1 R1 to R3 0.1 1 10 kΩ 2 C1 to C3, C VDD 0.01 0.1 1 μF Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1 to R3 and to C1 to C3 and C VDD. 4. Set R VDD, C1 to C3, and CVDD so that the condition (RVDD) × (C1 to C3, CVDD) ≥ 5 × 10−6 is satisfied. 5. Set R1 to R3, C1 to C3, and C VDD so that the condition (R1 to R3) × (C1 to C3, CVDD) ≥ 1 × 10−4 is satisfied. 6. Since “H” may be output at CO transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff.
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) S-8264A/B/C Series Rev.4.2_00 Seiko Instruments Inc. 22 (3) 2-serial cell SC PROTECTOR EB− EB+ BAT1 BAT2 FET SENSE VC1 VC2 VC3 VSS CO VDD CTL CVDD RVDD External input*1 DP S-8264A/B/C Series RCTL Figure 15 *1. Refer to Table 13 for setting on external input. Table 16 Constants for External Components No. Part Min. Typ. Max. Unit 1 R1 and R2 0.1 1 10 kΩ 2 C1 and C2, C VDD 0.01 0.1 1 μF Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1 to R3 and to C1 to C3 and C VDD. 4. Set R VDD, C1 to C3, and CVDD so that the condition (RVDD) × (C1 to C3, CVDD) ≥ 5 × 10−6 is satisfied. 5. Set R1 to R3, C1 to C3, and C VDD so that the condition (R1 to R3) × (C1 to C3, CVDD) ≥ 1 × 10−4 is satisfied. 6. Since “H” may be output at CO transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff.
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.2_00 S-8264A/B/C Series Seiko Instruments Inc. 23 Precautions
- Do not connect batteries charged with V CU + VHC or more. If the connected batteries include a battery charged with VCU + VHC or more, “H” may be output at CO after all pins are connected.
- In some application circuits, even if an overcharged battery is not included, the order of connecting batteries may be restricted to prevent transient output of CO detection pulses when the ba tteries are connected. Perform thorough evaluation with the actual application circuit.
- In the S-8264B Series, “H” may be output at CO after all the pins are connected. In this case, set the CTL pin from “L” to “H”.
- Before the battery connection, short-circuit the battery side pins R VDD and R1, shown in the figure in “ Battery Protection IC Connection Example”.
- The application conditions for the inpu t voltage, output voltage, and load current should not exceed the package power dissipation.
- Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic protection circuit.
- SII claims no responsibility for any disputes arising out of or in connection with any infringement of patents owned by a third party by products including this IC.
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) S-8264A/B/C Series Rev.4.2_00 Seiko Instruments Inc. 24 Example of Application Circuit 1. Overheat Protection via PTC (S-8264A Series) SC PROTECTOR EB− EB+ BAT1 BAT2 BAT3 BAT4 FET SENSE VC1 VC2 VC3 VSS CO VDD CTL CVDD RVDD PTC DP CCTL S-8264A Series Figure 16 Cautions 1. The above connection example will not guarantee successful operation. Perform thorough evaluation using the actual application. 2. A pull-down resistor is included in the CTL pin. To perform overheat protection via the PTC in the S-8264A Series, connect the PTC before connecting batteries. 3. When the power fluctuation is large, connect the power supply of the PTC to the VDD pin of the S-8264A Series. 4. Since “H” may be output at CO transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff. [For SC PROTECTOR, contact] Device Sales Dept., Advanced Process Device Division, Dexerials Corporation Gate City Osaki East Tower 8F, 1-11-2 Osaki, Shinagawa-ku, Tokyo, 141-0032 Japan TEL +81-3-5435-3946 Contact Us: http://www.dexerials.jp/en/ [For PTC, contact] Murata Manufacturing Co., Ltd. Thermistor Products Department Nagaokakyo-shi, Kyoto 617-8555 Japan TEL +81-75-955-6863 Contact Us: http://www.murata.com/contact/index.html
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.2_00 S-8264A/B/C Series Seiko Instruments Inc. 25 Characteristics (Typical Data) 1. Detection Voltage vs. Temperature (1) Overcharge Detection Voltage vs. Temperature VCU = 4.3 V (2) Overcharge Release Voltage vs. Temperature VHC = 0.52 V VCU [V] 4.40 4.35 4.30 4.25 4.20 40 25 25 50 75 85 Ta [C] VCU − VHC [V] 3.90 3.85 3.80 3.75 3.70 40 25 25 50 75 85 Ta [C] 2. Current Consumption vs. Temperature (1) Current Consumption during Normal Operation vs. Temperature VDD = 14 V (2) Current Consumption during Overdischarge vs. Temperature VDD = 9.2 V IOPE [μA] 4.0 3.0 2.0 1.0 0.0 40 25 25 50 75 85 Ta [C] IOPED [μA] 4.0 3.0 2.0 1.0 0.0 40 25 25 50 75 85 Ta [C] 3. Delay Time vs. Temperature (1) Overcharge Detection Delay Time vs. Temperature VDD = 20 V (2) Overcharge Release Delay Time vs. Temperature VDD = 14 V tCU [s] 6.0 5.0 4.0 3.0 2.0 40 25 25 50 75 85 Ta [C] tCL [ms] 40 25 25 50 75 85 Ta [C]
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) S-8264A/B/C Series Rev.4.2_00 Seiko Instruments Inc. 26 4. Output Current vs. Temperature (1) CO Pin Sink Current vs. VDD Ta = 25 °C (2) CO Pin Source Current vs. VDD Ta = 25 °C ICOL [mA] 10.0 7.5 5.0 2.5 0.0 0 5 15 20 25 VDD [V] ICOH [μA] 1000 700 500 250 0 5 15 20 25 VDD [V] 5. CTL Pin vs. Temperature (1) CTL Pin Threshold Voltage vs. Temperature VDD = 14 V (2) CTL Pin Input Resistance vs. Temperature VDD = 14 V VTH.CTL [V] 12.0 11.5 11.0 10.5 10.0 40 25 25 50 75 85 Ta [C] RCTL [M] 14.0 12.0 10.0 8.0 6.0 40 25 25 50 75 85 Ta [C]
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.2_00 S-8264A/B/C Series Seiko Instruments Inc. 27 Marking Specifications (1) SNT-8A Top view 14 3 2 85 6 7 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (1) Blank (2) to (4) Product code (Refer to Product name vs. Product code) (5), (6) Blank (7) to (11) Lot number Product name vs. Product code (a) S-8264A Series (b) S-8264B Series Product name Product code Product name Product code S-8264AAA-I8T1U Q 5 A S-8264BAA-I8T1U Q 6 A S-8264AAB-I8T1U Q 5 B S-8264BAB-I8T1U Q 6 B S-8264AAC-I8T1U Q 5 C S-8264AAD-I8T1U Q 5 D (c) S-8264C Series S-8264AAE-I8T1U Q 5 E Product name Product code S-8264AAF-I8T1U Q 5 F (2) (3) (4) S-8264AAG-I8T1U Q 5 G S-8264CAA-I8T1U Q 7 A S-8264AAH-I8T1U Q 5 H S-8264CAB-I8T1U Q 7 B S-8264AAI-I8T1U Q 5 I S-8264AAJ-I8T1U Q 5 J S-8264AAK-I8T1U Q 5 K S-8264AAO-I8T1U Q 5 O S-8264AAS-I8T1U Q 5 S S-8264AAT-I8T1U Q 5 T (2) 8-Pin TSSOP Top view (1) (2) (3) (4) (5) (6) (7) (8) (1) to (5) Product name: S8264 (Fixed) (6) to (8) Function code (9) to (14) Lot number Product name vs. Function code (a) S-8264A Series (b) S-8264B Series Product name Product code Product name Product code S-8264AAA-T8T1x A A A S-8264BAB-T8T1x B A B S-8264AAB-T8T1x A A B S-8264AAK-T8T1U A A K Remark 1. x: G or U 2. Please select products of environmental code = U for Sn 100%, halogen-free products.
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