S8249

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www.sii-ic.com VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION © SII Semiconductor Corporation, 2015-2017 Rev.1.4_00 The S-8249 Series is a voltage monitoring IC with a ce ll balancing function and includes a high-accuracy voltage detection circuit and a delay circuit. The S-8249 Series is suitable for cell balancing and ov ercharge protection of batteries and capacitors.  Features

• High-accuracy voltage detection circuit Cell balancing detection voltage: 2.0 V to 4.6 V (5 mV step) Accuracy ±12 mV (2.0 V ≤ VBU < 2.4 V) Accuracy ±0.5% (2.4 V ≤ VBU ≤ 4.6 V) Cell balancing release voltage: 2.0 V to 4.6 V *1 Accuracy ±24 mV (2.0 V ≤ VBL < 2.4 V) Accuracy ±1.0% (2.4 V ≤ VBL ≤ 4.6 V) Overcharge detection voltage: 2.0 V to 4.6 V (5 mV step) Accuracy ±12 mV (2.0 V ≤ VCU < 2.4 V) Accuracy ±0.5% (2.4 V ≤ VCU ≤ 4.6 V) Overcharge release voltage: 2.0 V to 4.6 V *2 Accuracy ±24 mV (2.0 V ≤ VCL < 2.4 V) Accuracy ±1.0% (2.4 V ≤ VCL ≤ 4.6 V)
• Built-in Nch transistor with ON resistance of 5 Ω typ. between the CB pin and the VSS pin
• Current consumption: 2.0 μA max. (Ta = +25°C)
• Delay times are generated only by an internal circuit (External capac itors are unnecessary).
• CO pin output form and output logic are selectable: CMOS output Active "H", active "L" Nch open-drain output Active "H", active "L"
• Switchable to power-saving mode by using the CE pin
• Operation temperature range: Ta = −40°C to +85°C
• Lead-free (Sn 100%), halogen-free *1. Cell balancing release voltage = Cell balancing detection voltage − Cell balancing hysteresis voltage (Cell balancing hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.7 V in 50 mV step.) *2. Overcharge release voltage = Overcharge detection voltage − Overcharge hysteresis voltage (Overcharge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.7 V in 50 mV step.)  Applications
• Rechargeable battery module
• Capacitor module  Package
• SOT-23-6

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION S-8249 Series Rev.1.4_00  Block Diagram CE CO VDD VSS DP 1 MΩ 1 MΩ CB Control circuit Delay circuit − Power-saving mode switching circuit *1. All diodes shown in the figure are parasitic diodes. Figure 1

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.4_00 S-8249 Series  Product Name Structure 1. Product name S-8249A xx - M6T1 U Serial code Sequentially set from AA to ZZ Environmental code U: Lead-free (Sn 100%), halogen-free Package abbreviation and IC packing specifications*1 M6T1: SOT-23-6, Tape *1. Refer to the tape drawing. 2. Package Table 1 Package Drawing Codes Package Name Dimension Tape Reel SOT-23-6 MP006-A-P-SD MP006-A-C-SD MP006-A-R-SD 3. Product name list Table 2 (2 / 1) Product Name Cell Balancing Detection Voltage [VBU] Cell Balancing Release Voltage [VBL] Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] CO Pin Output Form CO Pin Output Logic Combination of Delay Time S-8249AAA-M6T1U 2.600 V 2.600 V 2.750 V 2.750 V CMOS output Active "H" (1) S-8249AAB-M6T1U 3.000 V 3.000 V 3.150 V 3.150 V CMOS output Active "H" (1) S-8249AAC-M6T1U 3.000 V 3.000 V 3.200 V 3.200 V CMOS output Active "H" (1) S-8249AAD-M6T1U 3.100 V 3.100 V 3.250 V 3.250 V CMOS output Active "H" (1) S-8249AAE-M6T1U 3.100 V 3.100 V 3.300 V 3.300 V CMOS output Active "H" (1) S-8249AAF-M6T1U 2.600 V 2.600 V 2.800 V 2.800 V CMOS output Active "H" (1) S-8249AAG-M6T1U 2.400 V 2.400 V 2.900 V 2.900 V CMOS output Active "H" (1) S-8249AAH-M6T1U 2.400 V 2.400 V 3.000 V 3.000 V CMOS output Active "H" (1) S-8249AAI-M6T1U 2.100 V 2.100 V 3.000 V 3.000 V CMOS output Active "H" (1) S-8249AAK-M6T1U 2.400 V 2.400 V 3.200 V 3.200 V CMOS output Active "H" (1) S-8249AAL-M6T1U 2.100 V 2.000 V 3.200 V 3.200 V CMOS output Active "H" (1) S-8249AAM-M6T1U 2.620 V 2.520 V 2.800 V 2.700 V CMOS output Active "H" (1) S-8249AAN-M6T1U 3.300 V 3.300 V 4.080 V 3.930 V CMOS output Active "H" (1) S-8249AAO-M6T1U 2.000 V 2.000 V 3.000 V 3.000 V CMOS output Active "H" (1) S-8249AAP-M6T1U 3.700 V 3.700 V 4.500 V 4.500 V CMOS output Active "H" (1) S-8249AAQ-M6T1U 3.800 V 3.800 V 4.080 V 3.930 V CMOS output Active "H" (1) S-8249AAR-M6T1U 2.800 V 2.800 V 3.150 V 3.150 V CMOS output Active "H" (1) S-8249AAS-M6T1U 2.800 V 2.800 V 3.200 V 3.200 V CMOS output Active "H" (1) S-8249AAT-M6T1U 2.800 V 2.800 V 3.100 V 3.100 V CMOS output Active "H" (1) S-8249AAU-M6T1U 2.500 V 2.400 V 3.800 V 3.700 V CMOS output Active "H" (1) S-8249AAV-M6T1U 2.300 V 2.200 V 3.800 V 3.700 V CMOS output Active "H" (1) S-8249AAW-M6T1U 2.650 V 2.600 V 2.750 V 2.650 V Nch open-drain output Active "L" (1) S-8249AAY-M6T1U 4.150 V 4.150 V 4.275 V 4.275 V CMOS output Active "H" (2)

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION S-8249 Series Rev.1.4_00 Table 2 (2 / 2) Product Name Cell Balancing Detection Voltage [VBU] Cell Balancing Release Voltage [VBL] Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] CO Pin Output Form CO Pin Output Logic Combination of Delay Time S-8249ABA-M6T1U 3.650 V 3.550 V 3.800 V 3.500 V CMOS output Active "L" (3) S-8249ABB-M6T1U 4.350 V 4.350 V 4.425 V 4.325 V CMOS output Active "L" (3) S-8249ABC-M6T1U 4.200 V 4.200 V 4.300 V 4.200 V CMOS output Active "L" (4) Remark 1. Contact our sales office for the products with detec tion voltage values other than those specified above. 2. Set V CU > V BU. 3. Refer to Table 3 for details about combinations of delay times. Table 3 Combination of Delay Time Cell Balancing Detection Delay Time [tBU] Cell Balancing Release Delay Time [tBL] Overcharge Detection Delay Time [tCU] Overcharge Release Delay Time [tCL] (1) 128 ms 1.0 ms 128 ms 1.0 ms (2) 128 ms 1.0 ms 1024 ms 1.0 ms (3) 64 ms 2.0 ms 256 ms 2.0 ms (4) 64 ms 2.0 ms 256 ms 1.0 ms Remark The delay times can be changed within the ranges listed above. For details, please contact our sales office. Table 4 Delay Time Symbol Selection Range Remark Cell balancing detection delay time *1 tBU 64 ms 128 ms*2 256 ms 512 ms 1024 ms Select a value from the left. Cell balancing release delay time t BL 0.5 ms 1.0 ms *2 2.0 ms Select a value from the left. Overcharge detection delay time *1 tCU 64 ms 128 ms*2 256 ms 512 ms 1024 ms Select a value from the left. Overcharge release delay time t CL 0.5 ms 1.0 ms *2 2.0 ms Select a value from the left. *1. Set t CU ≥ tBU. *2. The value is the delay ti me of the standard products.

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.4_00 S-8249 Series  Pin Configuration 1. SOT-23-6 Table 5 13 2 546 Top view Figure 2 Pin No. Symbol Description

1 CO Output pin for overcharge signal

2 VSS Input pin for negative power supply

"H": Test mode (used to shorten the delay time) "L": Normal operation mode 4 CE Power-saving mode switching pin "H": Power-saving mode "L": Normal operation mode

5 VDD Input pin for positive power supply

6 CB Output pin for cell balancing signal

(Nch open-drain output)

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION S-8249 Series Rev.1.4_00  Absolute Maximum Ratings Table 6 (Ta = +25°C unless otherwise specified) Item Symbol Applied Pin Absolute Maximum Rating Unit Input voltage between VDD pin and VSS pin VDS VDD VSS − 0.3 to V SS + 6.0 V Input pin voltage VIN CE , DP VSS − 0.3 to V DD + 0.3 ≤ VSS + 6.0 V Output pin voltage VOUT CO, CB V SS − 0.3 to V DD + 0.3 ≤ VSS + 6.0 V Output pin current ICB CB 100 ( −40°C to +85°C) mA Operation ambient temperature T opr − −40 to +85 °C Storage temperature Tstg − −55 to +125 °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions.  Thermal Resistance Value Table 7 Item Symbol Condition Min. Typ. Max. Unit Junction-to-ambient thermal resistance *1 θJA SOT-23-6 Board A − 159 − °C/W Board B − 124 − °C/W Board C − − − °C/W Board D − − − °C/W Board E − − − °C/W *1. Test environment: compliance with JEDEC STANDARD JESD51-2A Remark Refer to " Power Dissipation" and "Test Board" for details.

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.4_00 S-8249 Series  Electrical Characteristics For details about the test circuits and testing method, refer to "  Test Circuit". Caution Unless otherwise specified in Table 8, set V2 = V3 = 0 V, and SWn (n = 1 to 4) = OFF. Table 8 (1 / 2) (Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Detection voltage Cell balancing detection voltage VBU SW1 = ON 2.0 V ≤ VBU < 2.4 V VBU −

0.012 VBU VBU +

0.012 V 2.4 V ≤ VBU ≤ 4.6 V VBU ×

0.995 VBU VBU ×

1.005 V Cell balancing release voltage VBL SW1 = ON 2.0 V ≤ VBL < 2.4 V VBL −

0.024 VBL VBL +

0.024 V 2.4 V ≤ VBL ≤ 4.6 V VBL ×

0.99 VBL VBL ×

1.01 V Overcharge detection voltage VCU 2.0 V ≤ VCU < 2.4 V VCU −

0.012 VCU VCU +

0.012 V 2.4 V ≤ VCU ≤ 4.6 V VCU ×

0.995 VCU VCU ×

1.005 V Overcharge release voltage VCL 2.0 V ≤ VCL < 2.4 V VCL −

0.024 VCL VCL +

0.024 V 2.4 V ≤ VCL ≤ 4.6 V VCL ×

0.99 VCL VCL ×

1.01 V Temperature coefficient Detection voltage temperature coefficient 1 *1 ΔVBU ΔTa • VBU Ta = −40°C to +85°C *3 − 100 350 ppm/ Detection voltage temperature coefficient 2 *2 ΔVCU ΔTa • VCU Ta = −40°C to +85°C *3 − 100 350 ppm/ Input voltage Operation voltage between VDD pin and VSS pin VDS Voltages output from CO pin and CB pin are fixed 1.5 − 5.0 V CE pin voltage "H" VCE H − − − VDD × 0.9 V CE pin voltage "L" VCE L − VDD × 0.1 − − V DP pin voltage "H" V DPH − − − VDD × 0.9 V DP pin voltage "L" V DPL − VDD × 0.1 − − V Input current Current consumption during operation IOPE I VDD when V1 = V BL − 0.1 V − 1.2 2.0 μA Current consumption during power-saving IPSV I VDD when V1 = V2 = V BL − 0.1 V − − 0.1 μA *1. A change in the temperature of the detection voltage [m V/°C] is calculated by using the following equation. ΔVBU ΔTa []mV/°C = V BU []V × ΔVBU ΔTa • VBU []ppm/°C ÷ 1000 *2. A change in the temperature of the detection voltage [m V/°C] is calculated by using the following equation. ΔVCU ΔTa []mV/°C = V CU []V × ΔVCU ΔTa • VCU []ppm/°C ÷ 1000 *3. Since products are not screened at high and low temperat ure, the specification for this temperature range is guaranteed by design, not tested in production. Remark 1. ΔVBU ΔTa , ΔVCU ΔTa : Change in temperature of detection voltage 2. V BU, VCU: Set detection voltage 3. ΔVBU ΔTa • VBU , ΔVCU ΔTa • VCU : Detection voltage temperature coefficient

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION S-8249 Series Rev.1.4_00 Table 8 (2 / 2) (Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Delay time Cell balancing detection delay time tBU − tBU × 0.8 tBU tBU × 1.2 ms Cell balancing release delay time tBL − tBL × 0.8 tBL tBL × 1.2 ms Overcharge detection delay time tCU − tCU × 0.8 tCU tCU × 1.2 ms Overcharge release delay time tCL − tCL × 0.8 tCL tCL × 1.2 ms Output current CB pin output current CB pin sink current I CBS V1 = V BU + 0.1 V, SW2 = ON, V4 = 0.5 V 30 − − mA CB pin leakage current I CBL V1 = V BL − 0.1 V, SW2 = ON, V4 = 6.0 V − − 0.1 μA CO pin output current (output form: CM OS output, output logic: active "H") CO pin sink current I COL V1 = V CL − 0.1 V, SW4 = ON, V5 = 0.5 V 5.0 − − mA CO pin source current I COH V1 = V CU + 0.1 V, SW4 = ON, V5 = V1 − 0.5 V 1.0 − − mA CO pin output current (output form: CMOS output, output logic: active "L") CO pin sink current I COL V1 = V CU + 0.1 V, SW4 = ON, V5 = 0.5 V 5.0 − − mA CO pin source current I COH V1 = V CL − 0.1 V, SW4 = ON, V5 = V1 − 0.5 V 1.0 − − mA CO pin output current (output form: Nch open-drain output, output logic: active "H") CO pin sink current I COL V1 = V CL − 0.1 V, SW4 = ON, V5 = 0.5 V 5.0 − − mA CO pin leakage current I COHL V1 = V CU + 0.1 V, SW4 = ON, V5 = 6.0 V − − 0.1 μA CO pin output current (output form: Nch open-drain output, output logic: active "L") CO pin sink current I COL V1 = V CU + 0.1 V, SW4 = ON, V5 = 0.5 V 5.0 − − mA CO pin leakage current I COHL V1 = V CL − 0.1 V, SW4 = ON, V5 = 6.0 V − − 0.1 μA

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.4_00 S-8249 Series  Test Circuit S-8249 Series VDD VSS DP CE CO CB A A A RCB = 100 kΩ R CO = 100 kΩ V2 V3 V4 V5 SW1 SW2 SW4 SW3 IVDD ICB ICO Figure 3 Caution Unless otherwise specified in Table 8, set V2 = V3 = 0 V, and SWn (n = 1 to 4) = OFF. 1. CE pin voltage "H" CE pin voltage "H" (V CE H) is defined as the voltage at which I VDD is changed from I OPE to IPSV when V2 is increased from 0 V after setting V1 = V BL − 0.1 V. 2. CE pin voltage "L" CE pin voltage "L" (V CE L) is defined as the voltage at which I VDD is changed from I PSV to IOPE when V2 is decreased from V BL − 0.1 V after setting V1 = V2 = V BL − 0.1 V. 3. DP pin voltage "H" *1 DP pin voltage "H" (V DPH ) is defined as the voltage at which the test mode is switched when V3 is increased from 0 V after setting V1 = V BL − 0.1 V. 4. DP pin voltage "L" *1 DP pin voltage "L" (V DPL ) is defined as the voltage at which the normal operation mode is switched when V3 is decreased from V BL − 0.1 V after setting V1 = V3 = V BL − 0.1 V. 5. Cell balancing detection delay time Cell balancing detection delay time (t BU) is defined as the time from when SW1 is set to ON and V1 is set to V BU − 0.1 V to when the CB pin output is inverted after setting V1 to V BU + 0.1 V. 6. Cell balancing release delay time Cell balancing release delay time (t BL) is defined as the time from when SW 1 is set to ON and V1 is set to V BL + 0.1 V to when the CB pin output is inverted after setting V1 to V BL − 0.1 V. 7. Overcharge detection delay time Overcharge detection delay time (t CU) is defined as the time from when SW 1 is set to ON and V1 is set to V CU − 0.1 V to when the CO pin output is inverted after setting V1 to V CU + 0.1 V. 8. Overcharge release delay time Overcharge release delay time (t CL) is defined as the time from when SW1 is set to ON and V1 is set to V CL + 0.1 V to when the CO pin output is inverted after setting V1 to V CL − 0.1 V. *1. For details about switching to the test mode by using the DP pin, refer to " 5. DP pin " in "  Operation ".

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION S-8249 Series Rev.1.4_00  Standard Circuit VDD CB VSS CO CE S-8249 Series RVDD CVDD RCB DP Figure 4 Table 9 Constants for External Components Symbol Part Purpose Min. Typ. Max. Remark RVDD Resistor ESD protection, for power fluctuation control 150 Ω 330 Ω 1.0 k Ω Resistance should be as small as possible to avoid worsening the overcharge detection accuracy due to current consumption. CVDD Capacitor For power fluctuation control 0.068 μF0 . 1 μF1 . 0 μF Connect a capacitor of 0.068 μF or more between VDD pin and VSS pin. RCB Resistor For setting the cell balancing current value − − − Set the required cell balancing current value depending on " 2. Cell balancing status " in " Operation ".*2 *1. When connecting a resistor less than 150 Ω to RVDD or a capacitor less than 0.068 μF to CVDD , the S-8249 Series may malfunction when power is largely fluctuated. *2. Set the cell balancing current value so that R CB does not exceed the power dissipation. Cautions 1. The above constants may be changed without notice. 2. The example of connection shown above and the constant do not guarantee proper operation. Perform thorough evaluation using the actual application to set the constant.

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.4_00 S-8249 Series  Operation Remark Refer to " Standard Circuit ". 1. Normal status In the S-8249 Series, if the voltage between the VDD pin and the VSS pin (V DS) has not reached the cell balancing detection voltage (V BU), the CB pin output is in the high-i mpedance status. The CO pin output status varies according to the output form and output logic selected, as shown in Table 10 . This is the normal status. Table 10 CO Pin Output Form and Output Logic CB Pin Output CO Pin Output CMOS output, active "H" "H" "L" CMOS output, active "L" "H" "H" Nch open-drain output, active "H" "H" "L" Nch open-drain output, active "L" "H" "H" 2. Cell balancing status In the S-8249 Series, if V DS is V BU or higher and this status continues for the cell balancing detection delay time (tBU) or longer, the CB pin output becomes "L ". This is the cell balancing status. The cell balancing status is released when V DS drops to the cell balancing release voltage (V BL) or lower and this status continues for the cell balancing release delay time (t BL) or longer. The S-8249 Series includes an Nch transistor with ON resistance of 5 Ω typ. (R CBON ) between the CB pin and the VSS pin, thus causing the cell balancing current (I CB) to flow in cell balancing status, and the cell balancing operation to start. By connecting a resistor (R CB) to the CB pin, I CB in cell balancing status can be calculated by using the following equation. ICB = V BU / (R CBON + RCB) CB RCB VSS VDD S-8249 Series ICB RCBON = 5 Ω typ. Control circuit Figure 5

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION S-8249 Series Rev.1.4_00 3. Overcharge status In the S-8249 Series, if V DS is the overcharge detection voltage (V CU) or higher and this status continues for the overcharge detection delay time (t CU) or longer, the CO pin output is inve rted. The CO pin output status varies according to the output form and output logic selected, as shown in Table 11 . This is the overcharge status. In the overcharge status, the CB pin output becomes "L". Table 11 CO Pin Output Form and Output Logic CB Pin Output CO Pin Output CMOS output, active "H" "L" "H" CMOS output, active "L" "L" "L" Nch open-drain output, active "H" "L" "H" Nch open-drain output, active "L" "L" "L" The overcharge status is released when V DS drops to the overcharge release voltage (V CL) or lower and this status continues for the overcharge release delay time (t CL) or longer. 4. CE pin The S-8249 Series has the CE pin (Power-saving mode switching pin). The S-8249 Series is set to power-saving mode by inputting a voltage of V CE H or higher to the CE pin. Table 12 CE Pin Status Open (V CE = V SS) Normal operation mode "H" (V CE ≥ VCE H) Power-saving mode "L" (V CE ≤ VCE L) Normal operation mode In power-saving mode, the current consumption is dec reased to current consumption during power-saving (I PSV ). The CB pin or the CO pin output in power-saving mode is the same as that in the normal status. The CE pin is pulled down to V SS by the internal resistor. When in a mode other than power-saving mode, leave the CE pin open or short it with V SS.

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.4_00 S-8249 Series 5. DP pin The S-8249 Series has the DP pin (Test mode switching pi n). The S-8249 Series is set to test mode (used to shorten the delay time) by inputting a voltage of V DPH or higher to the DP pin. Table 13 DP Pin Status Open (V DP = V SS) Normal operation mode "H" (V DP ≥ VDPH ) Test mode "L" (V DP ≤ VDPL ) Normal operation mode In test mode, the cell balancing detection delay time (t BU) and overcharge detection delay time (t CU) are shortened to 1/64 of the delay time in the normal operation mode. The DP pin is pulled down to V SS by the internal resistor. When in a mode other than test mode, leave the DP pin open or short it with V SS.

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION S-8249 Series Rev.1.4_00  Timing Chart VSS VDD VSS (1) VCU VBL (VBU − VHB) VBU VDD VSS Overcharge release delay time (tCL) tBL (2) tBU Overcharge detection delay time (tCU) VCB VCL (VCU − VHC) Battery voltage CB pin voltage CO pin voltage (Active "H") CO pin voltage (Active "L") Status*2 Charger connection Cell balancing release delay time (tBL) Cell balancing detection delay time (tBU) *1. The CB pin is pulled up by the external resistor. *2. (1): Normal status (2): Cell balancing status (3): Overcharge status Remark The charger is assumed to ch arge with a constant current. Figure 6

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.4_00 S-8249 Series  Precautions

• The application conditions for the input voltage, output voltage, and load current should not exceed the power dissipation.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit.
• SII Semiconductor Corporation claims no responsibility for any and all disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party.

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION S-8249 Series Rev.1.4_00  Characteristics (Typical Data) 1. Current consumption 1. 1 I OPE vs. Ta VDD = V BL − 0.1 V 1. 2 I PSV vs. Ta VDD = V BL − 0.1 V 8540 2 50 2 55 07 5 0.00 2.50 Ta [C] 2.00 1.50 1.00 0.50 IOPE [A] 0.00 0.10 Ta [C] 0.08 0.06 0.04 0.02 IPSV [A] 8540 25 0 25 50 75 1. 3 I OPE vs. V DD 4.00 0.00 VDD [V] 3.00 2.00 1.00 IOPE [A] 2. Cell balancing detection / release voltage, overcharge detection / release voltage and delay times 2. 1 V BU vs. Ta 2. 2 V BL vs. Ta Ta [C] VBU [V] 2.62 2.58 2.61 2.60 2.59 8540 2 50 2 55 07 5 Ta [C] VBL [V] 2.64 2.56 2.62 2.60 2.58 8540 2 50 2 55 07 5 2. 3 V CU vs. Ta 2. 4 V CL vs. Ta Ta [C] VCU [V] 2.77 2.73 2.76 2.75 2.74 8540 2 50 2 55 07 5 Ta [C] VCL [V] 2.79 2.71 2.77 2.75 2.73 8540 2 50 2 55 07 5

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.4_00 S-8249 Series 2. 5 t BU vs. Ta 2. 6 t BL vs. Ta 100 160 Ta [C] tBU [ms] 140 120 8540 2 50 2 55 07 5 0.8 1.2 Ta [C] tBL [ms] 1.1 1.0 0.9 8540 2 50 2 55 07 5 2. 7 t CU vs. Ta 2. 8 t CL vs. Ta 100 160 Ta [C] tCU [ms] 140 120 8540 2 50 2 55 07 5 0.8 1.2 Ta [C] tCL [ms] 1.1 1.0 0.9 8540 2 50 2 55 07 5 3. Output current 3. 1 I CBH vs. V CB 3. 2 I CBL vs. V CB Ta = +25°C, V DD = V BL − 0.1 V Ta = +25°C, V DD = V BU + 0.1 V 0.10 0.00 VCB [V] ICBH [A] 0.08 0.06 0.04 0.02 400 VCB [V] 300 200 100 ICBL [mA] 3. 3 I COH vs. V CO 3. 4 I COL vs. V CO Ta = +25°C, V DD = V CU + 0.1 V Ta = +25°C, V DD = V CL − 0.1 V 8.0 0.0 0.0 3.0 ICOH [mA] VCO [V] 6.0 4.0 2.0 40.0 0.0 0.0 3.0 ICOL [mA] VCO [V] 30.0 20.0 10.0

VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION S-8249 Series Rev.1.4_00  Power Dissipation 0 25 50 75 100 125 150 1750.0 0.2 0.4 0.6 0.8 1.0 Ambient temperature (Ta) [C] Power dissipation (PD) [W] Tj = 125C max. SOT-23-6 B A Board Power Dissipation (P D) A 0.63 W B 0.81 W C − D − E −

(1) (2) Board A Item Specification Size [mm] 114.3 x 76.2 x t1.6 Material FR-4 Number of copper foil layer 2 Copper foil layer [mm] Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.070 74.2 x 74.2 x t0.070 Thermal via - Board B Item Specification Size [mm] 114.3 x 76.2 x t1.6 Thermal via - Material FR-4 Number of copper foil layer 4 Copper foil layer [mm] Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.035 IC Mount Area SOT-23-3/5/6 Test Board No. SOT23x-A-Board-SD-1.0 SII Semiconductor Corporation

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