S8243A

S8243A SII | Alldatasheet

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www.sii-ic.com BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK © Seiko Instruments Inc., 2002-2010 Rev.3.0_00 Seiko Instruments Inc. 1 The S-8243A/B Series is a protection IC for lithium-ion rechargeable battery. The S-8243A Series protects 3-series, the S-8243B Series protects 4-series cell pack from the overcharge, overdischarge, overcurrent voltages. This IC has a high-accuracy battery protection circuit and a battery monitor amplifier, and also a voltage regulator which operates the microcomputer or gas gauge IC. Combining this IC and a microcomputer or a gas gauge IC allows to display the amount of charge remained in a battery. „ Features (1) High-accuracy voltage detection for each cell

• Overcharge detection voltage n (n = 1 to 4) 3.9 V to 4.4 V (50 mV step) Accuracy ±25 mV
• Hysteresis voltage n (n = 1 to 4) of overcharge detection −0.10 V to −0.40 V (50 mV step) or 0 V Accuracy ±50 mV (Overcharge release voltage n (= Overcharge detection voltage n + Hysteresis voltage n) can be selected within the range 3.8 V to 4.4 V.)
• Overdischarge detection voltage n (n = 1 to 4) 2.0 V to 3.0 V (100 mV step) Accuracy ±80 mV
• Hysteresis voltage n (n = 1 to 4) of overdischarge detection 0.15 V to 0.70 V or 0 V (50 mV step) Accuracy ±100 mV (Overdischarge release voltage n (= Overdischarge detection voltage n + Hysteresis voltage n) can be selected within the range 2.0 V to 3.4 V.) (2) Three-level overcurrent protection including protection for short-circuiting
• Overcurrent detection voltage 1 0.05 V to 0.3 V (50 mV step) Accuracy ±25 mV
• Overcurrent detection voltage 2 0.5 V Accuracy ±100 mV
• Overcurrent detection voltage 3 V DD / 2 Accuracy ±15 % (3) Delay times for overcharge detection, overdischarge det ection and overcurrent detection 1 can be set by external capacitors. (Delay times for overcurrent detection 2 and 3 are fixed internally.) (4) Charge/discharge operation can be c ontrolled through the control pins. (5) High-accuracy battery monitor amp GAMP = VBATTERY × 0.2 ±1.0% (6) Voltage regulator VOUT = 3.3 V ±2.4 % (3 mA max.) (7) High input-voltage device Absolute maximum rating: 26 V (8) Wide operating voltage range 6 V to 18 V (9) Wide operating temperature range: −40°C to +85°C (10) Low current consumption
• Operation mode 120 μA max.
• Power down mode 0.1 μA max. (11) Lead-free, Sn 100%, halogen-free *1 *1. Refer to “ „ Product Name Structure” for details. „ Applications
• Lithium-ion rechargeable battery packs
• Lithium polymer rechargeable battery packs „ Package
• 16-Pin TSSOP

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 2 „ Block Diagrams 1. S-8243A Series Battery protection VC3 VC2 VC1 VDD DOP COP VMP VREG VBATOUT 200 nA CTL1 CTL2 CTL3 1.4 MΩ 1.4 MΩ 1 MΩ 1 MΩ 5 MΩ 5 MΩ CTL4 VREG VREG VREG Delay control RVCM,RVSM DOP,COP, Delay Delay Delay Battery monitor amp Voltage regulator 1.4 MΩ 1.4 MΩ 1.4 MΩ 1.4 MΩ 660 kΩ 660 kΩ 440 kΩ CCT VSS CDT Battery selection Remark1. Diodes in the figure are parasitic diodes. 2. Numerical values are typical values. Figure 1

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK Rev.3.0_00 S-8243A/B Series Seiko Instruments Inc. 3 2. S-8243B Series Battery protection VC3 VC2 VC1 VDD DOP COP VMP VREG VBATOUT 200 nA CTL1 CTL2 CTL3 1.4 MΩ 1.4 MΩ 1 MΩ 1 MΩ 5 MΩ 5 MΩ CTL4 VREG VREG VREG Delay control RVCM, RVSM DOP, COP, Delay Delay Delay Battery monitor amp Voltage regulator 1.4 MΩ 1.4 MΩ 1.4 MΩ 1.4 MΩ 660 kΩ 660 kΩ 440 kΩ CCT VSS CDT Battery selection Remark1. Diodes in the figure are parasitic diodes. 2. Numerical values are typical values. Figure 2

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 4 „ Product Name Structure 1. Product Name S-8243 x xx FT - TB − x Environmental code U : Lead-free (Sn 100%), halogen-free G : Lead-free (for details, please contact our sales office) IC direction in tape specifications*1 Package name (abbreviation) FT: 16-Pin TSSOP Serial code*2 Sequentially set from AA to ZZ Product series name A : 3-cell B : 4-cell *1. Refer to the tape specifications at the end of this book. *2. Refer to the “3. Product Name List”. 2. Package Drawing Code Package Name Package Tape Reel Environmental code = G FT016-A-P- SD FT016-A-C-SD FT016-A-R-SD 16-Pin TSSOP Environmental code = U FT016-A-P- SD FT016-A-C-SD FT016-A-R-S1 3. Product Name List Table 1 S-8243A Series (For 3-Serial Cell) Product name / Item Overcharge detection voltage [VCU] Hysteresis voltage for overcharge detection [VHC] Overdischarge detection voltage [VDL] Hysteresis voltage for overdischarge detection [VHD] Overcurrent detection voltage1 [VIOV1]

0 V battery

Table 2 S-8243B Series (For 4-Serial Cell) Product name / Item Overcharge detection voltage [VCU] Hysteresis voltage for overcharge detection [VHC] Overdischarge detection voltage [VDL] Hysteresis voltage for overdischarge detection [VHD] Overcurrent detection voltage1 [VIOV1] Remark 1. Change in the detection voltage is available in products other than listed above. Contact our sales office. 2. x: G or U 3. Please select products of environmental code = U for Sn 100%, halogen-free products.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK Rev.3.0_00 S-8243A/B Series Seiko Instruments Inc. 5 „ Pin Configuration 16-Pin TSSOP Top view VDD DOP COP VMP VC1 VC2 VC3 VSS VREG CTL1 CTL2 CTL3 CTL4 VBATOUT CCT CDT Figure 3 Table 3 Pin description (S-8243A Series) Pin No. Symbol Description

1 VDD Input pin for positive power supply, Connection pin for battery 1’s positive voltage

2 DOP Connection pin for discharge control FET gate (CMOS output)

3 COP Connection pin for charge cont rol FET gate (Nch open drain output)

4 VMP Pin for voltage detection between VDD-VM P pin (Pin for overcurrent detection)

5 VC1 No connection

6 VC2 Connection pin for battery 1’s negative voltage, for battery 2’s positive voltage

7 VC3 Connection pin for battery 2’s negative voltage, for battery 3’s positive voltage

8 VSS Input pin for negative power supply, Connection pin for battery 3’s negative voltage

9 CDT Connection pin to capacitor for overdischarge detection delay, for overcurrent detection delay 1

10 CCT Connection pin to capacitor for overcharge detection delay

11 VBATOUT Output pin for battery voltage and offset voltage

12 CTL4 Pin for selecting output from VBATOUT pin

13 CTL3 Pin for selecting output from VBATOUT pin

14 CTL2 Control pin for charge / discharge FET

15 CTL1 Control pin for charge / discharge FET

16 VREG Output pin for voltage regulator (3.3 V) Table 4 Pin description (S-8243B Series) Pin No. Symbol Description

3 COP Connection pin for charge control FET gate (Nch open drain output)

4 VMP Pin for voltage detection between VDD-VMP pin (Pin for overcurrent detection)

5 VC1 Connection pin for battery 1’s negative voltage, for battery 2’s positive voltage

6 VC2 Connection pin for battery 2’s negative voltage, for battery 3’s positive voltage

7 VC3 Connection pin for battery 3’s negative voltage, for battery 4’s positive voltage

8 VSS Input pin for negative power supply, Connection pin for battery 4’s negative voltage

16 VREG Output pin for voltage regulator (3.3 V)

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 6 „ Absolute Maximum Ratings Table 5 (Ta = 25°C unless otherwise specified) Item Symbol Applied Pins Absolute Maximum Ratings Unit Input voltage VDD VDS − V SS−0.3 to VSS+26 V Input voltage VIN VC1, VC2, VC3, CCT, CDT VSS−0.3 to VDD+0.3 V VMP pin Input voltage VMP VMP V SS−0.3 to VSS+26 V DOP pin output voltage VDOP DOP V SS−0.3 to VDD+0.3 V COP pin output voltage VCOP COP V SS−0.3 to VSS+26 V VREG pin output voltage V OUT VREG V SS−0.3 to VDD+0.3 V CTL1 pin input voltage VCTL1 CTL1 V SS−0.3 to VDD+0.3 V CTL2 to CTL4 pin input voltage V CTLn CTL2, CTL3, CTL4 VSS−0.3 to VOUT+0.3 V Cell voltage output voltage V BATOUT VBATOUT V SS−0.3 to VOUT+0.3 V − 300 (When not mounted on board) mW Power dissipation PD − 1100*1 mW Operation ambient temperature T opr − −40 to +85 °C Storage temperature Tstg − −40 to +125 °C *1. When mounted on board [Mounted board] (1) Board size : 114.3 mm × 76.2 mm × t1.6 mm (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated valu es exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 0 50 100 150 800 400 Power Dissipation (PD) [mW] Ambient Temperature (Ta) [°C] 1000 600 200 1200 Figure 4 Power Dissipation of Package (When Mounted on Board)

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK Rev.3.0_00 S-8243A/B Series Seiko Instruments Inc. 7 „ Electrical Characteristics 1. S-8243A Series Table 6 (1 / 2) (Ta = 25°C unless otherwise specified) Item Symbol Conditions Min. Typ. Max. Unit Test circuit BATTERY PROTECTION Overcharge detection voltage n n=1, 2, 3 VCUn 3.9 V to 4.4 V, 50 mV Step VCUn −0.025 VCUn VCUn +0.025 V 4 Hysteresis voltage n of overcharge detection n = 1, 2, 3 VHCn −0.10 V to −0.40 V, and 0 V VHCn −0.05 VHCn VHCn +0.05 V 4 Overdischarge detection voltage n = 1, 2, 3 VDLn 2.0 V to 3.0 V, 100 mV Step VDLn −0.08 VDLn VDLn +0.08 V 4 Hysteresis voltage n of Overdischarge detection n = 1, 2, 3 VHDn 0.15 V to 0.70 V, and 0 V VHDn −0.10 VHDn VHDn +0.10 V 4 Overcurrent detection voltage 1 V IOV1 0.05 V to 0.3 V, 50 mV Step VM voltage based on VDD VIOV1 −0.025 VIOV1 VIOV1 +0.025 V 4 Overcurrent detection voltage 2 V IOV2 VM voltage based on VDD 0.40 0.50 0.60 V 4 Overcurrent detection voltage 3 V IOV3 − V DD×0.425 V DD×0.5 V DD×0.575 V 4 Temperature coefficient for detection and release voltage*1 TCOE1 Ta = −5°C to +55°C*3 −1.0 0 1.0 mV/ °C 4 Temperature coefficient for overcurrent detection voltage *2 TCOE2 Ta = −5°C to +55°C*3 −0.5 0 0.5 mV/ °C 4 0 V BATTERY CHARGING FUNCTION (The 0 V battery function is either "0 V battery charging is allowed." or "0 V battery charging is inhibited." depending upon the product type.)

0 V battery charge starting charger

voltage V0CHA 0 V battery charging available − 0.8 1.5 V 7

0 V battery charge inhibition battery

0INH 0 V battery charging unavailable 0.4 0.7 1.1 V 7 INTERNAL RESISTANCE Internal resistance between VMP and VDD R VDM V1 = V2 = V3 = 3.5 V 500 1100 2400 k Ω 8 Internal resistance between VMP and VSS R VSM V1 = V2 = V3 = 1.8 V 300 700 1500 k Ω 8 VOLTAGE REGULATOR Output voltage VOUT V DD = 14 V, IOUT = 3 mA 3.221 3.300 3.379 V 2 Line regulation ΔVOUT1 V DD = 6 V→18 V, IOUT = 3 mA − 5 15 mV 2 Load regulation ΔVOUT2 V DD = 14 V, IOUT = 5 μA→3 mA − 15 30 mV 2 BATTERY MONITOR AMP Input offset voltage n n = 1, 2, 3 VOFFn V1 = V2 = V3 = 3.5 V 60 165 270 mV 3 Voltage gain n n INPUT VOLTAGE, OPERATING VOLTAGE Operating voltage between V DD and VSS VDSOP − 6 − 18 V 4 CTL1 input voltage for High V CTL1H − V DD×0.8 − − V 6 CTL1 input voltage for Low V CTL1L − − − V DD×0.2 V 6 CTLn input voltage for High n = 2, 3, 4 V CTLnH − V OUT×0.9 − V OUT V 3, 6 CTLn input voltage for Low n = 2, 3, 4 V CTLnL − − − V OUT×0.1 V 3, 6

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 8 Table 6 (2 / 2) Item Symbol Remarks Min. Typ. Max. Unit Test circuit INPUT CURRENT Current consumption at not monitoring VBATOUT IOPE V1 = V2 = V3 = 3.5 V, V MP = VDD − 65 120 μA 1 Current consumption at power down I PDN V1 = V2 = V3 = 1.5 V, V MP = VSS − − 0.1 μA 1 Current for VCn at not monitoring V BATOUT (n = 2, 3) IVCnN V1 = V2 = V3 = 3.5 V −0.3 0 0.3 μA 3 Current for VC2 at monitoring of V BATOUT IVC2 V1 = V2 = V3 = 3.5 V − 2.0 7.2 μA 3 Current for VC3 at monitoring of V BATOUT IVC3 V1 = V2 = V3 = 3.5 V − 1.0 4.0 μA 3 Current for CTL1 at Low ICTL1L V1 = V2 = V3 = 3.5 V, V CTL1 = 0 V −0.4 −0.2 − μA 5 Current for CTLn at High n = 2,3,4 I CTLnH V CTLn = VOUT − 2.5 5 μA 9 Current for CTLn at Low n = 2,3,4 I CTLnL V CTLn = 0 V −5 −2.5 − μA 9 OUTPUT CURRENT Leak current COP ICOH V COP = 24 V − − 0.1 μA 9 Sink current COP ICOL V COP = VSS+0.5 V 10 − − μA 9 Source current DOP IDOH V DOP = VDD−0.5 V 10 − − μA 9 Sink current DOP IDOL V DOP = VSS+0.5 V 10 − − μA 9 Source current VBATOUT I VBATH V BATOUT = VDD−0.5 V 100 − − μA 9 Sink current VBATOUT I VBATL V BATOUT = VSS+0.5 V 100 − − μA 9 Applied to S-8243AACFT and S-8243AADFT Item Symbol Conditions Min. Typ. Max. Unit Test circuit DELAY TIME Overcharge detection delay time t CU C CT = 0.1 μF 0.5 1.0 1.5 s 5 Overdischarge detection delay time t DL C DT = 0.1 μF 50 100 150 ms 5 Overcurrent detection delay time 1 t lOV1 C DT = 0.1 μF 5 10 15 ms 5 Overcurrent detection delay time 2 t lOV2 − 1.5 2.5 4.0 ms 4 Overcurrent detection delay time 3 t lOV3 − 100 300 600 μs 4 *1. Temperature coefficient for detection and release voltage is app lied to overcharge detection voltage n, overcharge release volt age n, overdischarge detection voltage n, and overdischarge release voltage n. *2. Temperature coefficient for overcurrent detection voltage is applied to over current detection voltage 1 and 2. *3. Since products are not screened at high and low temperature, t he specification for this temperature range is guaranteed by des ign, not tested in production.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK Rev.3.0_00 S-8243A/B Series Seiko Instruments Inc. 9 2. S-8243B Series Table 7 (1 / 2) (Ta = 25°C unless otherwise specified) Item Symbol Conditions Min. Typ. Max. Unit Test circuit DETECTION VOLTAGE Overcharge detection voltage n n = 1, 2, 3, 4 VCUn 3.9 V to 4.4 V, 50 mV Step VCUn −0.025 VCun VCUn +0.025 V 4 Hysteresis voltage n of overcharge detection n = 1, 2, 3, 4 V HCn −0.10 V to −0.40 V, and 0 V VHCn −0.05 VHCn VHCn +0.05 V 4 Overdischarge detection voltage n = 1, 2, 3, 4 V DLn 2.0 V to 3.0 V, 100 mV Step VDLn −0.08 VDLn VDLn +0.08 V 4 Hysteresis voltage n of overdischarge detection n = 1, 2, 3, 4 V HDn 0.15 V to 0.70 V, and 0 V VHDn −0.10 VHDn VHDn +0.10 V 4 Overcurrent detection voltage 1 V IOV1 0.05 V to 0.3 V, 50 mV Step VM voltage based on VDD VIOV1 −0.025 VIOV1 VIOV1 +0.025 V 4 Overcurrent detection voltage 2 V IOV2 VM voltage based on VDD 0.40 0.50 0.60 V 4 Overcurrent detection voltage 3 V IOV3 − VDD ×0.425 VDD ×0.5 VDD ×0.575 V 4 Temperature coefficient for detection and release voltage*1 TCOE1 Ta = −5°C to +55°C*3 −1.0 0 1.0 mV/ °C 4 Temperature coefficient for overcurrent detection voltage *2 TCOE2 Ta = −5°C to +55°C*3 −0.5 0 0.5 mV/ °C 4 0 V BATTERY CHARGING FUNCTION (The 0 V battery function is either "0 V battery charging is allowed." or "0 V battery charging is inhibited. " depending upon the product type.) voltage V0CHA 0 V battery charging allowed − 0.8 1.5 V 7 0INH 0 V battery charging inhibited 0.4 0.7 1.1 V 7 INTERNAL RESISTANCE Internal resistance between VMP and VDD R VDM V1 = V2 = V3 = V4 = 3.5 V 500 1100 2400 k Ω 8 Internal resistance between VMP and VSS R VSM V1 = V2 = V3 = V4 = 1.8 V 300 700 1500 k Ω 8 VOLTAGE REGULATOR Output voltage VOUT V DD = 14V, IOUT = 3 mA 3.221 3.300 3.379 V 2 Line regulation ΔVOUT1 V DD = 6 V→18 V, IOUT = 3 mA − 5 15 mV 2 Load regulation ΔVOUT2 V DD = 14 V, IOUT = 5 μA→3 mA − 15 30 mV 2 BATTERY MONITOR AMP Input offset voltage n n = 1, 2, 3, 4 V OFFn V1 = V2 = V3 = V4 = 3.5 V 60 165 270 mV 3 Voltage gain n n = 1, 2, 3, 4 GAMPn V1 = V2 = V3 = V4 = 3.5 V 0.2 INPUT VOLTAGE, OPERATING VOLTAGE Operating voltage between V DD and VSS VDSOP − 6 − 18 V 4 CTL1 input voltage for High V CTL1H − V DD×0.8 − − V 6 CTL1 input voltage for Low V CTL1L − − − V DD×0.2 V 6 CTLn input voltage for High n = 2, 3, 4 V CTLnH − V OUT×0.9 − V OUT V 3, 6 CTLn input voltage for Low n = 2, 3, 4 V CTLnL − − − V OUT×0.1 V 3, 6

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 10 Table 7 (2 / 2) Item Symbol Remarks Min. Typ. Max. Unit Test circuit INPUT CURRENT Current consumption at not monitoring VBATOUT IOPE V1 = V2 = V3 = V4 = 3.5 V, V MP = VDD − 65 120 μA 1 Current consumption at power down I PDN V1 = V2 = V3 = V4 = 1.5 V, V MP = VSS − − 0.1 μA 1 Current for VCn at not monitoring V BATOUT (n = 2, 3) IVCnN V1 = V2 = V3 = V4 = 3.5 V −0.3 0 0.3 μA 3 Current for VC1 at monitoring of V BATOUT IVC1 V1 = V2 = V3 = V4 = 3.5 V − 3.2 10.4 μA 3 Current for VC2 at monitoring of V BATOUT IVC2 V1 = V2 = V3 = V4 = 3.5 V − 2.0 7.2 μA 3 Current for VC3 at monitoring of V BATOUT IVC3 V1 = V2 = V3 = V4 = 3.5 V, V CTL1 = 0 V − 1.0 4.0 μA 3 Current for CTL1 at Low ICTL1L V1 = V2 = V3 = V4 = 3.5 V, V CTL1 = 0 V −0.4 −0.2 − μA 5 Current for CTLn at High n = 2, 3, 4 I CTLnH V CTLn = VOUT − 2.5 5 μA 9 Current for CTLn at Low n = 2, 3, 4 I CTLnL V CTLn = 0 V −5 −2.5 − μA 9 OUTPUT CURRENT Leak current COP ICOH V COP = 24 V − − 0.1 μA 9 Sink current COP ICOL V COP = VSS+0.5 V 10 − − μA 9 Source current DOP IDOH V DOP = VDD−0.5 V 10 − − μA 9 Sink current DOP IDOL V DOP = VSS+0.5 V 10 − − μA 9 Source current VBATOUT I VBATH V BATOUT = VDD−0.5 V 100 − − μA 9 Sink current VBATOUT IVBATL V BATOUT = VSS+0.5 V 100 − − μA 9 Applied to S-8243BAEFT, S-8243BAFFT, S-8243BAHFT Item Symbol Conditions Min. Typ. Max. Unit Test circuit DELAY TIME Overcharge detection delay time t CU C CT = 0.1 μF 0.5 1.0 1.5 s 5 Overdischarge detection delay time t DL C DT = 0.1 μF 50 100 150 ms 5 Overcurrent detection delay time 1 t lOV1 C DT = 0.1 μF 5 10 15 ms 5 Overcurrent detection delay time 2 t lOV2 − 1.5 2.5 4.0 ms 4 Overcurrent detection delay time 3 t lOV3 − 100 300 600 μs 4 Applied to S-8243BADFT Item Symbol Conditions Min. Typ. Max. Unit Test circuit DELAY TIME Overcharge detection delay time t CU C CT = 0.1 μF 0.5 1.0 1.5 s 5 Overdischarge detection delay time t DL C DT = 0.1 μF 55.5 111 222 ms 5 Overcurrent detection delay time 1 t lOV1 C DT = 0.1 μF 3.31 6.62 13.2 ms 5 Overcurrent detection delay time 2 t lOV2 − 1.5 2.5 4.0 ms 4 Overcurrent detection delay time 3 t lOV3 − 100 300 600 μs 4 *1. Temperature coefficient for detection and release voltage is app lied to overcharge detection voltage n, overcharge release voltage n, overdischarge detection voltage n, and overdischarge release voltage n. *2. Temperature coefficient for overcurrent detection voltage is applied to over current detection voltage 1 and 2. *3. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by des ign, not tested in production.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK Rev.3.0_00 S-8243A/B Series Seiko Instruments Inc. 11 „ Test Circuits In this chapter test methods are explained for the case of S-8243B series, which is designed for 4-serial cell pack. For the case of S-8243A series, which is designed for 3-serial cell, voltage source V2 should be shorted, V3 should be read as V2, and V4 as V3. 1. Current consumption (Test circuit 1) Current consumption at not monitoring VBATOUT, IOPE, is a current measured at the VSS pin when V1 = V2 = V3 = V4 = 3.5 V and VMP = VDD. Current consumption at power down, IPDN, is a current measured at the VSS pin when V1 = V2 = V3 = V4 = 1.5 V and VMP = VSS. 2. Voltage regulator (Test circuit 2) Output voltage of the regulator VOUT is a voltage measured at the VREG pin when VDD = VMP = 14 V and IOUT = 3 mA. Line regulation of t he voltage regulator ΔVOUT1 is defined by the equation ΔVOUT1 = V OUT2−VOUT1 where V OUT1 is the output voltage when VDD = VMP = 6 V and IOUT = 3 mA, and VOUT2 is the output voltage when VDD = VMP = 18 V and IOUT = 3 mA. Load regulation of the regulator is defined by the equation ΔV OUT2 = VOUT3−VOUT where VOUT3 is the output voltage when VDD = VMP = 14 V and IOUT = 5 μA. 3. Battery monitor amp and pin current for VC1 to VC3 (Test circuit 3) Voltage gain of the battery monitor amp for each cell is defined by the input offset voltage and the measurement result provided from the VBATOUT pin for the combination of the CTL3 pin and CTL4 pin expressed by the following table at the condition where V1 = V2 = V3 = V4 = 3.5 V. Pin current for VC1 to VC3, I VCn and I VCnN are at the same time measured. Table 8 CTL3 pin status CTL4 pin status VBATOUT pin output VCn (n = 1, 2, 3) pin current VCTL3H min. V CTL4H min. VOFF1 I VC1 at VC1 pin VCTL3H min. Open VBAT1 − VCTL3H min. V CTL4L max. VOFF2 I VC2 at VC2 pin Open V CTL4H min. VBAT2 − Open Open V OFF3 I VC3 at VC3 pin Open V CTL4L max. VBAT3 − VCTL3L max. V CTL4H min. VOFF4 I VCnN at VCn pin (n = 1, 2, 3) VCTL3L max. Open VBAT4 − Voltage gain of the battery monitor amp for each cell is calculated by the equation GAMPn = (V BATn−VOFFn) / Vn (n = 1 to 4)

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 12 4. Overcharge detection voltages, overcharge detection hysteresis, overdischarge detection voltages, overdischarge detection hysteresis, and overcurrent detection voltages (Test circuit 4) 4. 1 Overcharge detection voltages, hysteresis voltages, and overdischarge detection voltages In the following VMP = VDD and the CDT pin is open. The COP pin and the DOP pin should provide “Low”, which is a voltage equal to VDD × 0.1 V or lower, in the condition that V1 = V2 = V3 = V4 = 3.5 V. The overcharge detection voltage VCU1 is defined by the voltage at which COP pin voltage becomes “High”, which is a voltage equal to VDD × 0.9 V or higher, when the voltage V1 is gradually increased from the starting condition V1 = 3.5 V. The overc harge release voltage VCL1 is defined by the voltage at wh ich COP pin voltage becomes “Low” when the voltage V1 is gradually decreased. The hysteresis voltage of the overcharge detection VHC1 is then defined by the difference between the overcharge detection voltage VCU1 and the overcharge release voltage VCL1. The overdischarge detection voltage VDL1 is defined by the voltage at which DOP pin voltage becomes “High” when the voltage V1 is gradually decreased fr om the starting condition V1 = 3.5 V. The overdischarge release voltage VDU1 is defined by the voltage at which DOP pin voltage becomes “Low” when the voltage V1 is gradually increased. The hysteresis of the ov erdischarge detection voltage V HD1 is then defined by t he difference between the overdischarge release voltage VDU1 and the overdischarge detection voltage VDL1. Other overcharge detection voltage VCUn, hysteresis voltage of overcharge detection VHCn, overdischarge detection voltage VDLn, and hysteresis of the ov erdischarge detection voltage VHDn ( for n = 2 to 4) are defined in the same manner as in the case for n = 1. 4. 2 Overcurrent detection voltages Starting condition is V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and the CDT pin is open. The DOP pin voltage thus provides “Low” The overcurrent detection voltage 1, VIOV1 is defined by the voltage difference VDD − VMP at which the DOP pin voltage becomes “High” when the voltage of VMP pin is decreased. Starting condition for measuring the overcurrent detection voltage 2 and 3 is V1 = V2 = V3 = V4 = 3.5 V, V MP = VDD and the CDT pin voltage VCDT = VSS . The DOP pin voltage thus provides “Low”. The overcurrent detection voltage 2, VIOV2 is defined by the voltage difference VDD−VMP at which the DOP pin voltage becomes “High” when the voltage of VMP pin is decreased. The overcurrent detection delay time 2, tIOV2 is a time needed for the DOP pin to become “High” from “Low” when the VM pin voltage is changed quickly to VIOV2 min.−0.2 V from the starting condition VMP = VDD. The overcurrent det ection voltage 3, V IOV3 is defined by the volt age of the VM pin at which the DOP pin voltage becomes “High” when the voltage of VMP pin is decreased at the speed 10 V / ms. The overcurrent detection delay time 3, tIOV3 is a time needed for the DOP pin to become “High” from “Low” when the VM pin voltage is changed quickly to VIOV3 min.−0.2 V from the starting condition VMP = VDD.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK Rev.3.0_00 S-8243A/B Series Seiko Instruments Inc. 13 5. CTL1 pin current, overcharge detection delay, overdischarge detection delay, and overcurrent detection delay 1 (Test circuit 5) Starting condition is V1 = V2 = V3 = V4 = 3.5 V and VMP = VDD. Current that flows between the CTL1 pin and VSS is the CTL1 pin current ICTL1L. The overcharge detection delay time tCU is a time needed for the COP pin voltage to change from “Low” to “High” just after the V1 voltage is rapidly increased from 3.5 V to 4.5 V. The overdischarge detection delay time tDL is a time needed for the DOP pin voltage to change from “Low” to “High” just after the V1 voltage is rapidly decreased from 3.5 V to 1.5 V. The overcurrent detection delay time 1 is a time needed for the DOP pin voltage to change from “Low” to “High” just after the VMP pin voltage is decreased from VDD to VDD−0.35 V when V1 = 3.5 V. 6. Input voltages for CTL1 and CTL2 (Test circuit 6) Starting condition is V1 = V2 = V3 = V4 = 3.5 V. Pin voltages of the COP and the DOP should be “High” when VCTL1 = VCTL1H min. and CTL2 is OPEN. Pin voltages of the COP and the DOP should be “Low” when VCTL1 = VCTL1L max. and CTL2 is OPEN. Pin voltage of the COP is “High” and the pin voltage of the DOP is “Low” when VCTL1 = VCTL1L max. and VCTL2 = VCTL2H min. Pin voltage of the COP is “Low” and the pin voltage of the DOP is “High” when V CTL1 = VCTL1L max. and VCTL2 = VCTL2L max. 7. 0 V battery charge starting charger voltage and 0 V battery charge inhibition battery voltage (Test circuit 7) One of the 0 V battery charge starting charger volt age and 0 V battery charge inhibition battery voltage is applied to each product according to the 0V battery charging function. Starting condition is V1 = V2 = V3 = V4 = 0 V for a product in which 0 V battery charging is available. The COP pin voltage should be lower than V 0CHA max.−1 V when the VMP pin voltage VMP = V0CHA max. Starting condition is V1 = V2 = V3 = V4 = V0INH for a product in which 0 V battery charging is inhibited. The COP pin voltage should be higher than VMP−1 V when the VMP pin voltage VMP = 24 V.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 14 8. Internal resistance (Test circuit 8) The resistance between VDD and VMP is RVDM and is calculated by the equation RVDM = VDD / IVDM where IVDM is a VMP pin current after VMP is changed to VSS from the starting condition V1 = V2 = V3 = V4 = 3.5 V and VMP = VDD. The resistance between VSS and VMP is RVSM and is calculated by the equation RVSM = VDD / IVSM where IVSM is a VMP pin current at the condition V1 = V2 = V3 = V4 = 1.8 V and VMP = VDD. 9. Pin current for CTL2 to CTL4, COP, DOP, VBATOUT (Test circuit 9) Starting condition is V1 = V2 = V3 = V4 = 3.5 V. Pin current for CTL2 at “High” is I CTL2H and is obtained by setting VCTL2 = VOUT. Pin current for CTL2 at “Low” is ICTL2L and is obtained by setting VCTL2 = VSS. Pin current for CTL3 and CTL4 can be obtained in the same manner as in the CTL2. Pin current for COP at “High” is I COH and is obtained by setting V1 = V2 = V3 = V4 = 6 V, VMP = VDD, and VCOP = VDD. And pin current for COP at “Low” is ICOL and is obtained by setting V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and VCOP = 0.5 V. Pin current for DOP at “Low” is IDOL and is obtained by setting V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and VDOP = 0.5 V. And pin current for COP at “High” is ICOH and is obtained by setting V1 = V2 = V3 =V4 = 3.5 V, VMP = VDD−1 V, and VDOP = VDD−0.5 V. Pin current for VBATOUT at “High” is I VBATH and is obtained by setting CTL3 and CTL4 are open and V BATOUT = VOFF3−0.5 V. And pin current for VBATOUT at “Low” is IVBATL and is obtained by setting VBATOUT = VOFF3+0.5 V. C1=1 μF

8 VSS

7 VC3

6 VC2

5 VC1

3 COP

2 DOP

4 VMP

1 VDD

A C1=1 μF IOUT V Test circuit 1 Test circuit 2 C1=1 μF V A A A R1=1 MΩ V V C1=1 μF Test circuit 3 Test circuit 4 Figure 5 (1 / 2)

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK Rev.3.0_00 S-8243A/B Series Seiko Instruments Inc. 15 C2=0.1 μF A C1=1 μF C3=0.1 μF C1=1 μF R1=1 MΩ V V Test circuit 5 Test circuit 6 R1=1 MΩ V C1=1 μF A C1=1 μF Test circuit 7 Test circuit 8 A A A A A A C1=1 μF Figure 5 (2 / 2)

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 16 „ Operation 1. Battery protection circuit Remark Refer to “„ Battery Protection IC Connection Example”. Battery protection protects batteries from overcharge and overdischarge, and also protects external FETs from overcurrent. 1. 1 Normal status When all of the battery voltages are in the range from V DLn to VCUn and the discharge current is lower than a specified value (the VMP pin voltage is lower than VIOV1), the charging and discharging FETs are turned on. 1. 2 Overcharge status When any one of the battery voltages becomes higher than VCUn and the state continues for tCU or longer, the COP pin becomes high impedance and is pulled up to EB + pin voltage by an external re sistor, and the charging FET is turned off to stop charging. The overcharge status is released when one of the following two conditions holds. (a) All battery voltages become lower than VCUn + VHCn. (b) VDD−VMP>VIOV1 (A load is connected, and discharging starts.) 1. 3 Overdischarge status When any one of the battery voltages becomes lower than VDLn and the state continues for tDL or longer, the DOP pin voltage becomes VDD level, and the discharging FET is turned off to stop discharging. This is the overdischarge status. 1. 4 Power down status After stopping discharging due to overdischarge status, the S-8243 enters power down status. In this status, almost all circuits of the S-8243 are stopped to save current consumption. The current consumption becomes lower than I PDN. In the power down status, the VMP pin is pulled down to VSS level by the internal RVSM resistor. In power down status, output pin voltages are fixed at the following levels. (a) COP High-Z (Charging FET is turned off) (b) DOP V DD (Discharging FET is turned off) (c) VREG V SS (Voltage regulator circuit is off) (d) VBATOUT V SS (Battery voltage monitor amp circuit is off) The power down status is released when the following condition holds. (a) VMP>VIOV3 (A charger is connected, and charging starts.) The overdischarging status is released when the following condition holds. (a) All of the battery voltages are VDLn or higher, and the VMP pin voltage is VDD / 2 or higher. (A charger is connected.) 1. 5 Overcurrent status The S-8243 has three overcu rrent detection levels (V IOV1, VIOV2 and V IOV3) and three overcurrent detection delay times (t IOV1, t IOV2 and t IOV3) corresponding to each overcurrent detecti on levels. When the discharging current becomes higher than a specifi ed value (the voltage between V DD and V MP is greater than V IOV1) and the state continues for tIOV1 or longer, the S-8243 enters the overcurrent status in which the DOP pin voltage becomes V DD level to turn off the discharging FET to stop discharging, the COP pin becomes high impedance and is pulled up to EB+ pin voltage by an external resistor to turn off the charging FET to stop charging, and the VMP pin is pulled up to VDD voltage by the internal resistor RVDM. Operation of two other overcurrent detection levels (VIOV2 and VIOV3) and overcurrent detection delay times (tIOV2 and tIOV3) is the same as that for VIOV1 and tIOV1. The overcurrent status is released when the following condition holds. (a) V MP> {VIOV3 / (1−VIOV3) × 3 / 5−2 / 5} × RVDM (A load is released, and the impedance between the EB− and EB+ pin becomes higher. )

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK Rev.3.0_00 S-8243A/B Series Seiko Instruments Inc. 17 1. 6 0 V battery charging function Regarding the charging of a self-di scharged battery (0 V battery) the S-8243 has two functions from which one should be selected. (a) 0 V battery charging is allowed (0 V battery charging is available) When a charger voltage is higher than V0CHA, 0 V battery can be charged. (b) 0 V battery charging is forbidden (0 V battery charging is impossible) When one of the battery voltages is lower than V0INH, 0 V battery can not be charged. Caution When the VDD pin voltage is lower than minimum of V DSOP, the operation of S-8243 series is not guaranteed. 1. 7 Delay time setting Overcharge detection delay times (t CU1 to t CU4) are determined by the external capacitor at the CCT pin. Overdischarge detection delay times (tDL1 to tDL4) and overcurrent detection delay time 1 (tIOV1) are determined by the external capacitor at CDT pin. Overcurrent detection delay time 2,3 (tIOV2, tIOV3) are fixed internally. S-8243AAC, S-8243AAD, S-8243BAE, S-8243BAF, S-8243BAH min. typ. max. tCU [s] = Delay factor ( 5 10 15 ) × CCT [μF] tDL [ms] = Delay factor ( 500 1000 1500 ) × CDT [μF] tIOV1 [ms] = Delay factor ( 50 100 150 ) × CDT [μF] S-8243BAD min. typ. max. tCU [s] = Delay factor ( 5 10 15 ) × CCT [μF] tDL [ms] = Delay factor ( 555 1110 2220 ) × CDT [μF] tIOV1 [ms] = Delay factor ( 33.1 66.2 132 ) × CDT [μF] 2. Voltage regulator circuit Built-in voltage regulator can be used to drive a micro computer, etc. The voltage regulator supplies voltage of 3.3 V (3 mA maximum) and an external capacitor is needed. Caution In the power down status the voltage regulator output is pulled down to the V SS level by an internal resistor. 3. Battery monitor amp circuit Battery monitor amp sends information of the batteries to a microcomputer. The battery monitor amp output is controlled and selected by CTL3 and CTL4 pins to give the following two voltages. (a) V BATn = GAMPn × VBATTERYn + VOFFn where GAMPn is the n-th voltage gain of the amp, V BATTERYn is the n-th battery voltage, and VOFFn is the n-th offset voltage of the amp. (b) N-th offset voltage V OFFn Each battery voltage VBATTERYn (n = 1 to 4) is thus calculated by following equation. VBATTERYn = (VBATn − VOFFn) / GAMPn (n = 1, 2, 3, 4) After the state of CTL3 and CTL4 are changed, a time between 25 μs and 250 μs is needed for the battery monitor amp to become stable. Caution In the power down status the battery monitor amp output is the V SS level.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 18 4. CTL pins The S-8243 has four control pins. The CTL1 and CTL2 pins are used to control the COP and DOP pin output voltages. CTL1 takes precedence over CTL2. CTL2 takes precedence over the battery protection circuit. The CTL3 and CTL4 pins are used to control the VBATOUT pin output voltage. Table 9 CTL1 and CTL2 Mode Input Output CTL1 pin CTL2 pin External discharging FET External charging FET High High OFF OFF High Open OFF OFF High Low OFF OFF Open High OFF OFF Open Open OFF OFF Open Low OFF OFF Low High Normal*1 OFF *2 Low Open Normal*1 Normal*1 Low Low OFF Normal*1 *1. States are controlled by voltage detection circuit. *2. Off state is brought after the overcharge detection delay time tCU. Table 10 CTL3 and CTL4 Mode Input Output CTL3 pin CTL4 pin V BATOUT (A series) VBATOUT (B series) High High V1 Offset V1 Offset High Open V1 × 0.2 + V1 Offset V1 × 0.2 + V1 Offset High Low Don’t use. V2 Offset Open High Don’t use. V2 × 0.2 + V2 Offset Open*1 Open *1 V2 Offset V3 Offset Open Low V2 × 0.2 + V2 Offset V3 × 0.2 + V3 Offset Low High V3 Offset V4 Offset Low Open V3 × 0.2 + V3 Offset V4 × 0.2 + V4 Offset Low Low Don’t use. Don’t use. *1. CTL3 and CTL4 pins should be open when a microcomputer is not used. Caution Please note unexpected behavior might occur when electrical potential difference between the CTL pin (“L” level) aMSS is generated through the external filter (RVSS and CVSS) as a result of input voltage fluctuations.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK Rev.3.0_00 S-8243A/B Series Seiko Instruments Inc. 19 „ Timing Charts 1. Overcharge detection, Over discharge detection (n = 1 to 4) VCUn VDUn VDLn VCLn Battery voltage High-Z VEB+ VSS COP pin voltage VIOV1 VSS VMP pin voltage VDD VDD DOP pin voltage VSS Charger connected Load connected Status*2 Overcharge detection delay time (tCU) Overdischarge detection delay time (tDL) VBAT VSS VBATOUT pin voltage*1 VOUT VOUT VSS VREG pin voltage VDD High-Z VIOV3 *1. State depends on CTL3 and CTL4 input levels. Refer to Figure 9. *2. <1>: Normal status, <2>: Overcharge status, <3>: Overdischarge status, <4>: Power down status Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger. Figure 6

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 20 2. Overcurrent detection VCU VDU VDL VCL Battery voltage VHC VHD VDD DOP pin voltage VSS High-Z VSS COP pin voltage High-Z High-Z VDD VSS VMP pin voltage VIOV3 VIOV2 VIOV1 Load connected VRETURN VOUT VSS VBATOUT pin voltage*2 VDD VSS VREG pin voltage VOUT VBAT Status*3 Charger connected Overcurrent detection delay time 1 ( tIOV1) Overcurrent detection delay time 3 ( tIOV3) Overcurrent detection delay time 2 ( tIOV2) VEB+ *1. VRETURN = VDD / 6 (typ.) *2. State depends on CTL3 and CTL4 input levels. Refer to Figure 9. *3. <1>: Normal status, <2>: Overcurrent status Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger. Figure 7

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK Rev.3.0_00 S-8243A/B Series Seiko Instruments Inc. 21 3. CTL1, CTL2 pin voltage COP pin Voltage VSS VOUT VSS VBATOUT pin Voltage*2 VDD VSS VREG pin Voltage VOUT VBAT VDD DOP pin Voltage VSS VDD VDD VDD VDD VDD VDD Normal*1 Normal*1 VDD High-Z Normal*1 Normal *1 VDD VSS CTL1 pin Voltage V OUT OPEN VDD VSS VOUT OPEN CTL2 pin Voltage High-Z High-Z High-Z High-Z High-Z High-Z VEB+ *1. State depends on each battery voltage and the VMP pin voltage. *2. State depends on CTL3 and CTL4 input levels. Refer to Figure 9. Figure 8

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 22 4. CTL3, TL4 pin voltage VOFF COP pin voltage *1 VSS VOUT VSS VDD VSS VREG pin voltage VOUT VBAT VDD DOP pin voltage*1 VSS VDD VSS CTL3 pin voltage VOUT OPEN VDD VSS VOUT OPEN CTL4 pin voltage VOUT VSS S-8243A (3-serial cell) VBATOUT pin voltage VBAT S-8243B (4-serial cell) VBATOUT pin voltage (1) VOFF V1 offset +V1 offset V1 × 0.2 V2 offset V2 × 0.2 +V2 offset +V3 offset V3 × 0.2 V3 offset V1 offset +V1 offset V1 × 0.2 V2 offset V3 × 0.2 +V2 offset V3 offset V4 × 0.2 V2 × 0.2 Don’t use Don’t use Don’t use Don’t use +V3 offset V4 offset +V4 offset (1) VEB+ *1. State depends on CTL1 and CTL2 and each battery voltage and the VMP pin voltage. Refer to Figure 6 to 8. Figure 9

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK Rev.3.0_00 S-8243A/B Series Seiko Instruments Inc. 23 „ Battery Protection IC Connection Example 1. S-8243A Series RVSS CTL1 RVMP RDOP EB- EB+ Charging FET Discharging FET RCOP Figure 10 Table 11 Constants for External Components No. Part Typ. Range Unit 1 R VC2 1 0.51 to 1*1 kΩ 2 R VC3 1 0.51 to 1*1 kΩ 3 R VSS 10 2.2 to 10*1 Ω 4 R DOP 5.1 2 to 10 kΩ 5 R COP 1 0.1 to 1 MΩ 6 R VMP 5.1 1 to 10 kΩ

7 R CTL1 1 1 to 100 kΩ

8 R CTL2 1 1 to 10 kΩ

9 R CTL3 1 1 to 10 kΩ

10 R CTL4 1 1 to 10 kΩ

11 R VBAT 0 0 to 100 kΩ

12 C VC2 0.047 0.047 to 0.22*1 μF 13 C VC3 0.047 0.047 to 0.22*1 μF 14 C VSS 4.7 2.2 to 10*1 μF 15 C CCT 0.1 More than 0.01 μF 16 C CDT 0.1 More than 0.02 μF 17 C VREG 4.7 0.68 to 10 μF *1. Please set up a filter constant to be RVSS × CVSS ≥ 22 μF • Ω and to be RVC2 × CVC2 = RVC3 × CVC3 = RVSS × CVSS. Caution1. No resistance should be inserted in the power supply pin VDD. 2. The above constants are subject to change without prior notice. 3. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addi tion, the example of connection s hown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 24 2. S-8243B Series RVSS CTL1 Charging FET Discharging FET RVMP RDOP EB- EB+ Table 12 Constants for External Components No. Part Typ. Range Unit 1 R VC1 1 0.51 to 1*1 kΩ 2 R VC2 1 0.51 to 1*1 kΩ 3 R VC3 1 0.51 to 1*1 kΩ 4 R VSS 10 2.2 to 10*1 Ω 5 R DOP 5.1 2 to 10 kΩ 6 R COP 1 0.1 to 1 MΩ 7 R VMP 5.1 1 to 10 kΩ

8 R CTL1 1 1 to 100 kΩ

9 R CTL2 1 1 to 10 kΩ

10 R CTL3 1 1 to 10 kΩ

11 R CTL4 1 1 to 10 kΩ

12 R VBAT 0 0 to 100 kΩ

13 C VC1 0.047 0.047 to 0.22*1 μF 14 C VC2 0.047 0.047 to 0.22*1 μF 15 C VC3 0.047 0.047 to 0.22*1 μF 16 C VSS 4.7 2.2 to 10*1 μF 17 C CCT 0.1 More than 0.01 μF 18 C CDT 0.1 More than 0.02 μF 19 C VREG 4.7 0.68 to 10 μF *1. Please set up a filter constant to be RVSS × CVSS ≥ 22 μF • Ω and to be RVC1 × CVC1 = RVC2 × CVC2 = RVC3 × CVC3 = RVSS × CVSS. Caution1. No resistance should be inserted in the power supply pin VDD. 2. The above constants are subject to change without prior notice. 3. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addi tion, the example of connection s hown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK Rev.3.0_00 S-8243A/B Series Seiko Instruments Inc. 25 „ Precautions

• Pay attention to the operating conditions for input/output voltage and load current so that the power loss in the IC does not exceed the package power dissipation.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit.
• Seiko Instruments Inc. shall not be responsible for any patent infringement by products including the S-8243 series, the method of using the S-8243 series in such products, the product specifications or the country of destination thereof.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 26 „ The Example of Application Circuit 1. S-8243A Series CTL1 EB− EB+

1. S-8243B Series CTL1 EB- EB+

Caution The above connection exampl e will not guarantee successful operation. Perform thorough evaluation using the actual application.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK Rev.3.0_00 S-8243A/B Series Seiko Instruments Inc. 27 „ Characteristics (Typical Data) 1. Current consumption 100 120 0 4 8 12 16 20 24 VDD [V] S-8243BAF IOPE − VDD IOPE [μA] 100 120 −40 −20 0 2 04 06 08 0 Ta [°C] S-8243BAF IOPE − Temp IOPE [μA] 0.00 0.02 0.04 0.06 0.08 0.10 0 4 8 12 16 20 24 S-8243BAF VDD [V] IPDN − VDD IPDN [μA] 0.00 0.02 0.04 0.06 0.08 0.10 S-8243BAF 0 2 04 06 08 0−40 −20 Ta [°C] IPDN − Temp IPDN [μA] 2. Overcharge detection/release voltage, overdi scharge detection/release voltage, overcurrent detection voltages, and delay times 4.225 4.230 4.235 4.240 4.245 4.250 4.255 4.260 4.265 4.270 4.275 S-8243BAF 0 20 40 60 80 −40 −20 Ta [°C] VCU − Temp VCU [V] 3.95 3.97 3.99 4.01 4.03 4.05 S-8243BAF 02 0 4 0 6 0 8 0−40 −20 Ta [°C] VCL − Temp VCL [V] 2.300 2.325 2.350 2.375 2.400 2.425 2.450 2.475 2.500 S-8243BAF 0 20 40 60 80−40 −20 Ta [°C] VDU − Temp VDU [V] 2.32 2.34 2.36 2.38 2.40 2.42 2.44 2.46 2.48 S-8243BAF 0 20 40 60 80 −40 −20 Ta [°C] VDL − Temp VDL [V] 0.175 0.180 0.185 0.190 0.195 0.200 0.205 0.210 0.215 0.220 0.225 10 12 14 16 S-8243BAF VDD [V] VIOV1 − VDD VIOV1 [V] 0.175 0.180 0.185 0.190 0.195 0.200 0.205 0.210 0.215 0.220 0.225 S-8243BAF 0 20 40 60 80−40 −20 Ta [°C] VIOV1 − Temp VIOV1 [V]

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 28 −0.60 −0.55 −0.50 −0.45 −0.40 10 12 14 16 S-8243BAF VDD [V] VIOV2 − VDD VIOV2 [V] VDD Reference −0.60 −0.55 −0.50 −0.45 −0.40 −40 −20 02 0 4 0 6 0 8 0 Ta [°C] VIOV2 [V] S-8243BAF VIOV2 − Temp VDD Reference 0.425 0.450 0.475 0.500 0.525 0.550 0.575 10 12 14 16 S-8243BAF VDD [V] VIOV3 − VDD VIOV3 / VDD 0.425 0.450 0.475 0.500 0.525 0.550 0.575 Ta [°C] S-8243BAF VIOV3 − Temp VIOV3 / VDD −40 −20 0 20 40 60 80 S-8243BAF CCT [μF] tCU − CCT tCU [s] 0.0 0.5 1.0 1.5 2.0 2.5 −40 −20 0 20 40 60 80 Ta [°C] tCU [s] S-8243BAF tCU − Temp CCT = 0.1 μF 500 1000 1500 S-8243BAF CDT [μF] tDL − CDT tDL [ms] 100 150 200 250 −40 −20 02 0 4 0 6 0 8 0 Ta [°C] tDL [ms] S-8243BAF tDL − Temp CDT = 0.1 μF 100 150 S-8243BAF CDT [μF] tIOV1 − CDT tIOV1 [ms] −40 −20 0 20 40 60 80 Ta [°C] tIOV1 [ms] S-8243BAF tIOV1 − Temp CDT = 0.1 μF 1.5 2.0 2.5 3.0 3.5 4.0 −40 −20 02 0 4 0 6 0 8 0 Ta [°C] tIOV2 [ms] S-8243BAF tIOV2 − Temp 100 200 300 400 500 600 −40 −20 0 20 40 60 80 Ta [°C] tIOV3 [μs] S-8243BAF tIOV3 − Temp

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK Rev.3.0_00 S-8243A/B Series Seiko Instruments Inc. 29 3. COP / DOP pin current 0.00 0.02 0.04 0.06 0.08 0.10 0 4 8 12 16 20 24 S-8243BAF VCOP [V] ICOH − VCOP ICOH [μA] 0 3.5 7.0 10.5 14.0 S-8243BAF VCOP [V] ICOL − VCOP ICOL [mA] 0 1.8 3.6 5.4 7.2 S-8243BAF VDOP [V] IDOH − VDOP IDOH [mA] 0 3.5 7.0 10.5 14.0 S-8243BAF VDOP [V] IDOL − VDOP IDOL [mA] 4. Voltage regulator 3.0 3.1 3.2 3.3 3.4 3.5 3.6 −40 −20 0 20 40 60 80 Ta [°C] VOUT [V] S-8243BAF VOUT − Temp 2.3 2.8 3.3 3.8 048 1 2 1 6 2 0 2 4 IOUT = 5 μA 100 μA 3 mA 10 mA S-8243BAF VDD [V] VOUT − VDD VOUT [V] VDD = 0→24 V, Ta = 25°C 0.0 1.0 2.0 3.0 4.0 0 20 40 60 80 100 VDD = 6 V 14 V 18 V 10 V IOUT [mA] VOUT − IOUT VOUT [V] V1 = V2 = V3 = V4 = VBAT S-8243BAF 0.0 1.0 2.0 3.0 4.0 0 20 40 60 80 100 85°C Ta = −40°C 25°C IOUT [mA] VOUT − IOUT VOUT [V] S-8243BAF

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.3.0_00 Seiko Instruments Inc. 30 5. Battery monitor amp 150 155 160 165 170 175 180 1 2 3 4 5 VOFF3 S-8243BAF VBAT [V] VOFF − VBAT VOFF [mV] V1 = V2 = V3 = V4 = VBAT VOFF4 VOFF2 VOFF1 150 155 160 165 170 175 180 −40 −20 02 04 0 6 0 8 0 Ta [°C] VOFF [mV] S-8243BAF VOFF − Temp VOFF3 VOFF4 VOFF2 VOFF1 0.198 0.199 0.200 0.201 0.202 1 2 3 4 5 GAMP S-8243BAF GAMP4 GAMP3 GAMP2 GAMP1 VBAT [V] GAMP − VBAT V1 = V2 = V3 = V4 = VBAT 0.198 0.199 0.200 0.201 0.202 −40 −20 0 20 40 60 80 Ta [°C] GAMP GAMP − Temp S-8243BAF GAMP4 GAMP3 GAMP2 GAMP1

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