S-8233A SII | Alldatasheet
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Rev.3.2_10 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Seiko Instruments Inc. 1 The S-8233A Series is a series of lithium-ion rechargeable battery protection ICs incorporating high-accuracy voltage detection circuits and delay circuits. It is suitable for a 3-serial-cell lithium-ion battery pack. Features (1) Internal high-accuracy voltage detection circuit y Over charge detection voltage 4.10 ± 0.05 V to 4.35 ± 0.05 V 50 mV- step y Over charge release voltage 3.85 ± 0.10 V to 4.35 ± 0.10 V 50 mV- step (The over charge release voltage can be selected within the range where a difference from over charge detection voltage is 0 V to 0.3 V) y Over discharge detection voltage 2.00 ± 0.08 V to 2.70± 0.08 V 100 mV- step y Over discharge release voltage 2.00 ± 0.10 V to 3.70± 0.10 V 100 mV - step (The over discharge release voltage can be selected within the range where a difference from over discharge detection voltage is 0 V to 1.0 V) y Over current detection voltage 1 0.15 ±0.015 V to 0.5 ±0.05 V 50 mV-step (2) High input-voltage device (abs olute maximum rating: 26 V) (3) Wide operating voltage range: 2 V to 24 V (4) The delay time for every detection can be set via an external capacitor. (5) Three over current detection levels (protection for short-circuiting) (6) Internal charge/discharge prohibition circuit via the control terminal (7) The function for charging batteries from 0 V is available. (8) Low current consumption y Operation 50 µA max. (+25 °C) y Power-down 0.1 µA max. (+25 °C)
Applications
Lithium-ion rechargeable battery packs Packages Drawing Code Package Name Package Tape Reel 14-Pin SOP FE014-A FE014-A FE014-A 16-Pin TSSOP FT016-A FT016-A FT016-A
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.3.2_10 Seiko Instruments Inc. 2 Block Diagram Battery 1 Over charge Battery 3 Over discharge Battery 3 Over charge Battery 2 Over charge Battery 2 Over discharge Over charge delay circuit Battery 1 Over discharge Battery 3 Over charge Battery 2 Over charge Battery 1 Over charge Reference volta ge 3 Reference voltage 2 Reference voltage 1 Control Logic Over current detection circuit Over discharge delay circuit Over current1, delay circuit Over current 2,3 delay circuit DOP VMP COVT CDT CCT COP CTLVSS CD3 VC2 CD2 CD1 VC1 VCC Floating detection circuit Figure 1 Remark The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The delay time cannot be changed via an external capacitor.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK Rev.3.2_10 S-8233A Series Seiko Instruments Inc. 3 Product Name Structure 1. Product name S−8233A x xx − TB IC direction in tape specifications*1 Package name (abbreviation) FE: 14-Pin SOP FT: 16-Pin TSSOP Serial code Assigned from A to Z in alphabetical order *1. Refer to the taping specifications.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.3.2_10 Seiko Instruments Inc. 4 2. Product name list ・14-Pin SOP Table 1 Product name / Parameter Overcharge detection voltage VCU Overcharge release voltage VCD Overdischarge detection voltage VDD Overdischarge release voltage VDU Overcurrent detection voltage1 VIOV1
0 V battery
*1. Without over charge detection hysteresis. Remark Please contact the SII marketing department for the products with the detection voltage value other than those specified above. ・16-Pin TSSOP Table 2 Product name / Parameter Overcharge detection voltage VCu Overcharge release voltage VCD Overdischarge detection voltage VDD Overdischarge release voltage VDU Overcurrent detection voltage1 VIOV1 *1. Without over charge detection hysteresis. Remark Please contact the SII marketing department for the products with the detection voltage value other than those specified above.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK Rev.3.2_10 S-8233A Series Seiko Instruments Inc. 5 Pin Assignment Table 3 Pin No. Symbol Pin description
1 DOP Connects FET gate for discharge control (CMOS output)
2 COP Connects FET gate for charge control (Nch open-drain output)
3 VMP Detects voltage between VCC to VMP(Over current detection pin)
4 COVT Connects capacitor for over current detection1delay circuit
5 CDT Connects capacitor for over discharge detection delay circuit
6 CCT Connects capacitor for over charge detection delay circuit
7 VSS Negative power input, and connects negative voltage for battery 3
8 CTL Charge/discharge control signal input
9 CD3 Battery 3 conditioning signal output
10 VC2 Connects battery 2 negative voltage and battery 3 positive voltage
11 CD2 Battery 2 conditioning signal output
12 VC1 Connects battery 1 negative voltage and battery 2 positive voltage
13 CD1 Battery 1 conditioning signal output
1 DOP
14 VCC Positive power input and connects battery 1 positive voltage
Pin No. Symbol Pin description
2 NC No connection*1
3 COP Connects FET gate for charge control (Nch open-drain output)
4 VMP Detects voltage between VCC to VMP(Over current detection pin)
5 COVT Connects capacitor for over current detection1 delay circuit
6 CDT Connects capacitor for over discharge detection delay circuit
7 CCT Connects capacitor for over charge detection delay circuit
8 VSS Negative power input, and connects negative voltage for battery 3
9 CTL Charge/discharge control signal input
10 CD3 Battery 3 conditioning signal output
11 VC2 Connects battery 2 negative voltage and battery 3 positive voltage
12 CD2 Battery 2 conditioning signal output
13 VC1 Connects battery 1 negative voltage and battery 2 positive voltage
14 CD1 Battery 1 conditioning signal output
15 NC No connection*1
16 VCC Positive power input and connects battery 1 positive voltage
*1. The NC pin is electrically open. The NC pin can be connected to VCC or VSS.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.3.2_10 Seiko Instruments Inc. 6 Absolute Maximum Ratings Table 5 (Ta = 25 °C unless otherwise specified) Parameter Symbol Applicable Pins Absolute Maximum Ratings Unit Input voltage between VCC and VSS VDS － V SS−0.3 ~ VSS+26 V Input pin voltage VIN VC1, VC2, CTL, CCT, CDT, COVT V SS−0.3 ~ VCC+0.3 V VMP Input terminal voltage V VMP VMP V SS−0.3 ~ VSS+26 V CD1 output terminal voltage V CD1 CD1 V C1−0.3 ~ VCC+0.3 V CD2 output terminal voltage VCD2 CD2 V C2−0.3 ~ VCC+0.3 V CD3 output terminal voltage VCD3 CD3 V SS−0.3 ~ VCC+0.3 V DOP output terminal voltage VDOP DOP V SS−0.3 ~ VCC+0.3 V COP output terminal voltage VCOP COP V SS−0.3 ~ VSS+26 V － 14-Pin SOP 400 mWPower dissipation P D － 16-Pin TSSOP 300 mW Operating temperature range Topr － −20 ~ +70 °C Storage temperature range Tstg － −40 ~ +125 °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK Rev.3.2_10 S-8233A Series Seiko Instruments Inc. 7 Electrical Characteristics Table 6 (1 / 2) (Ta = 25 °C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Measure- ment condition Measure- ment circuit Detection voltage Over charge detection voltage1 VCU1 4.10 to 4.35 Adjustment VCU1−0.05 V CU1 V CU1+0.05 V 1 1 Over charge release voltage1 VCD1 3.85 to 4.35 Adjustment VCD1−0.10 V CD1 V CD1+0.10 V 1 1 Over discharge detection voltage1 VDD1 2.00 to 2.70 Adjustment VDD1−0.08 V DD1 V DD1+0.08 V 1 1 Over discharge release voltage1 VDU1 2.00 to 3.70 Adjustment VDU1−0.10 V DU1 V DU1+0.10 V 1 1 Over charge detection voltage 2 VCU2 4.10 to 4.35 Adjustment VCU2−0.05 V CU2 V CU2+0.05 V 2 1 Over charge release voltage 2 VCD2 3.85 to 4.35 Adjustment VCD2−0.10 V CD2 V CD2+0.10 V 2 1 Over discharge detection voltage 2 VDD2 2.00 to 2.70 Adjustment VDD2−0.08 V DD2 V DD2+0.08 V 2 1 Over discharge release voltage 2 VDU2 2.00 to 3.70 Adjustment VDU2−0.10 V DU2 V DU2+0.10 V 2 1 Over charge detection voltage3 VCU3 4.10 to 4.35 Adjustment VCU3−0.05 V CU3 V CU3+0.05 V 3 1 Over charge release voltage3 VCD3 3.85 to 4.35 Adjustment VCD3−0.10 V CD3 V CD3+0.10 V 3 1 Over discharge detection voltage3 VDD3 2.00 to 2.70 Adjustment VDD3−0.08 V DD3 V DD3+0.08 V 3 1 Over discharge release voltage3 VDU3 2.00 to 3.70 Adjustment VDU3−0.10 V DU3 V DU3+0.10 V 3 1 Over current detection voltage1*1 VIOV1 0.15 to 0.50V Adjustment VIOV1 x 0.9 V IOV1 VIOV1 x 1.1 V 4 2 Over current detection voltage 2 VIOV2 VCC Reference 0.54 0.6 0.66 V 4 2 Over current detection voltage3 VIOV3 VSS Reference 1.0 2.0 3.0 V 4 2 Voltage temperature factor 1*2 TCOE1 Ta=-20 to 70°C −1.0 0 1.0 mV/ °C − − Voltage temperature factor 2*3 TCOE2 Ta=-20 to 70°C −0.5 0 0.5 mV/ °C − − Delay time Over charge detection delay time1 tCU1 CCCT=0.47 µF 0.5 1.0 1.5 s 9 6 Over charge detection delay time 2 tCU2 CCCT=0.47 µF 0.5 1.0 1.5 s 10 6 Over charge detection delay time3 tCU3 CCCT=0.47 µF 0.5 1.0 1.5 s 11 6 Over discharge detection delay time1 tDD1 CCDT=0.1 µF 20 40 60 ms 9 6 Over discharge detection delay time 2 tDD2 CCDT=0.1 µF 20 40 60 ms 10 6 Over discharge detection delay time3 tDD3 CCDT=0.1 µF 20 40 60 ms 11 6 Over current detection delay time1 tIOV1 CCOVT=0.1 µF 10 20 30 ms 12 7 Over current detection delay time 2 tIOV2 − 2 4 8 ms 12 7 Over current detection delay time3 tIOV3 FET gate capacitor =2000 pF 100 300 550 µs 12 7 Operating voltage Operating voltage between VCC and VSS*4 VDSOP − 2.0 − 24 V − − Current consumption Current consumption (during normal operation) IOPE V1=V2=V3=3.5 V − 20 50 µA 5 3 Current consumption for cell 2 ICELL2 V1=V2=V3=3.5 V −300 0 300 nA 5 3 Current consumption for cell 3 ICELL3 V1=V2=V3=3.5 V −300 0 300 nA 5 3 Current consumption at power down IPDN V1=V2=V3=1.5 V − − 0.1 µA 5 3 Internal resistance RVCM V1=V2=V3=3.5 V 0.40 0.90 1.40 M Ω 6 3 Resistance between VCC and VMP V1=V2=V3=3.5 V *5 0.20 0.50 0.80 M Ω 6 3 RVSM V1=V2=V3=1.5 V 0.40 0.90 1.40 M Ω 6 3 Resistance between VSS and VMP V1=V2=V3=1.5 V *5 0.20 0.50 0.80 M Ω 6 3 Input voltage CTL"H" Input voltage VCTL(H) − VCCx0.8 − − V − − CTL"L" Input voltage VCTL(L) − − − VCCx0.2 V − −
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.3.2_10 Seiko Instruments Inc. 8 Table 6 (2 / 2) (Ta = 25 °C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Measure- ment condition Measure- ment circuit Output voltage DOP"H" voltage V DO(H) I OUT=10 µA V CC-0.5 − − V 7 4 DOP"L" voltage V DO(L) I OUT=10 µA − − VSS+0.1 V 7 4 COP"L" voltage V CO(L) I OUT=10 µA − − VSS+0.1 V 8 5 COP OFF LEAK current I COL V1=V2=V3=4.5 V − − 100 nA 14 9 CD1"H" voltage V CD1(H) I OUT=0.1 µA V CC -0.5 − − V 13 8 CD1"L" voltage V CD1(L) I OUT=10 µA − − VC1+0.1 V 13 8 CD 2"H" voltage V CD2(H) I OUT=0.1 µA V CC -0.5 − - V 13 8 CD 2"L" voltage V CD2(L) I OUT=10 µA − − VC2+0.1 V 13 8 CD3"H" voltage V CD3(H) I OUT=0.1 µA V CC -0.5 − − V 13 8 CD3"L" voltage V CD3(L) I OUT=10 µA − − VSS+0.1 V 13 8
0 V battery charging function
0 V charging start voltage V 0CHAR −*5 − − 1.4 V 15 10 *1. If over current detection voltage 1 is 0.50 V, both over current detection voltages 1 and 2 are 0.54 to 0.55 V, but VIOV2 > VIOV1. *2. Voltage temperature factor 1 indicates over charge de tection voltage, over charge release voltage, over discharge detection voltage, and over discharge release voltage. *3. Voltage temperature factor 2 indicates over current detection voltage. *4. The DOP and COP logic must be established for the operating voltage. *5. This spec applies for only 0 V battery charging function available type.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK Rev.3.2_10 S-8233A Series Seiko Instruments Inc. 9 Measurement Circuits (1) Measurement 1 Measurement circuit 1 Set V1, V2, and V3 to 3.5 V under normal condition. Increase V1 from 3.5 V gradually. The V1 voltage when COP = 'H' is over charge detection voltage 1 (VCU1). Decrease V1 gradually. The V1 voltage when COP = 'L' is over charge release voltage 1 (VCD1). Further decrease V1. The V1 voltage when DOP = 'H' is over discharge voltage 1 (VDD1). Increase V1 gradually. The V1 voltage when DOP = 'L' is over discharge release voltage 1 (VDU1). Remark The voltage change rate is 150 V/s or less. (2) Measurement 2 Measurement circuit 1 Set V1, V2, and V3 to 3.5 V under normal condition. Increase V2 from 3.5 V gradually. The V2 voltage when COP = 'H' is over charge detection voltage 2 (VCU2). Decrease V2 gradually. The V2 voltage when COP = 'L' is over charge release voltage 2 (VCD2). Further decrease V2. The V2 voltage when DOP = 'H' is over discharge voltage 2 (VDD2). Increase V2 gradually. The V2 voltage when DOP = 'L' is over discharge release voltage 2 (VDU2). Remark The voltage change rate is 150 V/s or less. (3) Measurement 3 Measurement circuit 1 Set V1, V2, and V3 to 3.5 V under normal condition. Increase V3 from 3.5 V gradually. The V3 voltage when COP = 'H' is over charge detection voltage 3 (VCU3). Decrease V3 gradually. The V3 voltage when COP = 'L' is over charge release voltage 3 (VCD3). Further decrease V3. The V3 voltage when DOP = 'H' is over discharge voltage 3 (VDD3). Increase V3 gradually. The V3 voltage when DOP = 'L' is over discharge release voltage 3 (VDU3). Remark The voltage change rate is 150 V/s or less. (4) Measurement 4 Measurement circuit 2 Set V1, V2, V3 to 3.5 V and V4 to 0 V under normal condition. Increase V4 from 0 V gradually. The V4 voltage when DOP = 'H' and COP = 'H', is over current detection voltage 1 (VIOV1). Set V1, V2, and V3 to 3.5 V and V4 to 0 V under normal condition. Fix the COVT terminal at VSS, increase V4 from 0 V gradually. The V4 voltage when DOP = 'H' and COP = 'H' is over current detection voltage 2 (VIOV2). Set V1, V2, and V3 to 3.5 V and V4 to 0 V under normal condition. Fix the COVT terminal at VSS, increase V4 gradually from 0 V at 400 µs to 2 ms. The V4 voltage when DOP = 'H' and COP = 'H' is over current detection voltage 3 (VIOV3). (5) Measurement 5 Measurement circuit 3 Set S1 to ON, V1, V2, and V3 to 3.5 V, and V4 to 0 V under normal condition and measure current consumption. I1 is the normal condition current consumption (IOPE), I2, the cell 2 current consumption (ICELL2), and I3, the cell 3 current consumption (ICELL3). Set S1 to ON, V1, V2, and V3 to 1.5 V, and V4 to 4.5 V under over discharge condition. Current consumption I1 is power-down current consumption (IPDN). (6) Measurement 6 Measurement circuit 3 Set S1 to ON, V1, V2, and V3 to 3.5 V, and V4 to 10.5 V under normal condition. V4/I4 is the internal resistance between VCC and VMP (RVCM). Set S1 to ON, V1, V2, and V3 to 1.5 V, and V4 to 4.1 V under over discharge condition. (4.5-V4)/I4 is the internal resistance between VSS and VMP (RVSM).
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.3.2_10 Seiko Instruments Inc. 10 (7) Measurement 7 Measurement circuit 4 Set S1 to ON, S2 to OFF, V1, V2, and V3 to 3.5 V, and V4 to 0 V under normal condition. Increase V5 from 0 V gradually. The V5 voltage when I1 = 10 µA is DOP'L' voltage (VD0(L)). Set S1 to OFF, S2 to ON, V1, V2, V3 to 3.5 V, and V4 to VIOV2+0.1 V under over current condition. Increase V6 from 0 V gradually. The V6 voltage when I2 = 10 µA is the DOP'H' voltage (VDO(H)). (8) Measurement 8 Measurement circuit 5 Set V1, V2, V3 to 3.5 V and V4 to 0 V under normal condition. Increase V5 from 0 V gradually. The V5 voltage when I1 = 10 µA is the COP'L' voltage (VC0(L)). (9) Measurement 9 Measurement circuit 6 Set V1, V2, V3 to 3.5 V under normal condition. Increase V1 from 3.5 V to 4.5 V immediately (within 10 µs). The time after V1 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 1 (tCU1). Set V1, V2, V3 to 3.5 V under normal condition. Decrease V1 from 3.5 V to 1.9 V immediately (within 10 µs). The time after V1 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 1 DD1). (10) Measurement 10 Measurement circuit 6 Set V1, V2, V3 to 3.5 V under normal condition. Increase V2 from 3.5 V to 4.5 V immediately (within 10 µs). The time after V2 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 2 (t CU2). Set V1, V2, V3 to 3.5 V under normal condition. Decrease V2 from 3.5 V to 1.9 V immediately (within 10 µs). The time after V2 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 2 DD2). (11) Measurement 11 Measurement circuit 6 Set V1, V2, V3 to 3.5 V under normal condition. Increase V3 from 3.5 V to 4.5 V immediately (within 10 µs). The time after V3 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 3 (t CU3). Set V1, V2, V3 to 3.5 V under normal condition. Decrease V3 from 3.5 V to 1.9 V immediately (within 10 µs). The time after V3 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 3 DD3). (12) Measurement 12 Measurement circuit 7 Set V1, V2, V3 to 3.5 V and S1 to OFF under normal condition. Increase V4 from 0 V to 0.55 V immediately (within 10 µs). The time after V4 becomes 0.55 V until DOP goes 'H' is the over current detection delay time 1 (tI0V1). Set V1, V2, V3 to 3.5 V and S1 to OFF under normal condition. Increase V4 from 0 V to 0.75 V immediately (within 10 µs). The time after V4 becomes 0.75 V until DOP goes 'H' is the over current detection delay time 2 (tIOV2) Set S1 to ON to inhibit over discharge detection. Set V1, V2, V3 to 4.0 V and increase V4 from 0 V to 6.0 V immediately (within 1 µs) and decrease V1, V2, and V3 to 2.0 V at a time. The time after V4 becomes 6.0 V until DOP goes 'H' is the over current detection delay time 3 (tIOV3).
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK Rev.3.2_10 S-8233A Series Seiko Instruments Inc. 11 (13) Measurement 13 Measurement circuit 8 Set S4 to ON, S1, S2, S3, S5, and S6 to OFF, V1, V2, V3 to 3.5 V and V4, V6, and V7 to 0 V under normal condition. Increase V5 from 0 V gradually. The V5 voltage when I2 = 10 µA is the CD1'L' voltage (VCD1(L)) Set S5 to ON, S1, S2, S3, S4, and S6 to OFF, V1, V2, and V3 to 3.5 V and V4, V5, and V7 to 0 V under normal condition. Increase V6 from 0 V gradually. The V6 voltage when I3 = 10 µA is the CD2'L' voltage (VCD2(L)). Set S6 to ON, S1, S2, S3, S4, and S5 to OFF, V1, V2, and V3 to 3.5 V and V4, V5, and V6 to 0 V under normal condition. Increase V7 from 0 V gradually. The V7 voltage when I4 = 10 µA is the CD3'L' voltage (VCD3(L)). Set S1 to ON, S2, S3, S4, S5, and S6 to OFF, V1 to 4.5 V, V2 and V3 to 3.5 V and V5, V6, and V7 to 0 V under over charge condition. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 µA is the CD1'H' voltage (VCD1(H)). Set S2 to ON, S1, S3, S4, S5, and S6 to OFF, V2 to 4.5 V, V1 and V3 to 3.5 V and V5, V6, and V7 to 0 V under over charge condition. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 µA is the CD2'H' voltage (VCD2(H)). Set S3 to ON, S1, S2, S4, S5, and S6 to OFF, V3 to 4.5 V, V1 and V2 to 3.5 V and V5, V6, and V7 to 0 V under over charge condition. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 µA is the CD3'H' voltage (VCD3(H)). (14) Measurement 14 Measurement circuit 9 Set V1, V2, and V3 to 4.5 V under over charge condition. The current I1 flowing to COP terminal is COP OFF LEAK current (ICOL). (15) Measurement 15 Measurement circuit 10 Set V1, V2, and V3 to 0 V, and V8 to 2 V, and decrease V8 gradually. The V8 voltage when COP = 'H' (VSS + 0.1 V or higher) is the 0V charge start voltage (V0CHAR).
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.3.2_10 Seiko Instruments Inc. 12 VSS DOP CTL VC2 COP VMP VC1 CCT COVT CDT VCC CD3 CD2 CD1 1 MΩ S-8233A VSS DOP CTL VC2 COP VMP VC1 CCT COVT CDT VCC CD3 CD2 CD1 1 MΩ S-8233A Measurement circuit 1 Measurement circuit 2 VSS DOP CTL VC2 COP VMP VC1 CCT COVT CDT VCC CD3 CD2 CD1 S-8233A VSS DOP CTL VC2 COP VMP VC1 CCT COVT CDT VCC CD3 CD2 CD1 S1 I1 S2 I2 S-8233A Measurement circuit 3 Measurement circuit 4 VSS DOP CTL VC2 COP VMP VC1 CCT COVT CDT VCC CD3 CD2 CD1 V5 I1 S-8233A VSS DOP CTL VC2 COP VMP VC1 CCT COVT CDT VCC CD3 CD2 CD1 1 MΩ C1=0.47 µF C2=0.1 µF C3=0.1 µF S-8233A Measurement circuit 5 Measurement circuit 6 Figure 4 (1/2)
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK Rev.3.2_10 S-8233A Series Seiko Instruments Inc. 13 VSS DOP CTL VC2 COP VMP VC1 CCT COVT CDT VCC CD3 CD2 CD1 C1=0.47 µF C2=0.1 µF C3=0.1 µF 1 MΩ S-8233A VSS DOP CTL VC2 COP VMP VC1 CCT COVT CDT VCC CD3 CD2 CD1 1 MΩ S-8233A Measurement circuit 7 Measurement circuit 8 VSS DOP CTL VC2 COP VMP VC1 CCT COVT CDT VCC CD3 CD2 CD1 S-8233A VSS DOP CTL VC2 COP VMP VC1 CCT COVT CDT VCC CD3 CD2 CD1
1 MΩ V8
Measurement circuit 9 Measurement circuit 10 Figure 4 (2/2)
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.3.2_10 Seiko Instruments Inc. 14 Operation Remark Refer to “Battery Protection IC Connection Example”. Normal condition This IC monitors the voltages of the three serially-connected batteries and the discharge current to control charging and discharging. If the voltages of all the three batteries are in the range from the over discharge detection voltage (VDD) to the over charge detection voltage (VCU), and the current flowing through the batteries becomes equal or lower than a specified value (the VMP terminal voltage is equal or lower than over current detection voltage 1), the charging and discharging FETs turn on. In this condition, charging and discharging can be carried out freely. This condition is called the normal condition. In this condition, the VMP and VCC terminals are shorted by the RVCM resistor. Over current condition This IC is provided with the three over current detection levels (VIOV1,VIOV2 and VIOV3) and the three over current detection delay time (tIOV1,tIOV2 and tIOV3) corresponding to each over current detection level. If the discharging current becomes equal to or higher than a specified value (the VMP terminal voltage is equal to or higher than the over current detection voltage) during discharging under normal condition and it continues for the over current detection delay time (t IOV) or longer, the discharging FET turns off to stop discharging. This condition is called an over current condition. The VMP and VCC terminals are shorted by the RVCM resistor at this time. The charging FET turns off. When the discharging FET is off and a load is connected, the VMP terminal voltage equals the VSS potential. The over current condition returns to the normal condition when the load is released and the impedance between the EB- and EB+ terminals (see Figure 9 for a connection example) is 100 MΩ or higher. When the load is released, the VMP terminal, which and the VCC terminal are shorted with the RVCM resistor, goes back to the VCC potential. The IC detects that the VMP terminal potential returns to over current detection voltage 1 (VIOV1) or lower (or the over current detection voltage 2 (VIOV2) or lower if the COVT terminal is fixed at the 'L' level and over current detection 1 is inhibited) and returns to the normal condition. Over charge condition If one of the battery voltages becomes higher than the over charge detection voltage (VCU) during charging under normal condition and it continues for the over charge detection delay time (tCU) or longer, the charging FET turns off to stop charging. This condition is called the over charge condition. The 'H' level signal is output to the conditioning terminal corresponding to the battery which exceeds the over charge detection voltage until the battery becomes equal to lower than the over charge release voltage (VCD). The battery can be discharged by connecting an Nch FET externally. The discharging current can be limited by inserting R11, R12 and R13 resistors (see Figure 9 for a connection example). The VMP and VCC terminals are shorted by the RVCM resistor under the over charge condition. The over charge condition is released in two cases: 1) The battery voltage which exceeded the over charge detection voltage (VCU) falls below the over charge release voltage (VCD), the charging FET turns on and the normal condition returns. 2) If the battery voltage which exceed ed the over charge detection voltage (VCU) is equal or higher than the over charge release voltage (VCD), but the charger is removed, a load is placed, and discharging starts, the charging FET turns on and the normal condition returns. The release mechanism is as follows: the discharge current flows through an internal parasitic diode of the charging FET immediately after a load is installed and discharging starts, and the VMP terminal voltage decreases by about 0.6 V from the VCC terminal voltage momentarily. The IC detects this voltage (over current detection voltage 1 or higher), releases the over charge condition and returns to the normal condition.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK Rev.3.2_10 S-8233A Series Seiko Instruments Inc. 15 Over discharge condition If any one of the battery voltages falls below the over discharge detection voltage (VDD) during discharging under normal condition and it continues for the over discharge detection delay time (tDD) or longer, the discharging FET turns off and discharging stops. This condition is called the over discharge condition. When the discharging FET turns off, the VMP terminal voltage becomes equal to the VSS voltage and the IC's current consumption falls below the power-down current consumption (IPDN). This condition is called the power-down condition. The VMP and VSS terminals are shorted by the RVSM resistor under the over discharge and power-down conditions. The power-down condition is canceled when the charger is connected and the voltage between VMP and VSS is 3.0 V or higher (over current detection voltage 3). When all the battery voltages becomes equal to or higher than the over discharge release voltage (VDU) in this condition, the over discharge condition changes to the normal condition. Delay circuits The over charge detection delay time (tCU1 to tCU3), over discharge detection delay time (tDD1 to tDD3), and over current detection delay time 1 (tIOV1) are changed with external capacitors (C4 to C6). The delay times are calculated by the following equations: Min. Typ. Max. tCU[s] =Delay factor ( 1.07, 2.13, 3.19)×C4 [uF] tDD[s] =Delay factor ( 0.20, 0.40, 0.60)×C5 [uF] tIOV1[s]=Delay factor ( 0.10, 0.20, 0.30)×C6 [uF] Caution: The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The delay time cannot be changed via an external capacitor. CTL terminal If the CTL terminal is floated under normal condition, it is pulled up to the VCC potential in the IC, and both the charging and discharging FETs turn off to inhibit charging and discharging. Both charging and discharging are also inhibited by applying the VCC terminal to the CTL terminal externally. At this time, the VMP and VCC terminals are shorted by the RVCM resistor. When the CTL terminal becomes equal to VSS potential, charging and discharging are enabled and go back to their appropriate conditions for the battery voltages. Caution Please note unexpected behavior might occur when electrical potential difference between the CTL pin ('L' level) and VSS is generated through the external filter (RVSS and CVSS) as a result of input voltage fluctuations. This function is used to recharge the three serially-connected batteries after they self-discharge to 0 V. When the 0 V charging start voltage (V0CHAR) or higher is applied to between VMP and VSS by connecting the charger, the charging FET gate is fixed to VSS potential. When the voltage between the gate sources of the charging FET becomes equal to or higher than the turn-on voltage by the charger voltage, the charging FET turns on to start charging. At this time, the discharging FET turns off and the charging current flows through the internal parasitic diode in the discharging FET. If all the battery voltages become equal to or higher than the over discharge release voltage (V DU), the normal condition returns. Caution: In the products without 0 V battery charging function, the resistance between VCC and VMP and between VSS and VMP are lower than the products with 0 V battery charging function. It causes to that over charge detection voltage increases by the drop voltage of R5 (see Figure 9 for a connection example) with sink current at VMP. The COP output is undefined below 2.0 V on VCC-VSS voltage in the products without 0 V battery charging function.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.3.2_10 Seiko Instruments Inc. 16 Voltage temperature factor Voltage temperature factor 1 indicates over charge detection voltage, over charge release voltage, over discharge detection voltage, and over discharge release voltage. Voltage temperature factor 2 indicates over current detection voltage. The Voltage temperature factors 1 and 2 are expressed by the oblique line parts in Figure 5. VCU25 Ex. Voltage temperature factor of over charge detection voltage −20 25 +0.1 mV/°C VCU [V] VCU25 is the over charge detection voltage at 25°C
70 Ta [°C]
−0.1 mV/°C Figure 5
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.3.2_10 Seiko Instruments Inc. 18 3. Over current detection Hi-z VCU VCD VDU VDD Battery voltage DOP terminal VCC V SS VSS COP terminal VMP terminal Charger connected Delay tIOV1 Delay tIOV2 Load connected Mode c f c f c f c c CTL terminal VSSÆVCC VCC VIOV1 VIOV2 VIOV3 Delay tIOV3 Inhibit charging and discharging Hi-z Hi-z Hi-z CTL terminal V CCÆVSS *1. cNormal mode, dOver charge mode, eOver discharge mode, fOver current mode Remark The charger is assumed to charge with a constant current. VCHA indicates the open voltage of the charger. V1, V2, and V3 batteries Figure 8
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK Rev.3.2_10 S-8233A Series Seiko Instruments Inc. 19 Battery Protection IC Connection Example EB+ EB- S-8233A series VSS DOP CTL VC2 COP VMP VC1 CCT COVT CDT Over charge delay time setting Over current delay time setting Over discharge delay time setting Battery 1 Battery 3 Battery 2 VCC CD1 CD3 CD2 Nch open drain R11 R13 R12 FET-A FET1 FET3 FET2 GND: Normal operation Floating: Inhibit charging and discharging. 10 KΩ 1 KΩ 1 MΩ High: Inhibit over discharge detection. FET-C FET-B Figure 9 [Description of Figure 9] z R11, R12, and R13 are used to adjust the batte ry conditioning current. The conditioning current during over charge detection is given by Vcu (over charge detection voltage)/R (R: resistance). To disable the conditioning function, open CD1, CD2, and CD3. z The over charge detection delay time (t CU1 to tCU3), over discharge detection delay time (tDD1 to tDD3), and over current detection delay time (tIOV1) are changed with external capacitors (C4 to C6). See the electrical characteristics. z R6 is a pull-up resistor that turns FET-B off when the COP terminal is opened. Connect a 100 kΩ to 1 MΩ resistor. z R5 is used to protect the IC if the charge r is connected in reverse. Connect a 10 kΩ to 50 kΩ resistor. z If capacitor C6 is absent, rush current occurs when a capacitive load is connected and the IC enters the over current mode. C6 must be connected to prevent it. z If capacitor C5 is not connected, the IC may enter the over discharge condition due to variations of battery voltage when the over current occurs. In this case, a charger must be connected to return to the normal condition. To prevent this, connect an at least 0.01 µF capacitor to C5. z If a leak current flows between the delay capaci tor connection terminal (CCT, CDT, or COVT) and VSS, the delay time increases and an error occurs. The leak current must be 100 nA or less. z Over discharge detection can be disabled by us ing FET-C. The FET-C off leak must be 0.1 µA or less. If over discharge is inhibited by using this FET, the current consumption does not fall below 0.1 µA even when the battery voltage drops and the IC enters the over discharge detection mode. z R1, R2, and R3 must be 1 k Ω or less. z R7 is the protection of the CTL when the CTL terminal voltage higher than V CC voltage. Connect a 300 Ω to 5 kΩ resister. If the CTL terminal voltage never greater than the VCC voltage (ex. R7 connect to VSS), without R7 resistance is allowed .
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.3.2_10 Seiko Instruments Inc. 20 Caution 1. The above constants may be changed without notice. 2. If any electrostatic discharge of 2000 V or higher is not applied to the S-8233A series with a human body model, R1, R2, R3, C1, C2, and C3 are unnecessary. 3. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant do not guarantee proper operation. Perform through evaluation using the actual application to set the constant. Precautions z If a charger is connected in the over discharge condition and one of the battery voltages becomes equal to or higher than the over charge release voltage (VCU) before the battery voltage which is below the over discharge detection voltage (VDD) becomes equal to or higher than the over discharge release voltage (VDU), the over discharge and over charge conditions are entered and the charging and discharging FETs turn off. Both charging and discharging are disabled. If the battery voltage which was higher than the over charge detection voltage (VCU) falls to the over charge release voltage (VCD) due to internal discharging, the charging FET turns on. If the charger is detached in the over charge and over discharge condition, the over charge condition is released, but the over discharge condition remains. If the charger is connected again, the battery condition is monitored after that. The charging FET turns off after the over charge detection delay time, the over charge and over discharge conditions are entered. z If any one of the battery voltages is equal to or lower than the over discharge release voltage (VDU) when they are connected for the first time, the normal condition may not be entered. If the VMP terminal voltage is made equal to or higher than the VCC voltage (if a charger is connected), the normal condition is entered. z If the CTL terminal floats in power-down mode, it is not pulled up in the IC, charging and discharging may not be inhibited. However, the over discharge condition becomes effective. If the charger is connected, the CTL terminal is pulled up, and charging and discharging are inhibited immediately. z Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. z SII claims no responsibility for any disputes arisin g out of or in connection with any infringement by products including this IC of patents owned by a third party.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK Rev.3.2_10 S-8233A Series Seiko Instruments Inc. 21 Characteristics (typical characteristics) 1. Detection voltage temperature characteristics 4.15 4.25 4.35 -40 -20 0 20 40 60 80 100 Ta(°C) VCU (V) Overcharge detection voltage vs. temperature VCU=4.25[V] 4.00 4.10 4.20 -40 -20 0 20 40 60 80 100 VCD=4.10[V] Ta(°C) VCD (V) Overcharge release voltage vs. temperature 2.25 2.35 2.45 -40 -20 0 20 40 60 80 100 VDD=2.35[V] Ta(°C) VDD (V) Overdischarge detection voltage vs. temperature 2.75 2.85 2.95 -40 -20 0 20 40 60 80 100 VDU=2.85[V] Ta(°C) VDU (V) Overdischarge release voltage vs. temperature 0.25 0.30 0.35 -40 -20 0 20 40 60 80 100 VIOV1=0.3 [V] Ta(°C) VIOV1 (V) Overcurrent1 detection voltage vs. temperature 0.55 0.60 0.65 -40 -20 0 20 40 60 80 100 VIOV2=0.6 [V] Ta(°C) VIOV2 (V) Overcurrent2 detection voltage vs. temperature
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.3.2_10 Seiko Instruments Inc. 22 2. Current consumption temperature characteristics -40 -20 0 20 40 60 80 100 VCC=10.5 [V] Ta(°C) IOPE (uA) Current consumption vs. temperature in normal mode 0.0 0.5 1.0 -40 -20 0 20 40 60 80 100 VCC=4.5 [V] Ta(°C) IPDN (nA) Current consumption vs. temperature in power-down mode 3. Delay time temperature characteristics tCU (s) Overcharge detection time vs. temperature 0.5 1.0 1.5 -40 -20 0 20 40 60 80 100 C=0.47[uF] VCC=11.5 [V] Ta(°C) -40 -20 0 20 40 60 80 100 C=0.1[uF] VCC=8.5 [V] Ta(°C) tDD (ms) Overdischarge detection time vs. temperature -40 -20 0 20 40 60 80 100 C=0.1[uF] VCC=10.5 [V] Ta(°C) tIOV1 (ms) Overcurrent1 detection time vs. temperature Overcurrent2 detection time vs. temperature -40 -20 0 20 40 60 80 100 Ta(°C) tIOV2 (ms) VCC=10.5 [V]
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK Rev.3.2_10 S-8233A Series Seiko Instruments Inc. 23 0.10 0.25 0.40 -40 -20 0 20 40 60 80 100 Ta(°C) tIOV3 (ms) Overcurrent3 (load short) detection time vs. temperature VCC=6.0 [V] 4. Delay time vs. power supply voltage 0.5 1.0 3 6 9 12 15 VCC(V) tIOV3(ms) Ta =25(°C) Over current 3 (load short) detection time vs. power supply voltage Caution Please design all applications of the S-8233A Series with safety in mind.
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