S8230A

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www.sii-ic.com BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK © Seiko Instruments Inc., 2013-2015 Rev.2.3_00 Seiko Instruments Inc. 1 The S-8230A/B Series is a protection IC for 1-cell lithi um-ion / lithium polymer rechargeable batteries and includes high-accuracy voltage detection circuits and delay circuits. The S-8230A/B Series is suitable for protecting 1-cell lit hium-ion / lithium polymer rechargeable battery packs from overcharge, overdischarge, overcurrent, and controlling discharge by external signal.  Features

• High-accuracy voltage detection circuit Overcharge detection voltage 3.5 V to 4.5 V (5 mV step) Accuracy ±20 mV (Ta = +25°C) Accuracy ±25 mV (Ta = −10°C to +60°C) Overcharge release voltage 3.1 V to 4.5 V *1 Accuracy ±30 mV Overdischarge detection voltage 2.0 V to 3.4 V (10 mV step) Accuracy ±35 mV Overdischarge release voltage 2.0 V to 3.4 V *2 Accuracy ±50 mV Discharge overcurrent detection voltage 0. 05 V to 0.20 V (10 mV step) Accuracy ±10 mV Load short-circuiting detection voltage 0.5 V (fixed) Accuracy ±100 mV Charge overcurrent detection voltage −0.20 V to −0.05 V (25 mV step) Accuracy ±15 mV −0.16 V to −0.08 V (40 mV step)
• Detection delay times are generated only by an internal circuit (External capacitors are unnecessary). Accuracy ±20%
• Discharge control function CTL pin control logic is selectable: Active "H", active "L" CTL pin internal resistance connection is selectable: Pull-up, pull-down CTL pin internal resistance value is selectable: 1.0 MΩ, 2.5 MΩ, 5.0 MΩ Discharge inhibition status latch function is selectable: Available, unavailable
• 0 V battery charge function is selectable: Available, unavailable
• Power-down function is selectable: Available, unavailable
• Release condition of discharge overcurrent status is selectable: Load disconnection, charger connection
• High-withstand voltage device is used for charger connection pins: VM pin and CO pin: Absolute maximum rating 28 V
• Wide operation temperature range: Ta = −40°C to +85°C
• Low current consumption During operation: 2.8 μA typ., 5.5 μA max. (Ta = +25°C) During power-down: 0.1 μA max. (Ta = +25°C)
• Lead-free (Sn 100%), halogen-free *1. Overcharge release voltage = Overcharge detection voltage − Overcharge hysteresis voltage (Overcharge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.4 V in 50 mV step.) *2. Overdischarge release voltage = Overdischarge detection voltage + Overdischarge hysteresis voltage (Overdischarge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.7 V in 100 mV step.)  Applications
• Lithium-ion rechargeable battery pack
• Lithium polymer rechargeable battery pack  Package
• SNT-6A

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 2  Block Diagram Discharge overcurrent detection comparator Control logic Delay circuit Oscillator VM VSS VDD CTL CO DO Overcharge detection comparator Overdischarge detection comparator Load short-circuiting detection comparator Charge overcurrent detection comparator Pull-up / pull-down selection circuit Remark All the diodes shown in the figure are parasitic diodes. Figure 1

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 3  Product Name Structure 1. Product name S-8230 x xx - I6T1 U Package abbreviation and IC packing specifications *1 I6T1: SNT-6A, Tape Serial code*2 Sequentially set from AA to ZZ Environmental code U: Lead-free (Sn 100%), halogen-free Discharge inhibition status latch function A: Unavailable B: Available *1. Refer to the tape drawing. *2. Refer to "3. Product name list". 2. Package Table 1 Package Drawing Codes Package Name Dimension Tape Reel Land SNT-6A PG006-A-P-SD PG006-A-C-SD PG006-A-R-SD PG006-A-L-SD

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 4 3. Product name list 3. 1 SNT-6A 3. 1. 1 S-8230A Series Table 2 Product Name Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] Over- discharge Detection Voltage [VDL] Over- discharge Release Voltage [VDU] Discharge Overcurrent Detection Voltage [VDIOV] Charge Overcurrent Detection Voltage [VCIOV] Delay Time Combination*1 Function Combination*2 *1. Refer to Table 4 about the details of the delay time combinations. *2. Refer to Table 6 about the details of the function combinations. Remark Please contact our sales office for the products with detection voltage value other than those specified above. 3. 1. 2 S-8230B Series Table 3 Product Name Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] Over- discharge Detection Voltage [VDL] Over- discharge Release Voltage [VDU] Discharge Overcurrent Detection Voltage [VDIOV] Charge Overcurrent Detection Voltage [VCIOV] Delay Time Combination*1 Function Combination*2 *1. Refer to Table 4 about the details of the delay time combinations. *2. Refer to Table 6 about the details of the function combinations. Remark Please contact our sales office for the products with detection voltage value other than those specified above.

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 5 Table 4 Delay Time Combination Overcharge Detection Delay Time [tCU] Overdischarge Detection Delay Time [tDL] Discharge Overcurrent Detection Delay Time [tDIOV] Load Short-circuiting Detection Delay Time [tSHORT] Charge Overcurrent Detection Delay Time [tCIOV] Discharge Inhibition Delay Time [tCTL] (1) 1.0 s 128 ms 16 ms 280 μs 8 ms 256 ms (2) 1.0 s 128 ms 16 ms 1 ms 8 ms 256 ms (3) 1.0 s 32 ms 8 ms 280 μs 8 ms 256 ms (4) 1.0 s 128 ms 32 ms 1 ms 8 ms 256 ms (5) 1.0 s 64 ms 8 ms 280 μs 8 ms 256 ms Remark The delay times can be changed within the range listed in Table 5. For details, please contact our sales office. Table 5 Delay Time Symbol Selection Range Remark Overcharge detection delay time tCU 256 ms 512 ms 1.0 s*1 Select a value from the left. Overdischarge detection delay time t DL 32 ms 64 ms*1 128 ms Select a value from the left. Discharge overcurrent detection delay time t DIOV 4 ms 8 ms*1 16 ms Select a value from the left. Load short-circuiting detection delay time t SHORT 280 μs*1 530 μs 1 ms Select a value from the left. Charge overcurrent detection delay time t CIOV 4 ms 8 ms*1 16 ms Select a value from the left. Discharge inhibition delay time tCTL 64 ms 128 ms 256 ms*1 Select a value from the left. *1. This value is the delay time of the standard products. Table 6 Function Combination CTL Pin Discharge Inhibition Status Latch Function *4

0 V Battery

Function*5 Power- down Function*6 Release Condition of Discharge Overcurrent Status*7 Control Logic*1 Internal Resistance Connection*2 Internal Resistance Value*3 [RCTL] (1) Active "L" Pull-down 1.0 MΩ Available Available Available Load disconnection (2) Active "L" Pull-up 1.0 MΩ Available Unavailable Available Charger connection (3) Active "L" Pull-up 5.0 MΩ Unavailable Available Available Load disconnection (4) Active "L" Pull-down 1.0 MΩ Available Unavailable Available Charger connection (5) Active "L" Pull-up 5.0 MΩ Unavailable Available Unavailable Load disconnection (6) Active "H" Pull-down 5.0 MΩ Unavailable Unavailable Available Load disconnection Caution The combination of CTL pin control logic active "H" and CTL pin internal resistance connection "pull-up" worsens the accuracy of overcharge detection voltage. Therefore, this combination can not be set up. *1. CTL pin control logic active "H" / active "L" is selectable. *2. CTL pin internal resistance connection "pull-up" / "pull-down" is selectable. *4. Discharge inhibition status latch function "available" / "unavailable" is selectable. *5. 0 V battery charge function "available" / "unavailable" is selectable. *6. Power-down function "available" / "unavailable" is selectable. *7. Release condition of discharge overcurrent status "load disconnection" / "charger connection" is selectable. Remark Please contact our sales office for the products with function combinations other than those specified above.

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 6  Pin Configuration 1. SNT-6A Top view Figure 2 Table 7 Pin No. Symbol Description

1 CTL Discharge control pin

2 CO Connection pin of charge control FET gate

(CMOS output)

3 DO Connection pin of discharge control FET gate

(CMOS output)

4 VSS Input pin for negative power supply

5 VDD Input pin for positive power supply

6 VM Voltage detection pin between VM pin and VSS pin

(Overcurrent / charger detection pin)

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 7  Absolute Maximum Ratings Table 8 (Ta = +25°C unless otherwise specified) Item Symbol Applied pin Abso lute Maximum Rating Unit Input voltage between VDD pin and VSS pin V DS VDD VSS − 0.3 to VSS + 12 V VM pin input voltage VVM VM V DD − 28 to VDD + 0.3 V DO pin output voltage VDO DO V SS − 0.3 to VDD + 0.3 V CO pin output voltage VCO CO V VM − 0.3 to VDD + 0.3 V CTL pin input voltage VCTL CTL V SS − 0.3 to VDD + 0.3 V Power dissipation PD − 400*1 mW Operation ambient temperature Topr − −40 to +85 °C Storage temperature Tstg − −55 to +125 °C *1. When mounted on board [Mounted board] (1) Board size: 114.3 mm × 76.2 mm × t1.6 mm (2) Board name: JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 0 50 100 150 400 200 700 300 100 500 600 Power Dissipation (PD) [mW] Ambient Temperature (Ta) [°C] Figure 3 Power Dissipation of Package (When Mounted on Board)

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 8  Electrical Characteristics 1. Ta = +25°C Table 9 (Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection Voltage Overcharge detection voltage VCU − V CU − 0.020 V CU V CU + 0.020 V 1 Ta = −10°C to +60°C*1 V CU − 0.025 V CU V CU + 0.025 V 1 Overcharge release voltage VCL VCL ≠ VCU VCL − 0.030 VCL VCL + 0.030 V1 VCL = VCU V CL − 0.025 V CL V CL + 0.020 V 1 Overdischarge detection voltage VDL − V DL − 0.035 V DL V DL + 0.035 V 2 Overdischarge release voltage VDU VDL ≠ VDU V DU − 0.050 V DU V DU + 0.050 V 2 VDL = VDU V DU − 0.035 V DU V DU + 0.035 V 2 Discharge overcurrent detection voltage V DIOV − V DIOV − 0.010 V DIOV V DIOV + 0.010 V 2 Load short-circuiting detection voltage V SHORT − 0.40 0.50 0.60 V 2 Charge overcurrent detection voltage V CIOV − V CIOV − 0.015 V CIOV V CIOV + 0.015 V 2

0 V Battery Charge Function

0 V battery charge starting charger voltage V 0CHA 0 V battery charge function

"available" 0.0 0.7 1.0 V 2

0 V battery charge inhibition battery voltage V 0INH 0 V battery charge function

"unavailable" 1.0 1.2 1.4 V 2 Internal Resistance Resistance between VM pin and VDD pin R VMD − 100 300 900 kΩ 3 Resistance between VM pin and VSS pin R VMS − 10 20 40 kΩ 3 CTL pin internal resistance RCTL − R CTL × 0.45 RCTL RCTL × 1.75 M Ω 3 Input Voltage Operation voltage between VDD pin and VSS pin V DSOP1 − 1.5 − 6.5 V − Operation voltage between VDD pin and VM pin V DSOP2 − 1.5 − 28 V − CTL pin voltage "H" VCTLH − − − V DD × 0.9 V 2 CTL pin voltage "L" VCTLL − V DD × 0.1 − − V2 Input Current Current consumption during operation I OPE − 1.0 2.8 5.5 μA3 Current consumption during power-down I PDN − − − 0.1 μA3 Current consumption during overdischarge I OPED − − − 4.0 μA3 Current consumption during discharge inhibition I OPEC − 1.0 2.8 5.5 μA 3 Output Resistance CO pin resistance "H" RCOH − 5 10 20 kΩ 4 CO pin resistance "L" RCOL − 5 10 20 kΩ 4 DO pin resistance "H" RDOH − 5 10 20 kΩ 4 DO pin resistance "L" RDOL − 5 10 20 kΩ 4 Delay Time Overcharge detection delay time tCU − t CU × 0.8 t CU t CU × 1.2 − 5 Overdischarge detection delay time t DL − t DL × 0.8 t DL t DL × 1.2 − 5 Discharge overcurrent detection delay time t DIOV − t DIOV × 0.8 t DIOV t DIOV × 1.2 − 5 Load short-circuiting detection delay time t SHORT − t SHORT × 0.8 t SHORT t SHORT × 1.2 − 5 Charge overcurrent detection delay time t CIOV − t CIOV × 0.8 t CIOV t CIOV × 1.2 − 5 Discharge inhibition delay time tCTL − t CTL × 0.8 t CTL t CTL × 1.2 − 5 *1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production.

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 9 2. Ta = −40°C to +85°C*1 Table 10 (Ta = −40°C to +85°C*1 unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection Voltage Overcharge detection voltage VCU − V CU − 0.045 V CU V CU + 0.030 V 1 Overcharge release voltage VCL VCL ≠ VCU V CL − 0.070 V CL V CL + 0.040 V 1 VCL = VCU V CL − 0.050 V CL V CL + 0.030 V 1 Overdischarge detection voltage VDL − V DL − 0.070 V DL V DL + 0.045 V 2 Overdischarge release voltage VDU VDL ≠ VDU V DU − 0.090 V DU V DU + 0.060 V 2 VDL = VDU V DU − 0.070 V DU V DU + 0.045 V 2 Discharge overcurrent detection voltage V DIOV − V DIOV − 0.010 V DIOV V DIOV + 0.010 V 2 Load short-circuiting detection voltage V SHORT − 0.40 0.50 0.60 V 2 Charge overcurrent detection voltage V CIOV − V CIOV − 0.015 V CIOV V CIOV + 0.015 V 2 "available" 0.0 0.7 1.5 V 2 "unavailable" 0.9 1.2 1.5 V 2 Internal Resistance Resistance between VM pin and VDD pin R VMD − 78 300 1310 kΩ 3 Resistance between VM pin and VSS pin R VMS − 7.2 20 44 kΩ 3 CTL pin internal resistance RCTL − R CTL × 0.27 R CTL R CTL × 3.50 M Ω 3 Input Voltage Operation voltage between VDD pin and VSS pin V DSOP1 − 1.5 − 6.5 V − Operation voltage between VDD pin and VM pin V DSOP2 − 1.5 − 28 V − CTL pin voltage "H" VCTLH − − − V DD × 0.95 V 2 CTL pin voltage "L" VCTLL − V DD × 0.05 − − V2 Input Current Current consumption during operation I OPE − 0.7 2.8 6.0 μA3 Current consumption during power-down I PDN − − − 0.15 μA3 Current consumption during overdischarge I OPED − − − 4.2 μA3 Current consumption during discharge inhibition I OPEC − 0.7 2.8 6.0 μA3 Output Resistance CO pin resistance "H" RCOH − 2.4 10 30 kΩ 4 CO pin resistance "L" RCOL − 2.4 10 30 kΩ 4 DO pin resistance "H" RDOH − 2.4 10 30 kΩ 4 DO pin resistance "L" RDOL − 2.4 10 30 kΩ 4 Delay Time Overcharge detection delay time tCU − t CU × 0.6 t CU t CU × 1.6 − 5 Overdischarge detection delay time t DL − t DL × 0.6 t DL t DL × 1.6 − 5 Discharge overcurrent detection delay time t DIOV − t DIOV × 0.6 t DIOV t DIOV × 1.6 − 5 Load short-circuiting detection delay time t SHORT − t SHORT × 0.6 t SHORT t SHORT × 1.6 − 5 Charge overcurrent detection delay time t CIOV − t CIOV × 0.6 t CIOV t CIOV × 1.6 − 5 Discharge inhibition delay time tCTL − t CTL × 0.6 t CTL t CTL × 1.6 − 5 *1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production.

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 10  Test Circuits When CTL pin control logic is active "H", SW1 and SW3 are turned off, SW 2 and SW4 are turned on. When CTL pin control logic is active "L", SW1 and SW3 are turned on, SW2 and SW4 are turned off. Caution Unless otherwise specified, the output voltage levels "H" and "L" at CO pin (V CO) and DO pin (VDO) are judged by the threshold voltage (1.0 V) of the N-channel FET. Judge the CO pin level with respect to V VM and the DO pin level with respect to VSS. 1. Overcharge detection voltage, overcharge release voltage (Test circuit 1) Overcharge detection voltage (VCU) is defined as the voltage V1 at which V CO goes from "H" to "L" when the voltage V1 is gradually increased from the starting condition of V1 = 3.4 V. Overcharge release voltage (V CL) is defined as the voltage V1 at which V CO goes from "L" to "H" when the voltage V1 is then gradually decreased. Overcharge hysteresis voltage (VHC) is defined as the difference between VCU and VCL. 2. Overdischarge detection voltage, overdischarge release voltage (Test circuit 2) Overdischarge detection voltage (V DL) is defined as the voltage V1 at which V DO goes from "H" to "L" when the voltage V1 is gradually decreased from the starting conditions of V1 = 3.4 V, V2 = V5 = 0 V. Overdischarge release voltage (V DU) is defined as the voltage V1 at which V DO goes from "L" to "H" when the voltage V1 is then gradually increased. Overdischarge hysteresis voltage (VHD) is defined as the difference between VDU and VDL. 3. Discharge overcurrent detection voltage (Test circuit 2) Discharge overcurrent detection voltage (VDIOV) is defined as the voltage V2 whose delay time for changing VDO from "H" to "L" is discharge overcurrent detection delay time (t DIOV) when the voltage V2 is increased from the starting conditions of V1 = 3.4 V, V2 = V5 = 0 V. 4. Load short-circuiting detection voltage (Test circuit 2) Load short-circuiting detection voltage (VSHORT) is defined as the voltage V2 whose delay time for changing V DO from "H" to "L" is load short-circuiting detection delay time (t SHORT) when the voltage V2 is increased from the starting conditions of V1 = 3.4 V, V2 = V5 = 0 V. 5. Charge overcurrent detection voltage (Test circuit 2) Charge overcurrent detection voltage (V CIOV) is defined as the voltage V2 whose delay time for changing V CO from "H" to "L" is charge overcurrent detection delay time (t CIOV) when the voltage V2 is decreased from the starting conditions of V1 = 3.4 V, V2 = V5 = 0 V. 6. Current consumption during operation (Test circuit 3) The current consumption during operation (I OPE) is the current that flows through the VDD pin (I DD) under the set conditions of V1 = 3.4 V, V2 = V5 = 0 V. 7. Current consumption during power-down, current consumption during overdischarge (Test circuit 3) 7. 1 With power-down function The current consumption during power-down (IPDN) is IDD under the set conditions of V1 = V2 = 1.5 V, V5 = 0 V. 7. 2 Without power-down function The current consumption during overdischarge (I OPED) is I DD under the set conditions of V1 = V2 = 1.5 V, V5 = 0 V.

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 11 8. Current consumption during discharge inhibition (Test circuit 3) 8. 1 CTL pin control logic active "L" and CTL pin internal resistance connection "pull-up" Current consumption during discharge inhibition (I OPEC) is the difference of absolute value between I DD and ICTL under the set conditions of V1 = V2 = V5 = 3.4 V. 8. 2 Other function combinations Current consumption during discharge inhibition (IOPEC) is IDD under the set conditions of V1 = V2 = V5 = 3.4 V. 9. Resistance between VM pin and VDD pin (Test circuit 3) Resistance between VM pin and VDD pin is RVMD under the set conditions of V1 = 1.8 V, V2 = V5 = 0 V. 10. Resistance between VM pin and VSS pin (Relea se condition of discharge overcurrent status "load disconnection") (Test circuit 3) Resistance between VM pin and VSS pin is R VMS under the set conditions of V1 = 3.4 V, V2 = 1.0 V, V5 = 0 V. 11. CTL pin internal resistance (Test circuit 3) 11. 1 CTL pin control logic active "H" and CTL pin internal resistance connection "pull-down" Resistance between CTL pin and VSS pin is RCTL under the set conditions of V1 = V5 = 3.4 V, V2 = 0 V. 11. 2 CTL pin control logic active "L" and CTL pin internal resistance connection "pull-up" Resistance between CTL pin and VDD pin is RCTL under the set conditions of V1 = V5 = 3.4 V, V2 = 0 V. 11. 3 CTL pin control logic active "L" and CTL pin internal resistance connection "pull-down" Resistance between CTL pin and VSS pin is RCTL under the set conditions of V1 = 3.4 V, V2 = V5 = 0 V. 12. CO pin resistance "H" (Test circuit 4) The CO pin resistance "H" (RCOH) is the resistance between VDD pin and CO pin under the set conditions of V1 = 3.4 V, V2 = 0 V, V3 = 3.0 V. 13. CO pin resistance "L" (Test Circuit 4) The CO pin resistance "L" (RCOL) is the resistance between VM pin and CO pin under the set conditions of V1 = 4.6 V, V2 = 0 V, V3 = 0.4 V. 14. DO pin resistance "H" (Test circuit 4) The DO pin resistance "H" (RDOH) is the resistance between VDD pin and DO pin under the set conditions of V1 = 3.4 V, V2 = 0 V, V4 = 3.0 V. 15. DO pin resistance "L" (Test circuit 4) The DO pin resistance "L" (RDOL) is the resistance between VSS pin and DO pin under the set conditions of V1 = 1.8 V, V2 = 0 V, V4 = 0.4 V.

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 12 16. CTL pin voltage "H", CTL pin voltage "L" (Test circuit 2) 16. 1 CTL pin control logic active "H" The CTL pin voltage "H" (VCTLH) is defined as the voltage V5 at which VDO goes from "H" to "L" when the voltage V5 is gradually increased under the set conditions of V1 = 3.4 V, V2 = V5 = 0 V. After that, the CTL pin voltage "L" (VCTLL) is defined as the voltage V5 at which VDO goes from "L" to "H" after V5 is gradually decreased. 16. 2 CTL pin control logic active "L" The CTL pin voltage "L" (VCTLL) is defined as the voltage difference between the voltage V5 and the voltage V1 (V1 − V5) at which VDO goes from "H" to "L" when the voltage V5 is gradually increased under the set conditions of V1 = 3.4 V, V2 = V5 = 0 V. After that, the CTL pin voltage "H" (VCTLH) is defined as the voltage difference between V1 − V5 at which VDO goes from "L" to "H" after V5 is gradually decreased. 17. Overcharge detection delay time (Test circuit 5) The overcharge detection delay time (tCU) is the time needed for VCO to go to "L" after the voltage V1 increases and exceeds VCU under the set condition of V1 = 3.4 V, V2 = V5 = 0 V. 18. Overdischarge detection delay time (Test circuit 5) The overdischarge detection delay time (t DL) is the time needed for V DO to go to "L" after the voltage V1 decreases and falls below VDL under the set condition of V1 = 3.4 V, V2 = V5 = 0 V. 19. Discharge overcurrent detection delay time (Test circuit 5) tDIOV is the time needed for V DO to go to "L" after the voltage V2 increases and exceeds V DIOV under the set conditions of V1 = 3.4 V, V2 = V5 = 0 V. 20. Load short-circuiting detection delay time (Test circuit 5) tSHORT is the time needed for V DO to go to "L" after the voltage V2 increases and exceeds V SHORT under the set conditions of V1 = 3.4 V, V2 = V5 = 0 V. 21. Charge overcurrent detection delay time (Test circuit 5) tCIOV is the time needed for V CO to go to "L" after the voltage V2 decreases and falls below V CIOV under the set condition of V1 = 3.4 V, V2 = V5 = 0 V. 22. Discharge inhibition delay time (Test circuit 5) 22. 1 CTL pin control logic active "H" Discharge inhibition delay time (t CTL) is the time needed for V DO to go to "L" after the voltage V5 increases and exceeds VCTLH under the set conditions of V1 = 3.4 V, V2 = V5 = 0 V. 22. 2 CTL pin control logic active "L" Discharge inhibition delay time (t CTL) is the time needed for V DO to go to "L" after the voltage V5 increases and V1 − V5 falls below VCTLL under the set conditions of V1 = 3.4 V, V2 = V5 = 0 V.

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 13 23. 0 V battery charge starting charger voltage (0 V battery charge function "available") (Test circuit 2) The 0 V battery charge starting charger voltage (V 0CHA) is defined as absolute value of the voltage V2 at which V CO goes to "H" (VCO = VDD) when the voltage V2 is gradually decreased under the set condition of V1 = V2 = V5 = 0 V. 24. 0 V battery charge inhibition battery voltage (0 V battery charge function "unavailable") (Test circuit 2) The 0 V battery charge inhibition battery voltage (V 0INH) is defined as the voltage V1 at which V CO goes to "H" (V CO = VDD) when the voltage V1 is gradually increased under the set condition of V1 = V5 = 0 V, V2 = −4.0 V.

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 15  Operation Remark Refer to " Battery Protection IC Connection Example". 1. Normal status The S-8230A/B Series monitors the voltage of the battery connected between the VDD pin and VSS pin, the voltage between the VM pin and VSS pin and the voltage between the CTL pin an d VSS pin to control charging and discharging. 1. 1 CTL pin control logic active "H" When the battery voltage is in the range from the overdischarge detection voltage (V DL) to the overcharge detection voltage (V CU), and the VM pin voltage is in the range fr om the charge overcurrent detection voltage (VCIOV) to the discharge overcurrent detection voltage (V DIOV), the S-8230A/B Series turns both the charge and discharge control FETs on if the CTL pin voltage is equal to or lower than the CTL pin voltage "L" (V CTLL). This condition is called the normal status, and in this condition charging and discharging can be carried out freely. The resistance between the VM pin and VDD pin (R VMD) and the resistance between the VM pin and VSS pin (RVMS) are not connected in the normal status. 1. 2 CTL pin control logic active "L" When the battery voltage is in the range from the overdischarge detection voltage (V DL) to the overcharge detection voltage (V CU), and the VM pin voltage is in the range fr om the charge overcurrent detection voltage (VCIOV) to the discharge overcurrent detection voltage (V DIOV), the S-8230A/B Series turns both the charge and discharge control FETs on if the CTL pin voltage is equal to or higher than the CTL pin voltage "H" (V CTLH). This condition is called the normal status, and in this condition charging and discharging can be carried out freely. The resistance between the VM pin and VDD pin (R VMD) and the resistance between the VM pin and VSS pin (RVMS) are not connected in the normal status. Caution When the battery is connected for the first time, the S-8230A/B Series may not be in the normal status. In this case, short the VM pin and VSS pin, or set the VM pin voltage at the level of V CIOV or more and at the level of V DIOV or less by connecting the charger. The S-8230A/B Series then becomes the normal status. 2. Overcharge status 2. 1 VCL ≠ VCU (Product in which overcharge release voltage differs from overcharge detection voltage) When the battery voltage becomes higher than V CU during charging in the normal status and detection continues for the overcharge detection delay time (t CU) or longer, the S-8230A/B Series turns the charge control FET off to stop charging. This condition is called the overcharge status. R VMD and RVMS are not connected in the overcharge status. The overcharge status is released in the following two cases. (1) In the case that the VM pin voltage is lower than V DIOV, the S-8230A/B Series releases the overcharge status when the battery voltage falls below overcharge release voltage (VCL). (2) In the case that the VM pin voltage is equal to or higher than V DIOV, the S-8230A/B Series releases the overcharge status when the battery voltage falls below VCU. When the discharge is started by connecting a load after the overcharge detection, the VM pin voltage rises by the V f voltage of the parasitic diode than the VSS pin volt age, because the discharge current flows through the parasitic diode in the charge control FET. If this VM pin voltage is equal to or higher than V DIOV, the S-8230A/B Series releases the overcharge status when the battery voltage is equal to or lower than VCU. Caution If the battery is charged to a voltage higher than V CU and the battery voltage does not fall below VCU even when a heavy load is connected, discharge overcurrent detection and load short-circuiting detection do not function until the battery voltage falls below V CU. Since an actual battery has an internal impedance of tens of m Ω, the battery voltage drops immediately after a heavy load that causes overcurrent is connected, and discharge overcurrent detection and load short-circuiting detection function.

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 16 2. 2 VCL = VCU (Product in which overcharge release voltage is the same as overcharge detection voltage) When the battery voltage becomes higher than V CU during charging in the normal status and detection continues for the overcharge detection delay time (t CU) or longer, the S-8230A/B Series turns the charge control FET off to stop charging. This condition is called the overcharge status. RVMD and RVMS are not connected in the overcharge status. The overcharge status is released in the following two cases. (1) In the case that the VM pin voltage is equal to or higher than V CIOV, and is lower than V DIOV, the S-8230A/B Series releases the overcharge status when the battery voltage falls below overcharge release voltage (VCL). (2) In the case that the VM pin voltage is equal to or higher than V DIOV, the S-8230A/B Series releases the overcharge status when the battery voltage falls below VCU. The discharge is started by connecting a load after the overcharge detection, the VM pin voltage rises more than the VSS pin voltage due to the V f voltage of the parasitic diode, because the discharge current flows through the parasitic diode in the charge control FET. If this VM pin voltage is equal to or higher than V DIOV, the S-8230A/B Series releases the overcharge status when the battery voltage is equal to or lower than VCU. Caution 1. If the battery is charged to a voltage higher than V CU and the battery voltage does not fall below VCU even when a heavy load is connected, discharge overcurrent detection and load short- circuiting detection do not function until the battery voltage falls below V CU. Since an actual battery has an internal impedance of tens of m Ω, the battery voltage drops immediately after a heavy load that causes overcurrent is connected, and discharge overcurrent detection and load short-circuiting detection function. 2. When a charger is connected after overcharge detection, the overcharge status is not released even if the battery voltage is below V CL. The overcharge status is released when the VM pin voltage goes over VCIOV by removing the charger. 3. Overdischarge status When the battery voltage falls below V DL during discharging in the normal status and the detection continues for the overdischarge detection delay time (t DL) or longer, the S-8230A/B Series turns the discharge control FET off to stop discharging. This condition is called the overdischarge status. In the overdischarge status, the VM pin and VDD pin are shorted by R VMD in the S-8230A/B Series. The VM pin voltage is pulled up by RVMD. When a battery in the overdischarge status is connected to a charger and provided that the VM pin voltage is lower than −0.7 V typ., the S-8230A/B Series releases the overdischarge status when the battery voltage reaches V DL or higher. When VM pin voltage is not lower than −0.7 V typ., the S-8230A/B Series releases the overdischarge status when the battery voltage reaches overdischarge release voltage (VDU) or higher. RVMS is not connected in the overdischarge status. 3. 1 With power-down function Under the overdischarge status, when voltage between the VDD pin and VM pin is 0.8 V typ. or lower, the power- down function works and the current consumption is reduced to the current consumption during power-down PDN). By connecting a charger, the power-down function is released when the VM pin voltage is 0.7 V typ. or lower.

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 17 4. Discharge overcurrent status (Discharge overcurrent, load short-circuiting) When a battery in the normal status is in the status where the VM pin voltage is equal to or higher than VDIOV because the discharge current is equal to or higher than the specified value and the status lasts for the discharge overcurrent detection delay time (t DIOV) or longer, the discharge control FET is turned off and discharging is stopped. This status is called the discharge overcurrent status. 4. 1 Release condition of discharge overcurrent status "load disconnection" In the discharge overcurrent status, t he VM pin and VSS pin are shorted by R VMS in the S-8230A/B Series. However, the VM pin voltage is the VDD pin voltage due to the load as long as the load is connected. When the load is disconnected, the VM pin voltage returns to the VSS pin voltage. If the VM pin voltage returns to V DIOV or lower, the S-8230A/B Series releases the discharge overcurrent status. RVMD is not connected in the discharge overcurrent status. 4. 2 Release condition of discharge overcurrent status "charger connection" In the discharge overcurrent status, the VM pin and VDD pin are shorted by RVMD in the S-8230A/B Series. If the VM pin voltage returns to V DIOV or lower by connecting a battery charger, the S-8230A/B Series releases the discharge overcurrent status. RVMS is not connected in the discharge overcurrent status. 5. Charge overcurrent status When a battery in the normal status is in the status where the VM pin voltage is equal to or lower than V CIOV because the charge current is equal to or higher than the specified value and the status lasts for the charge overcurrent detection delay time (t CIOV) or longer, the charge control FET is turned off and charging is stopped. This status is called the charge overcurrent status. The S-8230A/B Series releases the charge overcurrent status when the VM pin voltage returns to V CIOV or higher by removing the charger. The charge overcurrent detection does not function in the overdischarge status and the discharge inhibition status. RVMD and RVMS are not connected in the charge overcurrent status.

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 18 6. Discharge inhibition status 6. 1 CTL pin control logic active "H" When a battery in the normal status is in the status where CTL pin voltage is equal to or higher than CTL pin voltage "H" (VCTLH) and the status lasts for discharge inhibition delay time (t CTL) or longer, the discharge control FET is turned off and discharging is stopped. This status is called the discharge inhibition status. 6. 1. 1 Discharge inhibition status latch function "available" If CTL pin voltage is equal to or lower than CTL pin voltage "L" (V CTLL), the S-8230A/B Series releases discharge inhibition status when the VM pin voltage becomes equal to or lower than V DIOV by connecting a charger. 6. 1. 2 Discharge inhibition status latch function "unavailable" The S-8230A/B Series releases discharge inhibition status when the CTL pin voltage becomes equal to or lower than VCTLL. 6. 2 CTL pin control logic active "L" When a battery in the normal status is in the status where CTL pin voltage is equal to or lower than CTL pin voltage "L" (V CTLL) and the status lasts for discharge inhibition delay time (t CTL) or longer, the discharge control FET is turned off and discharging is stopped. This status is called the discharge inhibition status. 6. 2. 1 Discharge inhibition status latch function "available" If CTL pin voltage is equal to or higher than CTL pin voltage "H" (V CTLH), the S-8230A/B Series releases discharge inhibition status when the VM pin voltage becomes equal to or lower than V DIOV by connecting a charger. 6. 2. 2 Discharge inhibition status latch function "unavailable" The S-8230A/B Series releases discharge inhibition status when the CTL pin voltage becomes equal to or higher than VCTLH. In discharge inhibition status, if the battery voltage exceeds V CU by connecting a charger, the S-8230A/B Series releases discharge inhibition status. The CTL pin is shorted to the VDD pin or VSS pin by the CTL pin internal resistance (R CTL) in the S-8230A/B Series. When the voltage between the VDD pin and VM pin is 0.8 V typ. or lower in the overdischarge status, R CTL is disconnected and the input and output current to the CTL pin is cut off. The discharge control by the CTL pin does not function in the overcharge status and the charge overcurrent status. In the discharge inhibition status, the VM pin and VDD pin are shorted by RVMD in the S-8230A/B Series. 7. 0 V battery charge function "available" This function is used to recharge a connected battery whose voltage is 0 V due to self-discharge. When the 0 V battery charge starting charger voltage (V 0CHA) or a higher voltage is applied between the EB + pin and EB − pin by connecting a charger, the charge control FET gate is fixed to the VDD pin voltage. When the voltage between the gate and source of the charge control FET becomes equal to or higher than the threshold voltage due to the charger voltage, the charge control FET is turned on to start charging. At this time, the discharge control FET is off and the charge current flows through the internal parasitic diode in the discharge control FET. When the battery voltage becomes equal to or higher than V DU, the S-8230A/B Series enters the normal status. Caution 1. Some battery providers do not recommend charging for a completely self-discharged battery. Please ask the battery provider to determine whether to enable or inhibit the 0 V battery charge function. 2. The 0 V battery charge function has higher priority than the charge overcurrent detection function. Consequently, a product in which use of the 0 V battery charge function is enabled charges a battery forcibly and the charge overcurrent cannot be detected when the battery voltage is lower than V DL.

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 19 8. 0 V battery charge function "unavailable" This function inhibits recharging when a battery that is internally short-circuited (0 V battery) is connected. When the battery voltage is the 0 V battery charge inhibition battery voltage (V 0INH) or lower, the charge control FET gate is fixed to the EB − pin voltage to inhibit charging. When the battery voltage is V 0INH or higher, charging can be performed. Caution Some battery providers do not recommend charging for a completely self-discharged battery. Please ask the battery provider to determine whether to enable or inhibit the 0 V battery charge function. 9. Delay circuit The detection delay times are determined by dividing a clock of approximately 4 kHz by the counter. Remark tDIOV and t SHORT start when V DIOV is detected. When V SHORT is detected over t SHORT after V DIOV, the S-8230A/B Series turns the discharge control FET off within tSHORT from the time of detecting VSHORT. DO pin voltage VM pin voltage VDD VDD Time VDIOV VSS VSS VSHORT tSHORT Time tD 0 ≤ tD ≤ tSHORT Figure 9

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 20  Timing Chart 1. Overcharge detection, overdischarge detection VCU VDU (VDL + VHD) VDL VCL (VCU − VHC) Battery voltage VSS CO pin voltage VDD DO pin voltage VSS Charger connection Load connection Status*1 Overcharge detection delay time (tCU) VDIOV VSS VM pin voltage VDD VEB− VDD VCIOV VEB− Overdischarge detection delay time (tDL) *1. (1): Normal status (2): Overcharge status (3): Overdischarge status Remark The charger is assumed to charge with a constant current. Figure 10

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 21 2. Discharge overcurrent detection 2. 1 Release condition of discharge overcurrent status "load disconnection" VDD VSS VSHORT (1) (2) (1) (1) Load short-circuiting detection delay time (tSHORT) (2) VDIOV Discharge overcurrent detection dela y time (tDIOV) VCU VDU (VDL + VHD) VDL VCL (VCU − VHC) Battery voltage VSS CO pin voltage VDD DO pin voltage VSS Load connection Status*1 VM pin voltage VDD *1. (1): Normal status (2): Discharge overcurrent status Remark The charger is assumed to charge with a constant current. Figure 11

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 22 2. 2 Release condition of discharge overcurrent status "charger connection" VDD VSS VSHORT VDIOV VCU VDU (VDL + VHD) VDL VCL (VCU − VHC) Battery voltage VSS CO pin voltage VDD DO pin voltage VSS Load connection VM pin voltage VDD VCIOV Charger connection Load short-circuiting detection delay time (tSHORT) VEB− Status*1 Discharge overcurrent detection delay time (tDIOV) *1. (1): Normal status (2): Discharge overcurrent status Remark The charger is assumed to charge with a constant current. Figure 12

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 23 3. Charge overcurrent detection VDD DO pin voltage VSS VDD VSS CO pin voltage VDD VSS VM pin voltage VCIOV Status*1 (3) (1) Charger connection VEB− VEB− Charge overcurrent detection delay time (tCIOV) VCU VDU (VDL + VHD) VDL VCL (VCU − VHC) Battery voltage (2) Load connection (1) (1) (2) Overdischarge detection delay time (tDL) Charge overcurrent detection delay time (t CIOV) *1. (1): Normal status (2): Charge overcurrent status (3): Overdischarge status Remark The charger is assumed to charge with a constant current. Figure 13

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 24 4. Discharge inhibition operation 4. 1 Discharge inhibition status latch function "available" VDD DO pin voltage VSS VDD VSS CO pin voltage VDD VSS VM pin voltage VCIOV Status*1 (1)(1) Charger connection VEB− VEB− VCU VDU (VDL + VHD) VDL VCL (VCU − VHC) Battery voltage (2) Load connection (2) (3) (2) VDD VSS CTL pin voltage (Active "H") VDIOV (1) tCTL (1) tCTL Discharge inhibition delay time (tCTL) Overcharge detection delay time (tCU) VCTLH VCTLL VDD VCTLH VCTLL VSS CTL pin voltage (Active "L") *1. (1): Normal status (2): Discharge inhibition status (3): Overcharge status Remark The charger is assumed to charge with a constant current. Figure 14

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 25 4. 2 Discharge inhibition status latch function "unavailable" VDD DO pin voltage VSS VDD VSS CO pin voltage VDD VSS VM pin voltage VCIOV Status*1 (1)(1) Charger connection VEB− VEB− VCU VDU (VDL + VHD) VDL VCL (VCU − VHC) Battery voltage (2) Load connection (2) (3) (2) VDD VSS CTL pin voltage (Active "H") VDIOV (1) tCTL (1) tCTL Discharge inhibition delay time (tCTL) Overcharge detection delay time (tCU) VCTLH VCTLL VDD VCTLH VCTLL VSS CTL pin voltage (Active "L") *1. (1): Normal status (2): Discharge inhibition status (3): Overcharge status Remark The charger is assumed to charge with a constant current. Figure 15

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 26  Battery Protection IC Connection Example Battery C1 VSS DO VDD CO VM S-8230A/B Series FET1 FET2 EB− EB+ CTL External input Figure 16 Table 11 Constants for External Components Symbol Part Purpose Min. Typ. Max. Remark FET1 N-channel MOS FET Discharge control − − − Threshold voltage ≤ Overdischarge detection voltage*1 Gate to source withstand voltage ≥ Charger voltage*2 FET2 N-channel MOS FET Charge control − − − Threshold voltage ≤ Overdischarge detection voltage*1 Gate to source withstand voltage ≥ Charger voltage*2 R1 Resistor ESD protection, For power fluctuation 150 Ω 330 Ω 1 k Ω Resistance should be as small as possible to avoid worsening the overcharge detection accuracy due to current consumption. C1 Capacitor For power fluctuation 0.068 μF0 . 1 μF 1.0 μF Connect a capacitor of 0.068 μF or higher between VDD pin and VSS pin. *4 R2 Resistor Protection for reverse connection of a charger 300 Ω 2 k Ω 4 k Ω Select as large a resistance as possible to prevent current when a charger is connected in reverse. R3 Resistor ESD protection 1 k Ω − 10 k Ω Connect a resistor of 1 kΩ or more to R3 for ESD protection.*6 *1. If the threshold voltage of an FET is low, the FET may not cut the charge current. If an FET with a threshold voltage equal to or higher than the overdischarge detection volt age is used, discharging may be stopped before overdischarge is detected. *2. If the withstand voltage between the gate and source is lower than the charger voltage, the FET may be destroyed. *3. An accuracy of overcharge detection voltage is guaranteed by R1 = 330 Ω. Connecting resistors with other values worsen the accuracy. In case of connecting a larger resi stor to R1, the voltage between the VDD pin and VSS pin may exceed the absolute maximum rating because the current flows to the S-8230A/B Series from the charger due to reverse connection of charger. Connect a resistor of 150 Ω or more to R1 for ESD protection. *4. When connecting a resistor less than 150 Ω to R1 or a capacitor less than 0.068 μF to C1, the S-8230A/B Series may malfunction when power dissipation is largely fluctuated. *5. When a resistor more than 4 kΩ is connected to R2, the charge current may not be cut. *6. If the resistance of R3 is too large, the conditions of VCTL ≥ VCTLH, VCTL ≤ VCTLL may not be met. Caution 1. The above constants may be changed without notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant do not guarantee proper operation. Perform thorough evaluation using the actual application to set the constant.

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 27  Precautions

• The application conditions for the input voltage, output voltage, and load current should not exceed the package power dissipation.
• Do not apply an electrostatic discharge to this IC that ex ceeds the performance ratings of the built-in electrostatic protection circuit.
• SII claims no responsibility for any and all disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party.

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 28  Characteristics (Typical Data) 1. Current consumption 1. 1 IOPE vs. Ta 1. 2 IOPE vs. VDD IOPE [μA] −4 0 0 2 55 07 5 85−25 Ta [°C] IOPE [μA] 6.5 VDD [V] 1. 3 IPDN vs. Ta 02 5 5 0 7 5 85 Ta [°C] 0.100 0.075 0.050 0.025 2. Detection voltage 2. 1 VCU vs. Ta 2. 2 VCL vs. Ta 4.32 4.30 4.28 4.26

4.24 VCU [V]

−4 0 0 2 55 07 5 85−25 Ta [°C] 4.22 4.20 4.18 4.16

4.14 VCL [V]

−40 0 25 50 75 85−25 Ta [°C] 2. 3 VDL vs. Ta 2. 4 VDU vs. Ta 2.31 2.30 2.29 2.28

2.27 VDL [V]

−4 0 0 2 55 07 5 85−25 Ta [°C] 2.31 2.30 2.29 2.28

2.27 VDU [V]

−40 0 25 50 75 85−25 Ta [°C]

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 29 2. 5 VDIOV vs. Ta 2. 6 VDIOV vs. VDD 0.13 0.12 0.11 0.10

0.09 VDIOV [V]

−4 0 0 2 55 07 5 85−25 Ta [°C] 0.13 0.12 0.11 0.10 4.5 VDD [V] 2. 7 VSHORT vs. Ta 2. 8 VSHORT vs. VDD 0.60 0.55 0.50 0.45

0.40 VSHORT [V]

−4 0 0 2 55 07 5 85−25 Ta [°C] 0.60 0.55 0.50 0.45 4.5 VDD [V] 2. 9 VCIOV vs. Ta 2. 10 VCIOV vs. VDD −0.08 −0.09 −0.10 −0.11 −0.12 VCIOV [V] −4 0 0 2 55 07 5 85−25 Ta [°C] 4.5 VDD [V] −0.08 −0.09 −0.10 −0.11 −0.12 VCIOV [V]

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 30 3. Delay time 3. 1 tCU vs. Ta 3. 2 tDL vs. Ta tCU [ms] 1500 1250 1000 750 500 −4 0 0 2 55 07 5 85−25 Ta [°C] tDL [ms] 192 160 128 −40 0 25 50 75 85−25 Ta [°C] 3. 3 tDIOV vs. Ta 3. 4 tDIOV vs. VDD tDIOV [ms] −4 0 0 2 55 07 5 85−25 Ta [°C] 4.5 VDD [V] tDIOV [ms] 3. 5 tSHORT vs. Ta 3. 6 tSHORT vs. VDD 100 150 200 250 300 350 400 −4 0 0 2 55 07 5 85−25 Ta [°C] tSHORT [μs] 4.5 VDD [V] 100 150 200 250 300 350 400tSHORT [μs] 3. 7 t CIOV vs. Ta 3. 8 tCIOV vs. VDD tCIOV [ms] −4 0 0 2 55 07 5 85−25 Ta [°C] 4.5 VDD [V] tCIOV [ms]

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK Rev.2.3_00 S-8230A/B Series Seiko Instruments Inc. 31 3. 9 tCTL vs. Ta 3. 10 tCTL vs. VDD tCTL [ms] 384 320 256 192 128 −4 0 0 2 55 07 5 85−25 Ta [°C] 4.5 VDD [V] tCTL [ms] 384 320 256 192 128 4. Output resistance 4. 1 RCOH vs. VCO 4. 2 RCOL vs. VCO RCOH [kΩ] VCO [V] 43210 RCOL [kΩ] VCO [V] 5 4 3 2 1 0 4. 3 RDOH vs. VDO 4. 4 RDOL vs. VDO RDOH [kΩ] VDO [V] 43210 RDOL [kΩ] VDO [V] 2.01.51.00.50

BATTERY PROTECTION IC WITH DISCHARGE CONTROL FUNCTION FOR 1-CELL PACK S-8230A/B Series Rev.2.3_00 Seiko Instruments Inc. 32  Marking Specification 1. SNT-6A Top view 13 2 64 5 (1) (2) (3) (4) (5) (6) (1) to (3): Product code (refer to Product name vs. Product code) (4) to (6): Lot number Product name vs. Product code 1. 1 S-8230A Series Product Name Product Code (1) (2) (3) S-8230AAD-I6T1U Y 8 D S-8230AAE-I6T1U Y 8 E S-8230AAF-I6T1U Y 8 F 1. 2 S-8230B Series Product Name Product Code (1) (2) (3) S-8230BAA-I6T1U Y 9 A S-8230BAB-I6T1U Y 9 B S-8230BAE-I6T1U Y 9 D S-8230BAF-I6T1U Y 9 E

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