S8225B

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www.sii-ic.com BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK © Seiko Instruments Inc., 2012-2015 Rev.1.4_00 Seiko Instruments Inc. 1 The S-8225B Series includes high-accuracy voltage detection ci rcuits and delay circuits, and can monitor the status of 3-serial to 5-serial cell lithium-ion rechargeable battery in si ngle use. By switching the voltage level which is applied to th e SEL1 pin and SEL2 pin, users are able to use the S-8225B Series for 3-serial to 5-serial cell pack.  Features

• High-accuracy voltage detection function for each cell Overcharge detection voltage n (n = 1 to 5) 3.5 V to 4.4 V (50 mV step) Accuracy ±20 mV (Ta = +25°C), ±30 mV (Ta = 0°C to +60°C) Overcharge release voltage n (n = 1 to 5) 3.3 V to 4.4 V *1 Accuracy ±50 mV Overdischarge detection voltage n (n = 1 to 5) 2.2 V to 3.2 V (100 mV step) Accuracy ±80 mV Overdischarge release voltage n (n = 1 to 5) 2.2 V to 3.4 V *2 Accuracy ±100 mV
• Overcharge detection delay time and overdischarge detection delay time can be set by external capacitor.
• Switchable between 3-serial to 5-serial cell by using the SEL1 pin and the SEL2 pin
• The CO pin and the DO pin are controlled by the CTLC pin and the CTLD pin, respectively.
• Output voltage of the CO pin and the DO pin is limited to 12 V max.
• Output logic is selectable. Active "H", active "L"
• High-withstand voltage element Absolute maximum rating: 28 V
• Wide operation voltage range 4 V to 26 V
• Wide operation temperature range Ta = −40°C to +85°C
• Low current consumption During operation (V1 = V2 = V3 = V4 = V5 = 3.4 V) 20 μA max. (Ta = +25°C) During power-down (V1 = V2 = V3 = V4 = V5 = 1.6 V) 3.0 μA max. (Ta = +25°C)
• Lead-free (Sn 100%), halogen-free *1. Overcharge hysteresis voltage n (n = 1 to 5) is sele ctable in 0 V, or in 0.1 V to 0.4 V in 50 mV step. (Overcharge hysteresis volt age = Overcharge detection voltage − Overcharge release voltage) *2. Overdischarge hysteresis voltage n (n = 1 to 5) is sele ctable in 0 V, or in 0.2 V to 0.7 V in 100 mV step. (Overdischarge hysteresis voltage = Overdischarge release voltage − Overdischarge detection voltage)  Application
• Lithium-ion rechargeable battery pack  Package
• 16-Pin TSSOP

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK S-8225B Series Rev.1.4_00 Seiko Instruments Inc. 2  Block Diagram VDD CTLD CTLC DO SEL1 SEL2 VC1 VC2 VC3 VC4 Delay circuit VC5 CO VC6 VSS CDT CCT CO pin output voltage limit circuit DO pin output voltage limit circuit Control circuit Delay circuit Overcharge 1 Overcharge 2 Overcharge 3 Overcharge 4 Overcharge 5 Over- discharge 1 Over- discharge 2 Over- discharge 3 Over- discharge 4 Over- discharge 5 Remark Diodes in the figure are parasitic diodes. Figure 1

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK Rev.1.4_00 S-8225B Series Seiko Instruments Inc. 3  Product Name Structure 1. Product name S-8225B xx - TCT1 U Environmental code U: Lead-free (Sn 100%), halogen-free Package abbreviation and IC packing specifications*1 TCT1: 16-Pin TSSOP, Tape Serial code*2 Sequentially set from AA to ZZ *1. Refer to the tape drawing. *2. Refer to "3. Product name list". 2. Package Table 1 Package Drawing Codes Package Name Dimension Tape Reel 16-Pin TSSOP FT016-A-P-SD FT016-A-C-SD FT016-A-R-S1 3. Product name list Table 2 Product Name Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] Overdischarge Detection Voltage [VDL] Overdischarge Release Voltage [VDU] CO Pin Output Logic DO Pin Output Logic

0 V Battery

S-8225BAA-TCT1U 4.220 V 4.170 V 2.30 V 2.30 V Active "H" Active "L" Unavailable S-8225BAB-TCT1U 3.600 V 3.550 V 2.20 V 2.20 V Active "H" Active "L" Unavailable S-8225BAC-TCT1U 4.450 V 4.050 V 2.50 V 2.70 V Active "H" Active "L" Unavailable S-8225BAE-TCT1U 4.250 V 4.200 V 2.70 V 3.00 V Active "H" Active "H" Unavailable S-8225BAF-TCT1U 4.250 V 4.200 V 2.50 V 2.70 V Active "H" Active "H" Unavailable S-8225BAG-TCT1U 4.275 V 4.225 V 2.30 V 2.80 V Active "H" Active "H" Unavailable S-8225BAH-TCT1U 3.900 V 3.600 V 2.20 V 2.40 V Active "H" Active "H" Available S-8225BAI-TCT1U 4.195 V 4.195 V 2.50 V 3.00 V Active "H" Active "H" Available Remark Please contact our sales office for products with detection voltage values other than those specified above.

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK S-8225B Series Rev.1.4_00 Seiko Instruments Inc. 4  Pin Configuration 1. 16-Pin TSSOP Top view Figure 2 Table 3 Pin No. Symbol Description

1 CTLD DO control pin

2 CTLC CO control pin

3 CO Output pin for overcharge detection

4 DO Output pin for overdischarge detection

5 SEL1 Switching pins for 3-serial to 5-serial cell*1 6 SEL2

7 CDT Capacitor connection pin for delay for overdischarge detection voltage

8 CCT Capacitor connection pin for delay for overcharge detection voltage

9 VSS Input pin for negative power supply,

connection pin for negative voltage of battery 5

10 VC6 Connection pin for negative voltage of battery 5

11 VC5 Connection pin for negative voltage of battery 4,

connection pin for positive voltage of battery 5

12 VC4 Connection pin for negative voltage of battery 3,

connection pin for positive voltage of battery 4

13 VC3 Connection pin for negative voltage of battery 2,

connection pin for positive voltage of battery 3

14 VC2 Connection pin for negative voltage of battery 1,

connection pin for positive voltage of battery 2

15 VC1 Connection pin for positive voltage of battery 1

16 VDD Input pin for positive power supply,

connection pin for positive voltage of battery 1 *1. Refer to "7. SEL pin" in " Operation" for setting of the SEL1 pin and the SEL2 pin.

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK Rev.1.4_00 S-8225B Series Seiko Instruments Inc. 5  Absolute Maximum Ratings Table 4 (Ta = +25°C unless otherwise specified) Item Symbol Applied Pin Ab solute Maximum Rating Unit Input voltage between VDD pin and VSS pin VDS VDD V SS − 0.3 to VSS + 28 V Input pin voltage V IN VC1, VC2, VC3, VC4, VC5, VC6, SEL1, SEL2, CTLC, CTLD, CCT, CDT V SS − 0.3 to VDD + 0.3 V Output pin voltage V OUT DO, CO V SS − 0.3 to VDD + 0.3 V Power dissipation P D − 1100*1 mW Operation ambient temperature T opr − −40 to +85 °C Storage temperature T stg − −40 to +125 °C *1. When mounted on board [Mounted board] (1) Board size: 114.3 mm × 76.2 mm × t1.6 mm (2) Board name: JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 0 50 100 150 800 400 Power dissipation (PD) [mW] Ambient temperature (Ta) [°C] 1000 600 200 1200 Figure 3 Power Dissipation of Package (When Mounted on Board)

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK S-8225B Series Rev.1.4_00 Seiko Instruments Inc. 6  Electrical Characteristics Table 5 (1 / 2) (Ta = +25°C, VDS = VDD − VSS = V1 + V2 + V3 + V4 + V5 unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection Voltage Overcharge detection voltage n Ta = +25°C V1 = V2 = V3 = V4 = V5 = V CU − 0.05 V VCUn − 0.020 VCUn VCUn + 0.020 V 1 Ta = 0°C to +60°C*1 V1 = V2 = V3 = V4 = V5 = V CU − 0.05 V VCUn − 0.030 VCUn VCUn + 0.030 V 1 Overcharge release voltage n (n = 1, 2, 3, 4, 5) VCLn − VCLn − 0.050 VCLn VCLn + 0.050 V 1 Overdischarge detection voltage n (n = 1, 2, 3, 4, 5) VDLn − VDLn − 0.08 VDLn VDLn + 0.08 V 1 Overdischarge release voltage n (n = 1, 2, 3, 4, 5) VDUn − VDUn − 0.10 VDUn VDUn + 0.10 V 1

0 V battery detection voltage n

(n = 1, 2, 3, 4, 5) V0INHn 0 V battery detection function "available" 0.4 0.7 1.1 V 1 Delay Time Function*2 Overcharge detection delay time tCU CCCT = 0.1 μF 0.67 1.00 1.33 s 2 Overdischarge detection delay time tDL CCDT = 0.1 μF 0.67 1.00 1.33 s 2 CCT pin voltage V CCT − − 1.5 5.0 V 2 CDT pin voltage V CDT − − 1.5 5.0 V 2 Input Voltage Operation voltage between VDD pin and VSS pin VDSOP Fixed output voltage of CO pin and DO pin 4 − 26 V − CTLC pin voltage "H" V CTLCH − V DS − 4.0 − V DS − 0.5 V 3 CTLC pin voltage "L" V CTLCL − 0.5 − 4.0 V 3 CTLD pin voltage "H" V CTLDH − V DS − 4.0 − V DS − 0.5 V 3 CTLD pin voltage "L" VCTLDL − 0.5 − 4.0 V 3 SEL1 pin voltage "H" V SELH1 − V DS × 0.8 − − V 3 SEL2 pin voltage "H" V SELH2 − V DS × 0.8 − − V 3 SEL1 pin voltage "L" V SELL1 − − − V DS × 0.2 V 3 SEL2 pin voltage "L" V SELL2 − − − V DS × 0.2 V 3 Output Voltage − CO pin voltage "H" V COH − 5.0 8.0 12.0 V 4 DO pin voltage "H" V DOH − 5.0 8.0 12.0 V 4 Input Current − Current consumption during operation IOPE V1 = V2 = V3 = V4 = V5 = 3.4 V − 12 20 μA5 Current consumption during power-down IPDN V1 = V2 = V3 = V4 = V5 = 1.6 V − 1.6 3.0 μA5 VC1 pin current I VC1 V1 = V2 = V3 = V4 = V5 = 3.4 V, V6 = V7 = VDS, V8 = V9 = 0 V − 0.4 0.8 μA6 VC2 to VC5 pins current IVC2 to IVC5 V1 = V2 = V3 = V4 = V5 = 3.4 V, V6 = V7 = VDS, V8 = V9 = 0 V −1.0 − 1.0 μA6 VC6 pin current IVC6 V1 = V2 = V3 = V4 = V5 = 3.4 V, V6 = V7 = VDS, V8 = V9 = 0 V −3.0 −1.0 − μA6 CTLC pin current "H" I CTLCH V1 = V2 = V3 = V4 = V5 = 3.4 V, V6 = V7 = VDS, V8 = V9 = 0 V − − 0.1 μA 6 CTLC pin current "L" I CTLCL V1 = V2 = V3 = V4 = V5 = 3.4 V, V7 = VDS, V6 = V8 = V9 = 0 V −0.1 − − μA 6

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK Rev.1.4_00 S-8225B Series Seiko Instruments Inc. 7 Table 5 (2 / 2) (Ta = +25°C, VDS = VDD − VSS = V1 + V2 + V3 + V4 + V5 unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit CTLD pin current "H" I CTLDH V1 = V2 = V3 = V4 = V5 = 3.4 V, V6 = V7 = VDS, V8 = V9 = 0 V − − 0.1 μA6 CTLD pin current "L" I CTLDL V1 = V2 = V3 = V4 = V5 = 3.4 V, V6 = VDS, V7 = V8 = V9 = 0 V −0.1 − − μA6 SEL1 pin current "H" I SELH1 V1 = V2 = V3 = V4 = V5 = 3.4 V, V6 = V7 = V8 = VDS, V9 = 0 V − − 0.1 μA6 SEL2 pin current "H" I SELH2 V1 = V2 = V3 = V4 = V5 = 3.4 V, V6 = V7 = V9 = VDS, V8 = 0 V − − 0.1 μA6 SEL1 pin current "L" I SELL1 V1 = V2 = V3 = V4 = V5 = 3.4 V, V6 = V7 = VDS, V8 = V9 = 0 V −0.1 − − μA6 SEL2 pin current "L" I SELL2 V1 = V2 = V3 = V4 = V5 = 3.4 V, V6 = V7 = VDS, V8 = V9 = 0 V −0.1 − − μA 6 Output Current (CO Pin Output Logic Active "H") CO pin source current I COH − − − −10 μA 7 CO pin sink current I COL − 10 − − μA 7 Output Current (CO Pin Output Logic Active "L") CO pin source current I COH − − − −10 μA 7 CO pin sink current I COL − 10 − − μA 7 Output Current (DO Pin Output Logic Active "H") DO pin source current I DOH − − − −10 μA 7 DO pin sink current I DOL − 10 − − μA 7 Output Current (DO Pin Output Logic Active "L") DO pin source current I DOH − − − −10 μA 7 DO pin sink current I DOL − 10 − − μA 7 *1. Since products are not screened at high an d low temperature, the specification for this temperature range is guaranteed by design, not tested in production. *2. Refer to " 6. Delay time setting" in " Operation" for details of the delay time function.

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK S-8225B Series Rev.1.4_00 Seiko Instruments Inc. 8  Test Circuits 1. Overcharge detection voltage (V CUn), Overcharge release voltage (VCLn), Overdischarge detection voltage (VDLn), Overdischarge release voltage (VDUn) (Test circuit 1) VCU1 is defined as the voltage V1 when V1 is gradually increased and the CO pin output becomes detection status after setting V1 = V2 = V3 = V4 = V5 = V CU − 0.05 V. After that, V CL1 is defined as the voltage V1 when V1 is gradually decreased and the CO pin output becomes rel ease status after setting V2 = V3 = V4 = V5 = 3.2 V. Moreover, V DL1 is defined as the voltage V1 when V1 is gradually decreased and the DO pin output becomes detection status after setting V1 = V2 = V3 = V4 = V5 = 3.5 V. After that, V DU1 is defined as the voltage V1 when V1 is gradually increased and the DO pin output becomes release status. Similarly, VCUn, VCLn, VDLn and VDUn can be defined by changing Vn (n = 2 to 5). 2. 0 V battery detection voltage (V 0INHn) (0 V battery detection function "available") (Test circuit 1) V0INH1 is defined as the voltage V1 when V1 is gradually decr eased and the CO pin output becomes detection status after setting V1 = V2 = V3 = V4 = V5 = 3.4 V. Similarly, V0INHn can be defined by changing Vn (n = 2 to 5). 3. Overcharge detection delay time (t CU), overdischarge detection delay time (tDL) (Test circuit 2) tCU is defined as the time period from when V1 changes from 3.4 V to 4.5 V to when the CO pin output becomes detection status after setting V1 = V2 = V3 = V4 = V5 = 3.4 V. Moreover, tDL is defined as the time period from when V1 changes from 3.4 V to 1.6 V to when the DO pin output becomes detection status after setting V1 = V2 = V3 = V4 = V5 = 3.4 V. 4. CCT pin voltage (V CCT), CDT pin voltage (VCDT) (Test circuit 2) VCCT is defined as the voltage between the CCT pin and the VSS pin during the time period when V1 changes from 3.4 V to 4.5 V to when the CO pin output becomes detection status after setting V1 = V2 = V3 = V4 = V5 = 3.4 V. Moreover, VCDT is defined as the voltage betw een the CDT pin and the VSS pin during the time period when V1 changes from 3.4 V to 1.6 V to when the DO pin output becomes detection status after setting V1 = V2 = V3 = V4 = V5 = 3.4 V. 5. CTLC pin voltage "H" (V CTLCH), CTLC pin voltage "L" (VCTLCL), CTLD pin voltage "H" (VCTLDH), CTLD pin voltage "L" (VCTLDL) (Test circuit 3) VCTLCL is defined as the voltage V6 when V6 is gradually decre ased and the CO pin out put becomes detection status after setting V1 = V2 = V3 = V4 = V5 = 3.4 V, V6 = V7 = VDS (= V1 + V2 + V3 + V4 + V5), V8 = V9 = 0 V. After that, VCTLCH is defined as the voltage V6 when V6 is gradually in creased and the CO pin output becomes release status. Moreover, V CTLDL is defined as the voltage V7 when V7 is gradual ly decreased and the DO pin output becomes detection status after setting V1 = V2 = V3 = V4 = V5 = 3.4 V, V6 = V7 = V DS (= V1 + V2 + V3 + V4 + V5), V8 = V9 = 0 V. After that, VCTLDH is defined as the voltage V7 when V7 is gradually increased and the DO pin output becomes release status.

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK Rev.1.4_00 S-8225B Series Seiko Instruments Inc. 9 6. SEL1 pin voltage "H" (V SELH1), SEL2 pin voltage "H" (V SELH2), SEL1 pin voltage "L" (V SELL1), SEL2 pin voltage "L" (VSELL2) (Test circuit 3) VSELH1 is defined as the voltage V8 when V8 is gradually increas ed and the DO pin output becomes release status after setting V1 = V2 = V3 = V5 = 3.5 V, V4 = 0 V, V6 = V7 = V DS (= V1 + V2 + V3 + V4 + V5), V8 = V9 = 0 V. After that, VSELL1 is defined as the voltage V8 when V8 is gradually de creased and the DO pin output becomes detection status. Moreover, V SELH2 is defined as the voltage V9 when V9 is gradually increased and the DO pin output becomes release status after setting V1 = V2 = V3 = V4 = 3.5 V, V5 = 0 V, V6 = V7 = V DS (= V1 + V2 + V3 + V4 + V5), V8 = V9 = 0 V. After that, V SELL2 is defined as the voltage V9 when V9 is gradually decreased and the DO pin output becomes detection status. 7. CO pin voltage "H" (V COH), DO pin voltage "H" (VDOH) (Test circuit 4) 7. 1 CO pin output logic active "H" VCOH is defined as the voltage between t he CO pin and the VSS pin when V1 = 6.8 V, V2 = 0 V, V3 = V4 = V5 = 3.4 V. 7. 2 CO pin output logic active "L" V COH is defined as the voltage between the CO pin and the VSS pin when V1 = V2 = V3 = V4 = V5 = 3.4 V. 7. 3 DO pin output logic active "H" VDOH is defined as the voltage between the DO pi n and the VSS pin when V1 = 6.8 V, V2 = 0 V, V3 = V4 = V5 = 3.4 V. 7. 4 DO pin output logic active "L" VDOH is defined as the voltage between the DO pin and the VSS pin when V1 = V2 = V3 = V4 = V5 = 3.4 V. 8. CO pin source current (I COH), CO pin sink current (ICOL), DO pin source current (IDOH), DO pin sink current (IDOL) (Test circuit 7) 8. 1 CO pin output logic active "H" ICOH is defined as the CO pin current when V1 = 6.8 V, V2 = 0 V, V3 = V4 = V5 = 3.4 V, V6 = VCOH − 0.5 V. ICOL is defined as the CO pin current when V1 = V2 = V3 = V4 = V5 = 3.4 V, V6 = 0.5 V. 8. 2 CO pin output logic active "L" ICOH is defined as the CO pin current when V1 = V2 = V3 = V4 = V5 = 3.4 V, V6 = VCOH − 0.5 V. ICOL is defined as the CO pin current when V1 = 6.8 V, V2 = 0 V, V3 = V4 = V5 = 3.4 V, V6 = 0.5 V. 8. 3 DO pin output logic active "H" IDOH is defined as the DO pin current when V1 = 6.8 V, V2 = 0 V, V3 = V4 = V5 = 3.4 V, V7 = VDOH − 0.5 V. IDOL is defined as the DO pin current when V1 = V2 = V3 = V4 = V5 = 3.4 V, V7 = 0.5 V. 8. 4 DO pin output logic active "L" IDOH is defined as the DO pin current when V1 = V2 = V3 = V4 = V5 = 3.4 V, V7 = VDOH − 0.5 V. IDOL is defined as the DO pin current when V1 = 6.8 V, V2 = 0 V, V3 = V4 = V5 = 3.4 V, V7 = 0.5 V.

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK S-8225B Series Rev.1.4_00 Seiko Instruments Inc. 10 3 CO 4 DO

5 SEL1

6 SEL2

7 CDT

9 CCT

V 3 CO 4 DO 0.1 μF 0.1 μF V Figure 4 Test Circuit 1 Figure 5 Test Circuit 2 3 CO 4 DO

1 MΩ 1 MΩ

Figure 6 Test Circuit 3 Figure 7 Test Circuit 4 3 CO 4 DO A IOPE, IPDN 3C O 4D O A A A A AV V V7V6 V9V8 AAAA Figure 8 Test Circuit 5 Figure 9 Test Circuit 6 3 CO 4 DO

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK Rev.1.4_00 S-8225B Series Seiko Instruments Inc. 11  Operation Remark Refer to " Connection Examples of Battery Monitoring IC". 1. Normal status When all battery voltages are in the range from overcharge detection voltage (V CUn) to overdischarge detection voltage (VDLn), and the CTLC pin input voltage (V CTLC) and the CTLD pin input voltage (V CTLD) are higher than the CTLC pin voltage "H" (V CTLCH) and the CTLD pin voltage "H" (V CTLDH), respectively, the S-8225B Series defines the CO pin output voltage (V CO) and the DO pin output voltage (V DO) as "L" (output logic active "H") or "H" (output logic active "L"). This is called normal status. V CO is defined as the CO pin voltage "H" (V COH) when it is "H". Similarly, V DO is defined as the DO pin voltage "H" (VDOH) when it is "H". 2. Overcharge status When any one of the battery voltages becomes V CUn or higher, the CO pin output inverts and the S-8225B Series becomes detection status. This is called overcharge status. When all battery voltages become overcharge release voltage (V CLn) or lower, the overcharge status is released and the S-8225B Series returns to normal status. 3. Overdischarge status When any one of the battery voltages becomes V DLn or lower, the DO pin output inverts and the S-8225B Series becomes detection status. This is called overdischarge status. When all battery voltages become overdischarge release voltage (V DUn) or higher, the overdischarge status is released and the S-8225B Series returns to normal status. 4. CTLC pin and CTLD pin The S-8225B Series has two pins to control. The CTLC pin controls the output voltage from the CO pin; the CTLD pin controls the output voltage from the DO pin. Thus it is possible for users to control the output voltages from the CO pin and DO pin, respectively. These controls precede the battery protection circuit. Table 6 Status Set by CTLC Pin CTLC Pin CO Pin "H"*1 Normal status *3 "L"*2 Detection status *1. "H": CTLC ≥ VCTLCH *2. "L": CTLC ≤ VCTLCL *3. The status is controlled by the voltage detection circuit. Table 7 Status Set by CTLD Pin CTLD Pin DO Pin "H"*1 Normal status *3 "L"*2 Detection status *1. "H": CTLD ≥ VCTLDH *2. "L": CTLD ≤ VCTLDL *3. The status is controlled by the voltage detection circuit.

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK S-8225B Series Rev.1.4_00 Seiko Instruments Inc. 12 5. 0 V battery detection function In the S-8225B Series, users are able to select a 0 V battery detection "available" function. If this optional function is selected, the CO pin becomes detection status when any one of the battery voltages becomes 0 V battery detection voltage (V0INHn) or lower. 6. Delay time setting When any one of the battery voltages becomes V CUn or higher, the S-8225B Series charges the capacitor connected to the CCT pin rapidly up to the CCT pin voltage (VCCT). After that, The S-8225B Series discharges the capacitor with the constant current of 100 nA, and the CO pin output is def ined as detection status at the time when the CCT pin voltage falls to a certain level or lower. The overcharge detection delay time (tCU) changes depending on the capacitor connected to the CCT pin. t CU is calculated by the following formula. Min. Typ. Max. tCU [s] = (6.7, 10, 13.3) × CCCT [μF] Similarly, the overdischarge detection delay time (tDL) changes depending on the capacitor connected to the CDT pin. tDL is calculated by the following formula. Min. Typ. Max. tDL [s] = (6.7, 10, 13.3) × CCDT [μF] Since the S-8225B Series charges the capacitor for delay rapidly, the voltage of the CCT pin and the CDT pin becomes large if the capacitance value is small. As a re sult, a variation between the calculated value of the delay time and the actual delay time is generated. If the capacitance value is so large that the rapid charging can not be finished within the internal delay time, the output pin becomes detection status simultaneously with the end of internal delay time. In addition, the charging current to the capacitor for delay passes through the VDD pin. Therefore, a large resistor connected to the VDD pin results in a big drop of the power supply voltage at the time of rapid charging which causes malfunction. Regarding the recommended values for external components, refer to " Table 9 Constants for External Components". 7. SEL pin In the S-8225B Series, switchable monitoring control betw een 3-cell to 5-cell is possible by using the SEL1 pin and the SEL2 pin. For example, since the overdischarge detection of V4 or V5 is prohibited and the overdischarge is not detected even if V4 or V5 is shorted when the SEL1 pin is "H" and the SEL2 pin is "L", the S-8225B Series can be used for 3-cell monitoring. Be sure to use the SEL1 pin and the SEL2 pin at "H" or "L" potential. Table 8 Settings of SEL1 Pin and SEL2 Pin SEL1 pin SEL2 pin Setting "H"*1 "L" *2 3-cell monitoring "L"*2 "H" *1 4-cell monitoring "L"*2 "L" *2 5-cell monitoring *1. "H": SEL1 ≥ VSELH1 and SEL2 ≥ VSELH2 *2. "L": SEL1 ≤ VSELL1 and SEL2 ≤ VSELL2

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK Rev.1.4_00 S-8225B Series Seiko Instruments Inc. 13  Timing Charts 1. Overcharge detection and overdischarge detection (n = 1 to 5) VCUn VDLn VCLn Battery voltage VSS DO pin voltage (Active "L") CO pin voltage (Active "L") VSS Charger connection Load connection Status*1 (1) (2) (1) (1) VDOH VCOH (3) VDUn Overcharge detection delay time (tCU) Overdischarge detection delay time (tDL) *1. (1): Normal status (2): Overcharge status (3): Overdischarge status Figure 11

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK S-8225B Series Rev.1.4_00 Seiko Instruments Inc. 14 2. Overcharge detection delay (n = 1 to 5) VCUn Battery voltage VSS CCT pin voltage CO pin voltage (Active "L") VSS Charger connection Status*1 Less than tCU (1) (2) VCCT VCOH tCU *1. (1): Normal status (2): Overcharge status Figure 12

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK Rev.1.4_00 S-8225B Series Seiko Instruments Inc. 15 3. Overdischarge detection delay (n = 1 to 5) VDLn Battery voltage VSS CDT pin voltage DO pin voltage (Active "L") VSS Charger connection Status*1 Less than tDL (1) (2) VCDT VDOH tDL *1. (1): Normal status (2): Overdischarge status Figure 13

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK S-8225B Series Rev.1.4_00 Seiko Instruments Inc. 16  Connection Examples of Battery Monitoring IC 1. 5-serial cell RSEL1 RSEL2 RCTLD RCTLC EB+ EB−

1 CTLD

2 CTLC

8 CCT

1. 4-serial cell RSEL1 RSEL2 RCTLD RCTLC EB+ EB−

Remark Regarding the recommended values for external components, refer to " Table 9 Constants for External Components".

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK Rev.1.4_00 S-8225B Series Seiko Instruments Inc. 17 3. 3-serial cell RSEL1 RSEL2 RCTLD RCTLC EB+ EB− Remark Regarding the recommended values for external components, refer to " Table 9 Constants for External Components". Table 9 Constants for External Components Symbol Min. Typ. Max. Unit RVDD 50 100 1000 Ω RVCn 0.5 1 2 k Ω CVDS 0.01 0.1 1 μF CVDD − 0 1 μF CVCn 0.01 0.1 1 μF CCCT 0.001 0.1 0.22 μF CCDT 0.001 0.1 0.22 μF RCTLC, RCTLD − 1 − k Ω RSEL1, RSEL2 0.5 1 − k Ω Caution 1. The above constants may be changed without notice. 2. The example of connection shown above and th e constant do not guar antee proper operation. Perform thorough evaluation using the actual application to set the constant. 3. RVC1 to RVC6 and CVC1 to CVC6 should be the same constant, respectively. 4. Set up RVCn and CVCn as RVCn × CVCn ≥ 50 × 10-6. 5. Set up RVDD and CVDS as 5 × 10-6 ≤ RVDD × CVDS ≤ 100 × 10-6. 6. Set (RVDD × CVDS) / (RVCn × CVCn) = 0.1. Remark n = 1 to 6

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK S-8225B Series Rev.1.4_00 Seiko Instruments Inc. 18  Precautions

• The application conditions for the input voltage, output voltage, and load current should not exceed the package power dissipation.
• If both an overcharge battery and an overdischarge battery are included among the whole batteries, the condition is set in overcharge status and overdischarge status. Therefore either charging or discharging is impossible.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit.
• SII claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party.

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK Rev.1.4_00 S-8225B Series Seiko Instruments Inc. 19  Characteristics (Typical Data) 1. Detection voltage 1. 1 VCU vs. Ta VCU = 4.220 V 1. 2 VCL vs. Ta VCL = 4.170 V −4 0 0 2 55 07 5 VCU [V] 4.24 4.20 Ta [°C] −25 85 4.23 4.22 4.21 −4 0 0 2 55 07 5 VCL [V] 4.22 4.12 Ta [°C] −25 85 4.20 4.18 4.16 4.14 1. 3 VDL vs. Ta VDL = 2.30 V 1. 4 VDU vs. Ta VDU = 2.30 V −4 0 0 2 55 07 5 VDL [V] 2.40 2.20 Ta [°C] −25 85 2.35 2.30 2.25 −4 0 0 2 55 07 5 VDU [V] 2.38 2.22 Ta [°C] −25 85 2.34 2.30 2.26 2. Current consumption 2. 1 IOPE vs. Ta VDD = 17.0 V 2. 2 IPDN vs. Ta VDD = 8.0 V −4 0 0 2 55 07 5 IOPE [μA] Ta [°C] −25 85 −4 0 0 2 55 07 5 IPDN [μA] Ta [°C] −25 85 2. 3 IOPE vs. VDD Ta = +25°C IOPE [μA] 0 305 1 01 52 02 5 VDD [V]

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK S-8225B Series Rev.1.4_00 Seiko Instruments Inc. 20 3. Delay time 3. 1 tCU vs. Ta VDD = 18.1 V 3. 2 tDL vs. Ta VDD = 15.2 V −4 0 0 2 55 07 5 tCU [s] 2.0 0.0 Ta [°C] −25 85 1.5 1.0 0.5 −4 0 0 2 55 07 5 tDL [s] 2.0 0.0 Ta [°C] −25 85 1.5 1.0 0.5 4. Output current 4. 1 ICOL vs. VDD Ta = +25°C 4. 2 ICOH vs. VDD Ta = +25°C 500 ICOL [μA] 0 305 1 01 52 02 5 VDD [V] 400 300 200 100 −80 ICOH [μA] 0 305 1 01 52 02 5 VDD [V] −20 −40 −60 4. 3 IDOL vs. VDD Ta = +25°C 4. 4 IDOH vs. VDD Ta = +25°C 500 IDOL [μA] 0 305 1 01 52 02 5 VDD [V] 400 300 200 100 −80 IDOH [μA] 0 305 1 01 52 02 5 VDD [V] −20 −40 −60 5. Output voltage 5. 1 VCOH vs. VDD Ta = +25°C, CO pin output logic active "L", V CU = 4.220 V

0 V battery detection function "unavailable"

1. 2 VDOH vs. VDD Ta = +25°C, DO pin output logic active "L" VDL = 2.30 V VCOH [V] 0 51 5 2 0 25 30 VDD [V] VDOH [V] 0 51 5 2 0 25 30 VDD [V]

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