S8224A

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 33

Technical content

www.sii-ic.com BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) © SII Semiconductor Corporation, 2017 Rev.1.2_00 The S-8224A/B Series is used for secondary protection of lithium-ion rechargeable batteries, and incorporates high-accuracy voltage detection circuits and delay circuits. Short-circuits between cells accommodate series connection of two cells to four cells. The S-8224B Series limits its CO pin output voltage to 11.5 V max., so an FET with the gate withstand voltage of 12 V can be used.  Features

• High-accuracy voltage detection circuit for each cell Overcharge detection voltage n (n = 1 to 4) 3.600 V to 4.700 V (50 mV step) Accuracy ±20 mV (Ta = +25°C) Accuracy ±25 mV (Ta = −10°C to +60°C) Overcharge hysteresis voltage n (n = 1 to 4)*1 0.0 mV to −550 mV (50 mV step) −300 mV to −550 mV Accuracy ±20% −100 mV to −250 mV Accuracy ±50 mV −50 mV Accuracy ±25 mV 0.0 mV Accuracy −25 mV to +20 mV
• Delay times for overcharge detection are generated only by an internal circuit (external capacitors are unnecessary) Overcharge detection delay time is selectable: 1 s, 2 s, 4 s, 6 s, 8 s Overcharge release delay time is selectable: 2 ms, 64 ms
• Built-in timer reset delay circuit
• Output control function via CTL pin
• Output form is selectable (S-8224A Series): CMOS output, Nch open-drain output
• Output logic is selectable (S-8224A Series): Active "H", active "L"
• CO pin output voltage is limited to 11.5 V max. (S-8224B Series)*2
• High-withstand voltage: Absolute maximum rating 28 V
• Wide operation voltage range: 3.6 V to 28 V
• Wide operation temperature range: Ta = −40°C to +85°C
• Low current consumption During overdischarge (VCU × 0.5 V for each cell): 0.3 μA max. (Ta = +25°C)
• Lead-free (Sn 100%), halogen-free *1. Select the overcharge hysteresis voltage calculated as the following formula. (Overcharge detection voltage n) + (Overcharge hysteresis voltage n) ≥ 3.4 V *2. Only output logic active "H" is available.  Application
• Lithium-ion rechargeable battery packs (for secondary protection)  Package
• SNT-8A

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) S-8224A/B Series Rev.1.2_00  Block Diagrams 1. S-8224A Series 1. 1 CMOS output product VC1 VC3 VC2 CO VC4 VSS VDD Control logic Delay circuit Oscillator CTL CO pin output control circuit Overcharge detection comparator 1 Overcharge detection comparator 2 Overcharge detection comparator 3 Overcharge detection comparator 4 Figure 1

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.2_00 S-8224A/B Series 1. 2 Nch open-drain output product VC3 VC2 CO VC1 VC4 VSS VDD Control logic Delay circuit Oscillator CTL CO pin output control circuit Overcharge detection comparator 1 Overcharge detection comparator 2 Overcharge detection comparator 3 Overcharge detection comparator 4 Figure 2

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) S-8224A/B Series Rev.1.2_00 2. S-8224B Series VC3 VC2 CO VC1 VC4 VSS VDD Control logic Delay circuit Oscillator CTL CO pin output control circuit CO pin output voltage limit circuit Overcharge detection comparator 1 Overcharge detection comparator 2 Overcharge detection comparator 3 Overcharge detection comparator 4 Figure 3

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.2_00 S-8224A/B Series  Product Name Structure 1. Product name Package abbreviation and IC packing specifications*1 I8T1: SNT-8A, Tape Serial code*2 Sequentially set from AA to AZ Environmental code U: Lead-free (Sn 100%), halogen-free S-8224 x xx - xxxx U Product type A: CMOS output, Nch open-drain output B: CO pin output voltage 11.5 V max. *1. Refer to the tape drawing. *2. Refer to "3. Product name list". 2. Package Table 1 Package Drawing Codes Package Name Dimension Tape Reel Land SNT-8A PH008-A-P-SD PH008-A-C-SD PH008-A-R-SD PH008-A-L-SD

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) S-8224A/B Series Rev.1.2_00 3. Product name list 3. 1 S-8224A Series Table 2 Product Name Overcharge Detection Voltage [VCU] Overcharge Hysteresis Voltage [VHC] Overcharge Detection Delay Time*1 [tCU] Overcharge Release Delay Time*2 [tCL] Output Form*3 Output Logic *4 S-8224AAS-I8T1U 4.450 V −400 mV 4 s 64 ms CMOS output Active "H" S-8224AAT-I8T1U 4.350 V −400 mV 4 s 64 ms CMOS output Active "H" S-8224AAU-I8T1U 4.500 V −400 mV 4 s 64 ms CMOS output Active "H" S-8224AAV-I8T1U 4.550 V −400 mV 6 s 64 ms CMOS output Active "H" S-8224AAW-I8T1U 4.450 V −400 mV 6 s 64 ms CMOS output Active "H" S-8224AAX-I8T1U 4.350 V −400 mV 6 s 64 ms CMOS output Active "H" *1. Overcharge detection delay time 1 s / 2 s / 4 s / 6 s / 8 s is selectable. *2. Overcharge release delay time 2 ms / 64 ms is selectable. *3. Output form CMOS output / Nch open-drain output is selectable. *4. Output logic active "H" / active "L" is selectable. Remark Please contact our sales office for the products with de tection voltage value other than those specified above. 3. 2 S-8224B Series Table 3 Product Name Overcharge Detection Voltage [VCU] Overcharge Hysteresis Voltage [VHC] Overcharge Detection Delay Time*1 [tCU] Overcharge Release Delay Time*2 [tCL] Output Logic*3 S-8224BAA-I8T1U 4.350 V −400 mV 4 s 2 ms Active "H" S-8224BAB-I8T1U 4.450 V −400 mV 6 s 64 ms Active "H" S-8224BAC-I8T1U 4.350 V −400 mV 4 s 64 ms Active "H" *1. Overcharge detection delay time 1 s / 2 s / 4 s / 6 s / 8 s is selectable. *2. Overcharge release delay time 2 ms / 64 ms is selectable. *3. Only output logic active "H" is available. Remark Please contact our sales office for the products with de tection voltage value other than those specified above.

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.2_00 S-8224A/B Series  Pin Configuration 1. SNT-8A Top view Figure 4 Table 4 Pin No. Symbol Description

1 VDD Positive power supply input pin

2 VC1 Positive voltage connection pin of battery 1

3 VC2 Negative voltage connection pin of battery 1

Positive voltage connection pin of battery 2

4 VC3 Negative voltage connection pin of battery 2

Positive voltage connection pin of battery 3

5 VC4 Negative voltage connection pin of battery 3

Positive voltage connection pin of battery 4

6 VSS Negative power supply input pin

Negative voltage connection pin of battery 4

7 CTL CO pin output control pin

8 CO FET gate connection pin for charge control

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) S-8224A/B Series Rev.1.2_00  Absolute Maximum Ratings Table 5 (Ta = +25°C unless otherwise specified) Item Symbol Applied Pin Absolute Maximum Rating Unit Input voltage between VDD pin and VSS pin VDS VDD V SS − 0.3 to VSS + 28 V Input pin voltage VIN VC1 V SS − 0.3 to VSS + 28 V VC2, VC3, VC4 V DD − 28 to VDD + 0.3 V CTL V SS − 0.3 to VDD + 0.3 V CO pin output voltage S-8224A Series CMOS output VCO CO VSS − 0.3 to VDD + 0.3 V Nch open-drain output VSS − 0.3 to VSS + 28 V S-8224B Series VSS − 0.3 to VDD + 0.3 V Operation ambient temperature Topr − −40 to +85 °C Storage temperature Tstg − −40 to +125 °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions.  Thermal Resistance Value Table 6 Item Symbol Condition Min. Typ. Max. Unit Junction-to-ambient thermal resistance*1 θja SNT-8A Board A − 211 − ° C/W Board B − 173 − ° C/W Board C − − − ° C/W Board D − − − ° C/W Board E − − − ° C/W *1. Test environment: compliance with JEDEC STANDARD JESD51-2A Remark Refer to " Power Dissipation" and "Test Board" for details.

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.2_00 S-8224A/B Series  Electrical Characteristics Table 7 (Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection voltage Overcharge detection voltage n Ta = +25°C VCU − 0.020 VCU VCU + 0.020 V 1 Ta = −10°C to +60°C*1 VCU − 0.025 VCU VCU + 0.025 V 1 Overcharge hysteresis voltage n −550 mV ≤ VHC ≤ −300 mV V HC × 1.2 V HC V HC × 0.8 V 1 −250 mV ≤ VHC ≤ −100 mV VHC − 0.050 VHC VHC + 0.050 V 1 VHC = −50 mV VHC − 0.025 VHC VHC + 0.025 V 1 VHC = 0.0 mV VHC − 0.025 VHC VHC + 0.020 V 1 Input voltage Operation voltage between VDD pin and VSS pin V DSOP − 3.6 − 28 V − CTL pin input voltage "H" V CTLH − V DD × 0.95 − − V 2 CTL pin input voltage "L" VCTLL − − − V DD × 0.4 V 2 Output voltage CO pin output voltage "H" V COH S-8224B Series 5.0 8.0 11.5 V 2 Input Current Current consumption during operation IOPE V1 = V2 = V3 = V4 = V CU − 1.0 V − 0.25 0.6 μA3 Current consumption during overdischarge IOPED V1 = V2 = V3 = V4 = V CU × 0.5 V − − 0.3 μA 3 VC1 pin input current IVC1 V1 = V2 = V3 = V4 = V CU − 1.0 V − − 0.3 μA4 VCn pin input current (n = 2, 3, 4) I VCn V1 = V2 = V3 = V4 = VCU − 1.0 V −0.3 0 0.3 μA4 CTL pin input current "H" I CTLH − 0.6 1.3 2.0 μA 4 CTL pin input current "L" I CTLL − −0.15 − − μA 4 Output Current CO pin source current ICOH S-8224A Series (CMOS output product), S-8224B Series − − −20 μA5 CO pin sink current ICOL − 20 − − μA5 CO pin leakage current ICOLL S-8224A Series (Nch open-drain output product) − − 0.1 μA5 Delay Time Overcharge detection delay time t CU − t CU × 0.8 t CU t CU × 1.2 s 1 Overcharge release delay time t CL tCL = 2 ms 1.6 2.0 3.0 ms 1 tCL = 64 ms 51.2 64 76.8 ms 1 Overcharge timer reset delay time t TR − 6 12 20 ms 1 CTL pin response delay time t CTL − − − 2.5 ms 2 Transition time to test mode tTST − − − 10 ms 1 *1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production.

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) S-8224A/B Series Rev.1.2_00  Test Circuits 1. Overcharge detection voltage, overcharge hysteresis voltage (Test circuit 1) Set SW1 to OFF in CMOS output product of the S-8224A Se ries and in the S-8224B Series, and set SW1 to ON in Nch open-drain output product of the S-8224A Series. 1. 1 Overcharge detection voltage n (VCUn) Set V0 = 0 V, V1 = V2 = V3 = V4 = VCU − 0.05 V in test circuit 1. The overcharge detection voltage 1 (VCU1) is the V1 voltage when the CO pin output inverts after the voltage of V1 has been gradually increased. Overcharge detection voltage (VCUn) (n = 2 to 4) can be determined in the same way as when n = 1. 1. 2 Overcharge hysteresis voltage n (VHCn) Set V0 = 0 V, V1 = VCU + 0.05 V, V2 = V3 = V4 = 2.5 V. The overcharge hysteresis voltage 1 (VHC1) is the difference between V1 voltage and V CU1 when the CO pin output inverts again a fter the V1 voltage has been gradually decreased. Overcharge hysteresis voltage (VHCn) (n = 2 to 4) can be determined in the same way as when n = 1. 2. CTL pin input voltage (Test circuit 2) Set SW1 to OFF in CMOS output product of the S-8224A Se ries and in the S-8224B Series, and set SW1 to ON in Nch open-drain output product of the S-8224A Series. 2. 1 CTL pin input voltage "H" (VCTLH) Set V1 = V2 = V3 = V4 = 3.5 V, V5 = 0 V. The CTL pin input voltage "H" (VCTLH) is the V5 voltage when the CO pin output inverts after the voltage of V5 has been gradually increased. 2. 2 CTL pin input voltage "L" (VCTLL) Set V5 =14 V. The CTL pin input voltage "L" (VCTLL) is the V5 voltage when the CO pin output inverts after the voltage of V5 has been gradually decreased. 3. Output voltage (S-8224B Series) (Test circuit 2) 3. 1 CO pin output voltage "H" The CO pin output voltage "H" (VCOH) is the voltage between the CO pin and the VSS pin when V1 = V2 = V3 = V4 = 3.5 V, V5 = 0 V. 4. Input current (Test circuit 4) 4. 1 CTL pin input current "H" (ICTLH) Set SW2 and SW3 to ON and OFF, respectively. The CTL pin input current "H" (ICTLH) is the current that flows through the CTL pin when V1 = V2 = V3 = V4 = 3.5 V. 4. 2 CTL pin input current "L" (ICTLL) Set SW2 and SW3 to OFF and ON, respectively. The CTL pin input current "L" (I CTLL) is the current that flows through the CTL pin when V1 = V2 = V3 = V4 = 3.5 V.

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.2_00 S-8224A/B Series 5. Output current (Test circuit 5) 5. 1 CMOS output product in S-8224A Series Set SW4 and SW5 to OFF. 5. 1. 1 Active "H" (1) CO pin source current (ICOH) Set SW4 to ON after setting V1 to V4 = 3.5 V, V5 = 0 V, V6 = 0.5 V. I1 is the CO pin source current (ICOH) at that time. (2) CO pin sink current (ICOL) Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 5. 1. 2 Active “L” (1) CO pin source current (ICOH) Set SW4 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V6 = 0.5 V. I1 is the CO pin source current (ICOH) at that time. (2) CO pin sink current (ICOL) Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 0 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 5. 2 Nch open-drain output product in S-8224A Series Set SW4 and SW5 to OFF. 5. 2. 1 Active "H" (1) CO pin leakage current (ICOLL) Set SW5 to ON after setting V1 to V4 = 7 V, V5 = 0 V, V7 = 28 V. I2 is the CO pin leakage current (ICOLL) at that time. (2) CO pin sink current (ICOL) Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 5. 2. 2 Active "L" (1) CO pin leakage current (ICOLL) Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V7 = 28 V. I2 is the CO pin leakage current (ICOLL) at that time. (2) CO pin sink current (ICOL) Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 0 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 5. 3 S-8224B Series Set SW4 and SW5 to OFF. 5. 3. 1 CO pin source current (ICOH) Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 0 V, V7 = VCOH − 0.5 V. I2 is the CO pin source current (ICOH) at that time. 5. 3. 2 CO pin sink current (ICOL) Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time.

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) S-8224A/B Series Rev.1.2_00 6. Overcharge detection delay time (tCU), overcharge release delay time (tCL) (Test circuit 1) Set SW1 to OFF in CMOS output product of the S-8224A Se ries and in the S-8224B Series, and set SW1 to ON in Nch open-drain output product of the S-8224A Series. Increase V1 up to 5.2 V after setting V0 = 0 V, V1 = V2 = V3 = V4 = 3.5 V. The overcharge detection delay time (tCU) is the time period until the CO pin output inverts. After that, decrease V1 down to 3.5 V. The overcharge release delay time (tCL) is the time period until the CO pin output inverts. 7. CTL pin response delay time (tCTL) (Test circuit 2) Set SW1 to OFF in CMOS output product of the S-8224A Se ries and in the S-8224B Series, and set SW1 to ON in Nch open-drain output product of the S-8224A Series. Decrease V5 down to 0 V after setting V1 = V2 = V3 = V4 = 3.5 V, V5 = 14 V. The CTL pin response delay time (tCTL) is the time period until the CO pin output inverts. 8. Overcharge timer reset delay time (tTR) (Test circuit 1) Set SW1 to OFF in CMOS output product of the S-8224A Se ries and in the S-8224B Series, and set SW1 to ON in Nch open-drain output product of the S-8224A Series. Increase V1 up to 5.2 V (first rise), and decrease V1 down to 3.5 V within the overcharge detection delay time (tCU) after setting V0 = 0 V, V1 = V2 = V3 = V4 = 3.5 V. After that, increase V1 up to 5.2 V again (second rise), and detect the time period until the CO pin output inverts. When the period from when V1 has fallen to the second rise is short, CO pin output inverts after tCU has elapsed since the first rise. If the period is gradually made longer, CO pin output inverts after tCU has elapsed since the second rise. The overcharge timer reset delay time (tTR) is the period from V1 fall until the second rise at that time. 9. Transition time to test mode (tTST) (Test circuit 1) Set SW1 to OFF in CMOS output product of the S-8224A Se ries and in the S-8224B Series, and set SW1 to ON in Nch open-drain output product of the S-8224A Series. Increase V0 up to 8.5 V, and decrease V0 again to 0 V after setting V0 = 0 V, V1 = V2 = V3 = V4 = 3.5 V. When the period from when V0 was raised to when it has fallen is short, if an overc harge detection operation is performed subsequently, the delay time is tCU. However, when the period from when V0 is raised to when it has fallen is gradually made longer, the delay time during the subse quent overcharge detection op eration is shorter than t CU. The transition time to test mode (tTST) is the period from when V0 was raised to when it has fallen at that time.

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) S-8224A/B Series Rev.1.2_00  Operation Remark Refer to " Battery Protection IC Connection Examples". 1. Normal status If the voltage of each of the batteries is lower than "the overcharge detection voltage (VCU) + the overcharge hysteresis voltage (VHC)", the CO pin output changes to "L" (active "H") or "H" (active "L"). This is called normal status. 2. Overcharge status When the voltage of one of the batteries exceeds V CU during charging under normal conditions and the status is retained for the overcharge detection delay time (tCU) or longer, CO pin output inverts. This status is called overcharge status. Connecting FET to the CO pin provides charge control and a second protection. If the voltage of each of the batteries is lower than VCU + VHC and the status is retained for the overcharge release delay time (tCL) or longer, S-8224A/B Series changes to normal status. 3. Overcharge timer reset function When an overcharge release noise that forces the voltage of one of the batteries temporarily below VCU is input during tCU from when V CU is exceeded to when charging is stopped, t CU is continuously counted if the time the overcharge release noise persists is shorter than the overcharge timer reset delay time (tTR). Under the same conditions, if the time the overcharge release noise persists is t TR or longer, counting of t CU is reset once. After that, when V CU has been exceeded, counting tCU resumes.

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.2_00 S-8224A/B Series 4. CTL pin The S-8224A/B Series has control pins. In the S-8224A/B Series, the CTL pin is used to control the output voltage of the CO pin. The CTL pin takes precedence over the overcharge detection circuit. Table 8 Status Set by CTL Pin CTL Pin CO Pin "H" Normal status*1 Open Detection status "L" Detection status *1. The status is controlled by the overcharge detection circuit. Pull-down resistor CTL*1 *1. In the S-8224A/B Series, the inversion voltage "H" to "L" or "L" to "H" of the CTL pin is the VDD pin voltage − 2.8 V typ., and does not have the hysteresis. Figure 10 Internal Equivalent Circuit of CTL Pin Caution In the S-8224A/B Series, since the CT L pin implements high resistance of 7 MΩ to 24 MΩ for pull down, be careful of external noise application. If an external noise is applied, the CO pin may become "H". Perform thorough evaluation using the actual application.

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) S-8224A/B Series Rev.1.2_00 5. Test mode In the S-8224A/B Series, the overcharge detection delay time (tCU) can be shortened by entering the test mode. The test mode can be set by retaining the VDD pin voltage 8.5 V or more higher than the VC1 pin voltage for at least 10 ms (V1 = V2 = V3 = V4 = 3.5 V, Ta = +25 °C). The status is retained by the internal latch and the test mode is retained even if the VDD pin voltage is decreased to the same voltage as that of the VC1 pin. If the CO pin becomes detection status when the delay time has elapsed after overcharge detection, the latch for retaining the test mode is reset and the S-8224A/B Series exits from the test mode. VCUn Pin voltage CO pin (Active "H") Test mode VDD pin voltage

8.5 V or

tTST = 10 ms max. VC1 pin voltage (n = 1 to 4) 32 ms typ. CO pin (Active "L") t CL Caution 1. Set the test mode when no batteries are overcharged. 2. The overcharge timer reset delay time (t TR) is not shortened in the test mode. Figure 11

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.2_00 S-8224A/B Series  Timing Charts 1. Overcharge detection operation VCUn Battery voltage CO pin (Active "H") VHCn (n = 1 to 4) tCU CO pin (Actve "L") tCL CTL pin tTR or longer t TR or shorter tTR or shorter Figure 12

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) S-8224A/B Series Rev.1.2_00 2. Overcharge timer reset operation VCUn Battery voltage CO pin (Active "H") tCU VHCn tCU or shorter tTR tTR or shorter Timer reset tTR or shorter tTR or longer (n = 1 to 4) CO pin (Active "L") Figure 13

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.2_00 S-8224A/B Series  Battery Protection IC Connection Examples 1. 4-serial cell SCP EB− EB+ BAT1 BAT2 BAT3 BAT4 FET VC1 VC2 VC3 VC4 VSS CO VDD CTL CVDD RVDD External input DP S-8224A/B Series RCTL *1. The S-8224B Series limits its CO pin output voltage to 11.5 V max., so an FET with the gate withstand voltage of 12 V can be used. Figure 14 Table 9 Constants for External Components No. Part Min. Typ. Max. Unit 1 R1 to R4 0.3 1 10 k Ω 2 C1 to C4, C VDD 0.01 0.1 1 μF

3 R VDD 300 330 1000 Ω

Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addi tion, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1 to R4 and to C1 to C4 and C VDD. 4. Since the CO pin may become detection st atus transiently when the battery is being connected, be sure to connect the positive terminal of BAT1 last in order to prevent the terminal protection fuse from cutoff.

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) S-8224A/B Series Rev.1.2_00 2. 3-serial cell SCP EB− EB+ BAT1 BAT2 BAT3 FET*1 VD1 VC2 VC3 VC4 VSS CO VDD CTL CVDD RVDD External input DP S-8224A/B Series RCTL *1. The S-8224B Series limits its CO pin output voltage to 11.5 V max., so an FET with the gate withstand voltage of 12 V can be used. Figure 15 Table 10 Constants for External Components No. Part Min. Typ. Max. Unit 1 R1 to R3 0.3 1 10 kΩ 2 C1 to C3, C VDD 0.01 0.1 1 μF Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1 to R3 and to C1 to C3 and C VDD. 4. Since the CO pin may become detection status transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the protection fuse from cutoff.

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.2_00 S-8224A/B Series 3. 2-serial cell SCP EB− EB+ BAT1 BAT2 FET VC1 VC2 VC3 VC4 VSS CO VDD CTL CVDD RVDD External input DP S-8224A/B Series RCTL Figure 16 Table 11 Constants for External Components No. Part Min. Typ. Max. Unit 1 R1 to R2 0.3 1 10 kΩ 2 C1 to C2, C VDD 0.01 0.1 1 μF Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1 to R2, and to C1 to C2 and C VDD. 4. Since the CO pin may become detection status transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the protection fuse from cutoff.

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) S-8224A/B Series Rev.1.2_00  Precaution

• Do not connect batteries charged with VCU + VHC or higher.
• If the connected batteries include a battery charged with V CU + VHC or higher, the S-8224A/B series may become overcharge status after all pins are connected.
• In some application circuits, even if an overcharged battery is not included, the order of connecting batteries may be restricted to prevent transient output of the CO pin detection pulses when the batteries are connected. Perform thorough evaluation with the actual application circuit.
• Before the battery connection, short-circuit the battery side pins R VDD and R1, shown in the figures in "  Battery Protection IC Connection Examples".
• The application conditions for the input voltage, output volt age, and load current should not exceed the power dissipation.
• Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic protection circuit.
• SII Semiconductor Corporation claims no responsibility fo r any disputes arising out of or in connection with any infringement of patents owned by a third party by products including this IC.

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.2_00 S-8224A/B Series  Example of Application Circuit 1. Overheat protection via PTC SCP EB− EB+ BAT1 BAT2 BAT3 BAT4 FET VC1 VC2 VC3 VC4 VSS CO VDD CTL CVDD RVDD PTC CCTL S-8224A/B Series First protection IC *1. The S-8224B Series limits its CO pin output voltage to 11.5 V max., so an FET with the gate withstand voltage of 12 V can be used. Figure 17 Caution 1. The above connection example will not guarantee successful operation. Perform thorough evaluation using the actual application. 2. A pull-down resistor is included in the CTL pi n. To perform overheat protection via the PTC in the S-8224A/B Series, connect the PTC before connecting batteries. 3. When the power fluctuation is large, connect the power supply of the PTC to the VDD pin of the S-8224A/B Series. 4. Since the CO pin may become detection status transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff. [For SCP, contact] Global Sales & Marketing Division, Dexerials Corporation Gate City Osaki East Tower 8F, 1-11-2 Osaki, Shinagawa-ku, Tokyo, 141-0032, Japan TEL +81-3-5435-3946 Contact Us: http://www.dexerials.jp/en/ [For PTC, contact] Murata Manufacturing Co., Ltd. Thermistor Products Department Nagaokakyo-shi, Kyoto, 617-8555, Japan TEL +81-75-955-6863 Contact Us: http://www.murata.com/contact/index.html

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) S-8224A/B Series Rev.1.2_00  Characteristics (Typical Data) 1. Detection voltage 1. 1 VCU vs. Ta VCU = 4.500 V 1. 2 VCU + VHC vs. Ta VHC = −400 mV VCU [V] 4.520 4.510 4.500 4.490 4.480 40 25 25 50 75 85 Ta [C] VCU + VHC [V] 40 25 25 50 75 85 Ta [C] 4.200 4.150 4.100 4.050 4.000 2. Current consumption 2. 1 IOPE vs. Ta VDD = 14 V 2. 2 IOPED vs. Ta VDD = 9 V IOPE [A] 0.4 0.3 0.2 0.1 0.0 40 25 25 50 75 85 Ta [C] 0.5 IOPED [A] 0.3 0.2 0.1 0.0 40 25 25 50 75 85 Ta [C] 2. 3 IOPE vs. VDD Ta = +25°C V DD [V] IOPE [A] 01 0 51 5 2 0 25 30 3. Delay time 3. 1 tCU vs. Ta VDD = 15.7 V tCU [s] 0.0 2.0 1.5 1.0 0.5 Ta [C] 40 25 25 50 75 850

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.2_00 S-8224A/B Series 4. CTL pin 4. 1 VCTLL vs. Ta VDD = 14 V 4. 2 ICTLH vs. Ta VDD = 14 V VCTLL [V] 10.0 12.0 11.5 11.0 10.5 Ta [C] 40 25 25 50 75 850 ICTLH [A] 0.5 2.5 2.0 1.5 1.0 Ta [C] 40 25 25 50 75 850 5. Output current 5. 1 ICOH vs. VDD (S-8224A Series) Ta = +25°C 5. 2 ICOH vs. VDD (S-8224B Series) Ta = +25°C 200 180 160 140 80 V DD [V] ICOH [A] 01 051 5 2 0 2 5 120 100 50 40 10 VDD [V] ICOH [A] 01 051 5 2 0 2 5 30 20 5. 3 ICOL vs. VDD Ta = +25°C 5. 4 ICOLL vs. VDD Ta = +25°C 100 VDD [V] ICOL [A] 01 051 5 2 0 2 5 0.00 0.02 0.06 0.10 VDD [V] ICOLL [A] 01 051 5 2 0 2 5 0.04 0.08 6. Output voltage 6. 1 VCOH vs. VDD VDD [V] VCOH [V] 01 0 51 5 2 0 2 5

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) S-8224A/B Series Rev.1.2_00  Marking Specifications 1. SNT-8A Top view 14 3 2 85 6 7 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (1) Blank (2) to (4) Product code (Refer to Product name vs. Product code) (5), (6) Blank (7) to (11) Lot number Product name vs. Product code Product name Product code (2) (3) (4) S-8224AAS-I8T1U 5 R S S-8224AAT-I8T1U 5 R T S-8224AAU-I8T1U 5 R U S-8224AAV-I8T1U 5 R V S-8224AAW-I8T1U 5 R W S-8224AAX-I8T1U 5 R Y Product name Product code (2) (3) (4) S-8224BAA-I8T1U 5 S A S-8224BAB-I8T1U 5 S B S-8224BAC-I8T1U 5 S C

BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.2_00 S-8224A/B Series  Power Dissipation 0 25 50 75 100 125 150 1750.0 0.2 0.4 0.6 0.8 1.0 Ambient temperature (Ta) [C] Power dissipation (PD) [W] Tj = 125C max. SNT-8A B A Board Power Dissipation (PD) A 0.47 W B 0.58 W C − D − E −

(1) (2) Thermal via - Material FR-4 Number of copper foil layer 4 Copper foil layer [mm] Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.070 Thermal via - Board B Item Specification Size [mm] 114.3 x 76.2 x t1.6 Number of copper foil layer 2 Copper foil layer [mm] Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.070 Board A Item Specification Size [mm] 114.3 x 76.2 x t1.6 Material FR-4 IC Mount Area SNT-8A Test Board No. SNT8A-A-Board-SD-1.0 SII Semiconductor Corporation

/X53/X49/X49/X20/X53/X65/X6D/X69/X63/X6F/X6E/X64/X75/X63/X74/X6F/X72/X20/X43/X6F/X72/X70/X6F/X72/X61/X74/X69/X6F/X6E /X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X31/X2E/X39/X37/XB1/X30/X2E/X30/X33 /X30/X2E/X32/XB1/X30/X2E/X30/X35 /X30/X2E/X34/X38/XB1/X30/X2E/X30/X32 /X30/X2E/X30/X38 /X6D/X6D /X53/X4E/X54/X2D/X38/X41/X2D/X41/X2D/X50/X4B/X47/X20/X44/X69/X6D/X65/X6E/X73/X69/X6F/X6E/X73 /X50/X48/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X32/X2E/X31 /X4E/X6F/X2E/X20/X50/X48/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X32/X2E/X31 /X30/X2E/X35 /X2B/X30/X2E/X30/X35 /X2D/X30/X2E/X30/X32/X31 /X32/X33/X34 /X35/X36/X37/X38

/X53/X49/X49/X20/X53/X65/X6D/X69/X63/X6F/X6E/X64/X75/X63/X74/X6F/X72/X20/X43/X6F/X72/X70/X6F/X72/X61/X74/X69/X6F/X6E /X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X6D/X6D /X50/X48/X30/X30/X38/X2D/X41/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X30 /X53/X4E/X54/X2D/X38/X41/X2D/X41/X2D/X43/X61/X72/X72/X69/X65/X72/X20/X54/X61/X70/X65 /X4E/X6F/X2E/X20/X50/X48/X30/X30/X38/X2D/X41/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X30 /X46/X65/X65/X64/X20/X64/X69/X72/X65/X63/X74/X69/X6F/X6E /X34/X2E/X30/XB1/X30/X2E/X31/X32/X2E/X30/XB1/X30/X2E/X30/X35 /X34/X2E/X30/XB1/X30/X2E/X31 /XF8/X31/X2E/X35/X2B/X30/X2E/X31 /X20/X2D/X30 /XF8/X30/X2E/X35/XB1/X30/X2E/X31 /X32/X2E/X32/X35/XB1/X30/X2E/X30/X35 /X30/X2E/X36/X35/XB1/X30/X2E/X30/X35 /X30/X2E/X32/X35/XB1/X30/X2E/X30/X35 /X32/X31/X33/X34 /X37/X38/X36/X35 /X35/XB0

/X53/X49/X49/X20/X53/X65/X6D/X69/X63/X6F/X6E/X64/X75/X63/X74/X6F/X72/X20/X43/X6F/X72/X70/X6F/X72/X61/X74/X69/X6F/X6E /X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X31/X32/X2E/X35/X6D/X61/X78/X2E /X39/X2E/X30/XB1/X30/X2E/X33 /XF8/X31/X33/XB1/X30/X2E/X32 /X28/X36/X30/XB0/X29 /X28/X36/X30/XB0/X29 /X45/X6E/X6C/X61/X72/X67/X65/X64/X20/X64/X72/X61/X77/X69/X6E/X67/X20/X69/X6E/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X72/X61/X6C/X20/X70/X61/X72/X74 /X51/X54/X59/X2E /X50/X48/X30/X30/X38/X2D/X41/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X30 /X6D/X6D /X53/X4E/X54/X2D/X38/X41/X2D/X41/X2D/X52/X65/X65/X6C /X4E/X6F/X2E/X20/X50/X48/X30/X30/X38/X2D/X41/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X30 /X35/X2C/X30/X30/X30

/X53/X49/X49/X20/X53/X65/X6D/X69/X63/X6F/X6E/X64/X75/X63/X74/X6F/X72/X20/X43/X6F/X72/X70/X6F/X72/X61/X74/X69/X6F/X6E /X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X6D/X6D /X53/X4E/X54/X2D/X38/X41/X2D/X41 /X20/X20/X20/X20/X20/X20/X2D/X4C/X61/X6E/X64/X20/X52/X65/X63/X6F/X6D/X6D/X65/X6E/X64/X61/X74/X69/X6F/X6E /X50/X48/X30/X30/X38/X2D/X41/X2D/X4C/X2D/X53/X44/X2D/X34/X2E/X31 /X30/X2E/X33/X30/X2E/X32 /X30/X2E/X35/X32 /X32/X2E/X30/X31 /X30/X2E/X35/X32 /X4E/X6F/X2E/X20/X50/X48/X30/X30/X38/X2D/X41/X2D/X4C/X2D/X53/X44/X2D/X34/X2E/X31 /X43/X61/X75/X74/X69/X6F/X6E /X31/X2E/X20/X44/X6F/X20/X6E/X6F/X74/X20/X64/X6F/X20/X73/X69/X6C/X6B/X73/X63/X72/X65/X65/X6E/X20/X70/X72/X69/X6E/X74/X69/X6E/X67/X20/X61/X6E/X64/X20/X73/X6F/X6C/X64/X65/X72/X20/X70/X72/X69/X6E/X74/X69/X6E/X67/X20/X75/X6E/X64/X65/X72/X20/X74/X68/X65/X20/X6D/X6F/X6C/X64/X20/X72/X65/X73/X69/X6E/X20/X6F/X66/X20/X74/X68/X65/X20/X70/X61/X63/X6B/X61/X67/X65/X2E /X32/X2E/X20/X54/X68/X65/X20/X74/X68/X69/X63/X6B/X6E/X65/X73/X73/X20/X6F/X66/X20/X74/X68/X65/X20/X73/X6F/X6C/X64/X65/X72/X20/X72/X65/X73/X69/X73/X74/X20/X6F/X6E/X20/X74/X68/X65/X20/X77/X69/X72/X65/X20/X70/X61/X74/X74/X65/X72/X6E/X20/X75/X6E/X64/X65/X72/X20/X74/X68/X65/X20/X70/X61/X63/X6B/X61/X67/X65/X20/X73/X68/X6F/X75/X6C/X64/X20/X62/X65/X20/X30/X2E/X30/X33/X20/X6D/X6D /X20/X6F/X72/X20/X6C/X65/X73/X73/X20/X66/X72/X6F/X6D/X20/X74/X68/X65/X20/X6C/X61/X6E/X64/X20/X70/X61/X74/X74/X65/X72/X6E/X20/X73/X75/X72/X66/X61/X63/X65/X2E /X33/X2E/X20/X4D/X61/X74/X63/X68/X20/X74/X68/X65/X20/X6D/X61/X73/X6B/X20/X61/X70/X65/X72/X74/X75/X72/X65/X20/X73/X69/X7A/X65/X20/X61/X6E/X64/X20/X61/X70/X65/X72/X74/X75/X72/X65/X20/X70/X6F/X73/X69/X74/X69/X6F/X6E/X20/X77/X69/X74/X68/X20/X74/X68/X65/X20/X6C/X61/X6E/X64/X20/X70/X61/X74/X74/X65/X72/X6E/X2E /X34/X2E/X20/X52/X65/X66/X65/X72/X20/X74/X6F/X20/X22/X53/X4E/X54/X20/X50/X61/X63/X6B/X61/X67/X65/X20/X55/X73/X65/X72/X27/X73/X20/X47/X75/X69/X64/X65/X22/X20/X66/X6F/X72/X20/X64/X65/X74/X61/X69/X6C/X73/X2E /X31/X2E/X20 /X28/X30/X2E/X32/X35/X20/X6D/X6D/X20/X6D/X69/X6E/X2E/X20/X2F/X20/X30/X2E/X33/X30/X20/X6D/X6D/X20/X74/X79/X70/X2E/X29 /X32/X2E/X20 /X20/X28/X31/X2E/X39/X36/X20/X6D/X6D/X20/X7E/X20/X32/X2E/X30/X36/X20/X6D/X6D/X29 /X31/X2E /X32/X2E /X30/X2E/X30/X33/X20/X6D/X6D /X33/X2E /X34/X2E /X53/X4E/X54 /X31/X2E/X20/X50/X61/X79/X20/X61/X74/X74/X65/X6E/X74/X69/X6F/X6E/X20/X74/X6F/X20/X74/X68/X65/X20/X6C/X61/X6E/X64/X20/X70/X61/X74/X74/X65/X72/X6E/X20/X77/X69/X64/X74/X68/X20/X28/X30/X2E/X32/X35/X20/X6D/X6D/X20/X6D/X69/X6E/X2E/X20/X2F/X20/X30/X2E/X33/X30/X20/X6D/X6D/X20/X74/X79/X70/X2E/X29/X2E /X32/X2E/X20/X44/X6F/X20/X6E/X6F/X74/X20/X77/X69/X64/X65/X6E/X20/X74/X68/X65/X20/X6C/X61/X6E/X64/X20/X70/X61/X74/X74/X65/X72/X6E/X20/X74/X6F/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X65/X72/X20/X6F/X66/X20/X74/X68/X65/X20/X70/X61/X63/X6B/X61/X67/X65/X20/X28/X31/X2E/X39/X36/X20/X6D/X6D/X20/X74/X6F/X20/X32/X2E/X30/X36/X6D/X6D/X29/X2E /X31 /X32 /X31/X2E /X32/X2E/X20 /X28/X31/X2E/X39/X36/X20/X6D/X6D/X20/X7E/X20/X32/X2E/X30/X36/X20/X6D/X6D/X29 /X28/X30/X2E/X32/X35/X20/X6D/X6D/X20/X6D/X69/X6E/X2E/X20/X2F/X20/X30/X2E/X33/X30/X20/X6D/X6D/X20/X74/X79/X70/X2E/X29

Disclaimers (Handling Precautions) 1. All the information described herei n (product data, specifications, figur es, tables, programs, algorithms and application circuit examples, etc.) is cu rrent as of publishing dat e of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. SII Semiconductor Corporation is not responsible for damages caused by the reasons other than the products or infringement of third-party intellectual property rights and any other rights due to the use of the information described herein. 3. SII Semiconductor Corporation is not responsible for da mages caused by the incorrect information described herein. 4. Take care to use the products described herein within their specified ranges. Pay special attention to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. SII Semiconductor Corporation is not re sponsible for damages caused by failu res and/or accidents, etc. that occur due to the use of products outside their specified ranges. 5. When using the products described herei n, confirm their applicatio ns, and the laws and regulat ions of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products described herein, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products described herein must not be used or prov ided (exported) for the purposes of the development of weapons of mass destruction or militar y use. SII Semiconductor Corporation is not responsible for any provision (export) to those whose purpose is to develop, manufactur e, use or store nuclear, biol ogical or chemical weapons, missiles, or other military use. 8. The products described herein are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equi pment, disaster prevention sy stems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do not use those products without the prior written permission of SII Semiconductor Corporation. Especially, the products described her ein cannot be used for life support dev ices, devices implanted in the human body and devices that directly affect human life, etc. Prior consultation with our sales office is required when considering the above uses. SII Semiconductor Corporation is not responsible for damages caused by unauthorized or unspecified use of our products. 9. Semiconductor products may fail or malfunction with some probability. The user of these products s hould therefore take responsibility to gi ve thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system must be sufficiently evaluated and applied on customer's own responsibility. 10. The products described herein are not designed to be radi ation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products described herein do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Take care when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products described herein, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright info rmation and know-how of SII Semiconductor Corporation. The information described herein does not convey any lic ense under any intellectual property rights or any other rights belonging to SII Semiconductor Corporation or a third party. Reproduction or copying of the information described herein for the purpose of disclosing it to a thir d-party without the express permission of SII Semiconductor Corporation is strictly prohibited. 14. For more details on the information de scribed herein, contact our sales office. 1.0-2016.01 www.sii-ic.com