S8215A

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www.sii-ic.com BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) © Seiko Instruments Inc., 2010-2015 Rev.2.3_00 Seiko Instruments Inc. 1 The S-8215A Series is used for secondary pr otection of lithium-ion rechargeable ba tteries, and incorporates high-accuracy voltage detection circuits and delay circuits. Short-circuiting between cells makes it possible for serial connection of three cells to five cells.  Features

• High-accuracy voltage detection circuit for each cell Overcharge detection voltage n (n = 1 to 5) 3.60 V to 4.70 V (50 mV step) Accuracy ±25 mV (Ta = +25°C) Accuracy ±30 mV (Ta = −5°C to +55°C) Overcharge hysteresis voltage n (n = 1 to 5) 0.0 mV to −550 mV (50 mV step) −300 mV to −550 mV Accuracy ±20% −100 mV to −250 mV Accuracy ±50 mV 0.0 mV to −50 mV Accuracy ±25 mV
• Delay times for overcharge detection can be set by an inte rnal circuit only (External capacitors are unnecessary).
• Output form is selectable: CMOS output, Nch open-drain output, Pch open-drain output
• Output logic is selectable : Active "H", active "L"
• High-withstand voltage device: Absolute maximum rating 28 V
• Wide operation voltage range: 3.6 V to 26 V
• Wide operation temperature range: Ta = −40°C to +85°C
• Low current consumption At V CUn − 1.0 V for each cell: 3.0 μA max. (Ta = +25°C) At 2.3 V for each cell: 1.7 μ A max. (Ta = +25°C)
• Lead-free (Sn 100%), halogen-free  Application
• Lithium-ion rechargeable battery pack (for secondary protection)  Packages
• TMSOP-8
• SNT-8A

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) S-8215A Series Rev.2.3_00 Seiko Instruments Inc. 2  Block Diagram VC4 VC3 VC2 CO*1 VC1 VSS VDD Overcharge detection comparator 1 Overcharge detection comparator 2 Overcharge detection comparator 3 Overcharge detection comparator 5 Reference voltage 1 Reference voltage 2 Reference voltage 3 Reference voltage 5 Oscillator Overcharge detection / release delay circuit VC5 Overcharge detection comparator 4 Reference voltage 4 Control circuit *1. The CO pin is connected only to Nch transistor in the case of Nch open-drain output. The CO pin is connected only to Pch trans istor in the case of Pch open-drain output. Remark The diodes in the figure are parasitic diodes. Figure 1

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.2.3_00 S-8215A Series Seiko Instruments Inc. 3  Product Name Structure 1. Product name S-8215A xx - xxxx U Package abbreviation and IC packing specifications*1 K8T2: TMSOP-8, Tape I8T1: SNT-8A, Tape Serial code*2 Sequentially set from AA to AZ Environmental code U: Lead-free (Sn 100%), halogen-free *1. Refer to the tape drawing. *2. Refer to "3. Product name list". 2. Packages Table 1 Package Drawing Codes Package Name Dimension Tape Reel Land TMSOP-8 FM008-A-P-SD FM008-A-C-SD FM008-A-R-SD − SNT-8A PH008-A-P-SD PH008-A-C- SD PH008-A-R-SD PH008-A-L-SD

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) S-8215A Series Rev.2.3_00 Seiko Instruments Inc. 4 3. Product name list 3. 1 TMSOP-8 Table 2 Product Name Overcharge Detection Voltage [VCU] Overcharge Hysteresis Voltage [VHC] Overcharge Detection Delay Time [tCU] Output Form Output Logic S-8215AAA-K8T2U 4.300 V −0.30 V 4.0 s CMOS output Active "H" S-8215AAB-K8T2U 4.275 V −0.05 V 2.0 s Nch open-drain output Active "L" S-8215AAC-K8T2U 4.150 V −0.25 V 1.0 s CMOS output Active "H" S-8215AAD-K8T2U 4.350 V −0.25 V 2.0 s CMOS output Active "H" S-8215AAE-K8T2U 4.325 V −0.05 V 1.0 s Nch open-drain output Active "L" S-8215AAF-K8T2U 4.220 V −0.10 V 1.0 s CMOS output Active "H" S-8215AAH-K8T2U 4.325 V −0.30 V 1.0 s Nch open-drain output Active "L" S-8215AAI-K8T2U 4.250 V −0.25 V 1.0 s CMOS output Active "H" S-8215AAJ-K8T2U 4.400 V −0.10 V 2.0 s CMOS output Active "H" S-8215AAK-K8T2U 4.150 V −0.05 V 2.0 s Nch open-drain output Active "L" S-8215AAL-K8T2U 4.150 V −0.50 V 2.0 s Nch open-drain output Active "L" S-8215AAM-K8T2U 4.150 V −0.05 V 2.0 s CMOS output Active "L" S-8215AAN-K8T2U 4.150 V −0.50 V 2.0 s CMOS output Active "L" S-8215AAO-K8T2U 4.350 V −0.25 V 4.0 s CMOS output Active "H" S-8215AAP-K8T2U 4.275 V −0.50 V 1.0 s CMOS output Active "H" S-8215AAQ-K8T2U 4.275 V −0.05 V 1.0 s CMOS output Active "H" Remark Please contact our sales office for the products wi th detection voltage value other than those specified above. 3. 2 SNT-8A Table 3 Product Name Overcharge Detection Voltage [VCU] Overcharge Hysteresis Voltage [VHC] Overcharge Detection Delay Time [tCU] Output Form Output Logic S-8215AAA-I8T1U 4.300 V −0.30 V 4.0 s CMOS output Active "H" S-8215AAG-I8T1U 4.220 V −0.05 V 1.0 s CMOS output Active "H" Remark Please contact our sales office for the products with detection voltage value other than those specified above.

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.2.3_00 S-8215A Series Seiko Instruments Inc. 5  Pin Configurations 1. TMSOP-8 Top view Figure 2 Table 4 Pin No. Symbol Description

1 VDD Input pin for positive power supply

2 VC1 Positive voltage connection pin of battery 1

3 VC2 Negative voltage connection pin of battery 1

Positive voltage connection pin of battery 2

4 VC3 Negative voltage connection pin of battery 2

Positive voltage connection pin of battery 3

5 VC4 Negative voltage connection pin of battery 3

Positive voltage connection pin of battery 4

6 VC5 Negative voltage connection pin of battery 4

Positive voltage connection pin of battery 5

7 VSS Input pin for negative power supply

Negative voltage connection pin of battery 5

8 CO FET gate connection pin for charge control

1. SNT-8A Top view Figure 3 Table 5 Pin No. Symbol Description

Positive voltage connection pin of battery 2 Positive voltage connection pin of battery 3 Positive voltage connection pin of battery 4 Positive voltage connection pin of battery 5 Negative voltage connection pin of battery 5

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) S-8215A Series Rev.2.3_00 Seiko Instruments Inc. 6  Absolute Maximum Ratings Table 6 (Ta = +25°C unless otherwise specified) Item Symbol Applied Pin Absolute Maximum Rating Unit Input voltage between VDD pin and VSS pin V DS VDD VSS − 0.3 to VSS + 28 V Input pin voltage VIN VC1, VC2, VC3, VC4, VC5 V SS − 0.3 to VDD + 0.3 V CO pin output voltage CMOS output product VCO CO VSS − 0.3 to VDD + 0.3 V Nch open-drain output product VSS − 0.3 to VSS + 28 V Pch open-drain output product VDD − 28 to VDD + 0.3 V Power dissipation TMSOP-8 PD − 650*1 mW SNT-8A 450*1 mW Operation ambient temperature Topr − −40 to +85 °C Storage temperature Tstg − −40 to +125 °C *1. When mounted on board [Mounted board] (1) Board size: 114.3 mm × 76.2 mm × t1.6 mm (2) Name: JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 0 50 100 150 800 Power Dissipation (PD) [mW] Ambient Temperature (Ta) [°C] TMSOP-8 400 600 200 SNT-8A Figure 4 Power Dissipation of Package (When Mounted on Board)

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.2.3_00 S-8215A Series Seiko Instruments Inc. 7  Electrical Characteristics Table 7 (Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection Voltage Overcharge detection voltage n (n = 1, 2, 3, 4, 5) VCUn − VCU − 0.025 VCU VCU + 0.025 V 1 Ta = −5°C to +55°C*1 VCU − 0.030 VCU VCU + 0.030 V 1 Overcharge hysteresis voltage n (n = 1, 2, 3, 4, 5) VHCn −550 mV ≤ VHC ≤ −300 mV V HC × 0.8 VHC VHC × 1.2 V 1 −250 mV ≤ VHC ≤ −100 mV VHC − 0.050 VHC VHC + 0.050 V 1 VHC = −50 mV, 0 mV VHC − 0.025 VHC VHC + 0.025 V 1 Input Voltage Operation voltage between VDD pin and VSS pin VDSOP − 3.6 − 26 V − Input Current Current consumption during operation IOPE V1 = V2 = V3 = V4 = V5 = VCU − 1.0 V − 1.6 3.0 μA 3 Current consumption during overdischarge IOPED V1 = V2 = V3 = V4 = V5 = 2.3 V − 0.8 1.7 μA 3 VC1 pin current IVC1 V1 = V2 = V3 = V4 = V5 = VCU − 1.0 V − 0.2 0.4 μA 4 VCn pin current (n = 2, 3, 4, 5) I VCn V1 = V2 = V3 = V4 = V5 = VCU − 1.0 V −0.3 0 0.3 μA 4 Output Current (CMOS Output Product) CO pin sink current ICOL − 0.4 − − mA 5 CO pin source current ICOH − 20 − − μA 5 Output Current (Nch Open-drain Output Product) CO pin sink current ICOL − 0.4 − − mA 5 CO pin leakage current "L" ICOLL − − − 0.1 μA 5 Output Current (Pch Open-drain Output Product) CO pin source current ICOH − 20 − − μA 5 CO pin leakage current "H" ICOLH − − − 0.1 μA 5 Delay Time Overcharge detection delay time t CU − tCU × 0.8 tCU tCU × 1.2 s 1 Overcharge timer reset delay time tTR − 6 12 20 ms 1 Transition time to test mode tTST − − − 80 ms 2 *1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production.

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) S-8215A Series Rev.2.3_00 Seiko Instruments Inc. 8  Test Circuits 1. Overcharge detection voltage, overcharge hysteresis voltage (Test circuit 1) 1. 1 Overcharge detection voltage n (VCUn) Set V1 = V2 = V3 = V4 = V5 = VCU − 0.05 V. The overcharge detection voltage 1 (VCU1) is the V1 voltage when the CO pin’s output changes after the voltage of V1 has been gradually increased. Overcharge detection voltage (VCUn) (n = 2 to 5) can be determined in the same way as when n = 1. 1. 2 Overcharge hysteresis voltage n (VHCn) Set V1 = V CU + 0.05 V, V2 = V3 = V4 = V5 = 2.5 V. The overcharge hysteresis voltage 1 (V HC1) is the difference between V1 voltage and VCU1 when the CO pin's output changes after the V1 voltage has been gradually decreased. Overcharge hysteresis voltage (VHCn) (n = 2 to 5) can be determined in the same way as when n = 1. 2. Output current (Test circuit 5) 2. 1 Output current of CMOS output product Set SW1 and SW2 to OFF. 2. 1. 1 Active "H" (1) CO pin source current (I COH) Set SW1 to ON after setting V1 = 5.5 V, V2 to V5 = 3.0 V, V6 = 0.5 V. I1 is the CO pin source current (ICOH) at that time. (2) CO pin sink current (ICOL) Set SW2 to ON after setting V1 to V5 = 3.5 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 2. 1. 2 Active "L" (1) CO pin source current (ICOH) Set SW1 to ON after setting V1 to V5 = 3.5 V, V6 = 0.5 V. I1 is the CO pin source current (ICOH) at that time. (2) CO pin sink current (ICOL) Set SW2 to ON after setting V1 = 5.5 V, V2 to V5 = 3.0 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 2. 2 Output current of Nch open-drain output product Set SW1 and SW2 to OFF. 2. 2. 1 Active "H" (1) CO pin leakage current "L" (I COLL) Set SW2 to ON after se tting V1 = 5.5 V, V2 to V5 = 3.0 V, V7 = 17.5 V. I2 is the CO pin leakage current "L" (ICOLL) at that time. (2) CO pin sink current (ICOL) Set V1 to V5 = 3.5 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 2. 2. 2 Active "L" (1) CO pin leakage current "L" (ICOLL) Set SW2 to ON after setting V1 to V5 = 3.5 V, V7 = 17.5 V. I2 is the CO pin leakage current "L" (ICOLL) at that time. (2) CO pin sink current (ICOL)

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.2.3_00 S-8215A Series Seiko Instruments Inc. 9 2. 3 Output current of Pch open-drain output product Set SW1 and SW2 to OFF. 2. 3. 1 Active "H" (1) CO pin source current (ICOH) Set SW1 to ON after setting V1 = 5.5 V, V2 to V5 = 3.0 V, V6 = 0.5 V. I1 is the CO pin source current (ICOH) at that time. (2) CO pin leakage current "H" (ICOLH) Set V1 to V5 = 3.5 V, V6 = 17.5 V. I1 is the CO pin leakage current "H" (ICOLH) at that time. 2. 3. 2 Active "L" (1) CO pin source current (ICOH) Set SW1 to ON after setting V1 to V5 = 3.5 V, V6 = 0.5 V. I1 is the CO pin source current (ICOH) at that time. (2) CO pin leakage current "H" (ICOLH) 3. Overcharge detection delay time (tCU) (Test circuit 1) Increase V1 up to 5.0 V after setting V1 = V2 = V3 = V4 = V5 = 3.5 V. The overcharge detection delay time (tCU) is the time period until the CO pin output changes. 4. Overcharge timer reset delay time (tTR) (Test circuit 1) Increase V1 up to 5.0 V (first rise), and decrease V1 down to 3.5 V within t CU after setting V1 = V2 = V3 = V4 = V5 = 3.5 V. After that, increase V1 up to 5.0 V again (second rise), and detect the time period till the CO pin output changes. When the period from when V1 has fallen to the second rise is short, CO pin output changes after tCU has elapsed since the first rise. If the period is gradually made longer, CO pin output changes after tCU has elapsed since the second rise. The overcharge timer reset delay time (tTR) is the period from V1 fall till the second rise at that time. 5. Transition time to test mode (tTST) (Test circuit 2) Increase V6 up to 5.0 V, and decrease V6 again to 0 V after setting V1 = V2 = V3 = V4 = V5 = 3.5 V, and V6 = 0 V. When the period from when V6 was raised to when it has fallen is short, if an overc harge detection operation is performed subsequently, the delay time is t CU. However, when the period from when V6 is raised to when it has fallen is gradually made longer, the delay time during the subse quent overcharge detection op eration is shorter than t CU. The transition time to test mode (tTST) is the period from when V6 was raised to when it has fallen at that time.

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.2.3_00 S-8215A Series Seiko Instruments Inc. 11  Operation Remark Refer to " Battery Protection IC Connection Examples". 1. Normal status If the voltage of each of the batteries is lower than "the overcharge detection voltage n (V CUn) + the overcharge hysteresis voltage n (V HCn)", the CO pin output changes to "L" (Active "H ") or "H" (Active L"). This is called normal status. 2. Overcharge status When the voltage of one of the batteries exceeds V CUn during charging under normal c onditions and the status is retained for the overcharge detection delay time (tCU) or longer, the CO pin output changes. This is called overcharge status. Connecting FET to the CO pin provides charge control and a second protection. If the voltage of each of the batteries is lower than VCUn + VHCn and the status is retained for 2.0 ms typ. or longer, the S-8215A Series changes to normal status. 3. Overcharge timer reset When an overcharge release noise that forces the voltage of one of the batteries temporarily below VCUn is input during tCU from when V CUn is exceeded to when charging is stopped, t CU is continuously counted if the time the overcharge release noise persists is shorter than the overcharge timer reset delay time (tTR). Under the same conditions, if the time the overcharge release noise persists is t TR or longer, counting of t CU is reset once. After that, when V CUn has been exceeded, counting tCU resumes.

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) S-8215A Series Rev.2.3_00 Seiko Instruments Inc. 12 4. Test mode The overcharge detection delay time (tCU) can be shortened by entering the test mode. The test mode can be set by retaining the VDD pin voltage 5.0 V or more higher than the VC1 pin voltage for the transition time to test mode (t TST) or longer. The status is retained by the internal latch and the test mode is retained even if the VDD pin voltage is decreased to the same voltage as that of the VC1 pin voltage. After that, the latch for retaining the test mode is rese t and the S-8215A Series exits from test mode under the overcharge status. VCUn Pin voltage CO pin (Active "H") Test mode VDD pin voltage

5.0 V or

tTST = 80 ms max. VC1 pin voltage (n = 1 to 5) 32 ms typ. CO pin (Active "L") 2.0 ms typ. Figure 10 Caution 1. When the VDD pin voltage is decreased to lower than the UVLO voltage of 2 V typ., the S-8215A Series exits from test mode. 2. Set the test mode when no batteries are overcharged. 3. The overcharge timer reset delay time (t TR) is not shortened in the test mode.

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.2.3_00 S-8215A Series Seiko Instruments Inc. 13  Timing Charts 1. Overcharge detection operation VCUn Battery voltage CO pin (Active "H") VHCn (n = 1 to 5) tCU tCU or shorter tTR or shorter tTR or longer CO pin (Active "L") 2.0 ms typ. Figure 11

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) S-8215A Series Rev.2.3_00 Seiko Instruments Inc. 14 2. Overcharge timer reset operation VCUn Battery voltage CO pin (Active "H") tCU VHCn tCU or shorter tTR tTR or shorter Timer reset tTR or shorter tTR or longer (n = 1 to 5) CO pin (Active "L") Figure 12

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.2.3_00 S-8215A Series Seiko Instruments Inc. 15  Battery Protection IC Connection Examples 1. 5-serial cell SC PROTECTOR EB− EB+ BAT1 BAT2 BAT3 BAT4 FET CVDD RVDD DP VC5 VC1 VC2 VC3 VC4 CO VDD S-8215A Series VSS BAT5 Figure 13 Table 8 Constants for External Components No. Part Min. Typ. Max. Unit 1 R1 to R5 0.5 1 10 kΩ 2 C1 to C5, C VDD 0.01 0.1 1 μF

3 R VDD 50 100 500 Ω

Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. R1 to R5 should be the same constant. C1 to C5 and C VDD should be the same constant. 4. Set R VDD, C1 to C5, and CVDD so that the condition (RVDD) × (C1 to C5, CVDD) ≥ 5 × 10−6 is satisfied. 5. Set R1 to R5, C1 to C5, and C VDD so that the condition (R1 to R5) × (C1 to C5, CVDD) ≥ 1 × 10−4 is satisfied. 6. Since the CO pin may become detection status transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff.

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) S-8215A Series Rev.2.3_00 Seiko Instruments Inc. 16 2. 4-serial cell SC PROTECTOR EB− EB+ BAT1 BAT2 BAT3 BAT4 FET CVDD RVDD DP VC5 VC1 VC2 VC3 VC4 CO VDD S-8215A Series VSS Figure 14 Table 9 Constants for External Components No. Part Min. Typ. Max. Unit 1 R1 to R4 0.5 1 10 kΩ 2 C1 to C4, C VDD 0.01 0.1 1 μF Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. R1 to R4 should be the same constant. C1 to C4 and C VDD should be the same constant. 4. Set R VDD, C1 to C4, and CVDD so that the condition (RVDD) × (C1 to C4, CVDD) ≥ 5 × 10−6 is satisfied. 5. Set R1 to R4, C1 to C4, and C VDD so that the condition (R1 to R4) × (C1 to C4, CVDD) ≥ 1 × 10−4 is satisfied. 6. Since the CO pin may become detection status transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff.

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.2.3_00 S-8215A Series Seiko Instruments Inc. 17 3. 3-serial cell SC PROTECTOR EB− EB+ BAT1 BAT2 BAT3 FET CVDD RVDD DP VC5 VC1 VC2 VC3 VC4 CO VDD S-8215A Series VSS Figure 15 Table 10 Constants for External Components No. Part Min. Typ. Max. Unit 1 R1 to R3 0.5 1 10 kΩ 2 C1 to C3, C VDD 0.01 0.1 1 μF Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. R1 to R3 should be the same constant. C1 to C3 and C VDD should be the same constant. 4. Set R VDD, C1 to C3, and CVDD so that the condition (RVDD) × (C1 to C3, CVDD) ≥ 5 × 10−6 is satisfied. 5. Set R1 to R3, C1 to C3, and C VDD so that the condition (R1 to R3) × (C1 to C3, CVDD) ≥ 1 × 10−4 is satisfied. 6. Since the CO pin may become detection status transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff.

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) S-8215A Series Rev.2.3_00 Seiko Instruments Inc. 18 [For SC PROTECTOR, contact] Device Sales Dept., Advanced Process Device Division, Dexerials Corporation Gate City Osaki East Tower 8F, 1-11-2 Osaki, Shinagawa-ku, Tokyo, 141-0032 Japan TEL +81-3-5435-3946 Contact Us: http://www.dexerials.jp/en/  Precautions

• Do not connect batteries charged with V CUn + VHCn or higher. If the connected batteries include a battery charged with VCUn + VHCn or higher, the S-8215A series may become overcharge status after all pins are connected.
• In some application circuits, even if an overcharged battery is not included, the order of connecting batteries may be restricted to prevent transient output of CO detection pulses when the batteries are connected. Perform thorough evaluation with the actual application circuit.
• Before the battery connection, shor t-circuit the battery side pins R VDD and R1, shown in the figure in "  Battery Protection IC Connection Examples".
• The application conditions for the inpu t voltage, output voltage, and load current should not exceed the package power dissipation.
• Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic protection circuit.
• SII claims no responsibility for any disputes arising out of or in connection with any infringement of patents owned by a third party by products including this IC.

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.2.3_00 S-8215A Series Seiko Instruments Inc. 19  Characteristics (Typical Data) 1. Detection voltage 1. 1 VCU vs. Ta VCU = 4.3 V 1. 2 VCU + VHC vs. Ta VHC = −0.3 V VCU [V] 4.400 4.350 4.300 4.250 4.200 40 25 25 50 75 85 Ta [C] VCU + VHC [V] 4.100 4.050 4.000 3.950 3.900 40 25 25 50 75 85 Ta [C] 2. Current consumption 2. 1 IOPE vs. Ta VDD = 16.5 V 2. 2 IOPED vs. Ta VDD = 11.5 V IOPE [μA] 4.0 3.0 2.0 1.0 0.0 40 25 25 50 75 85 Ta [C] IOPED [μA] 4.0 3.0 2.0 1.0 0.0 40 25 25 50 75 85 Ta [C] 2. 3 IOPE vs. VDD Ta = +25°C V DD [V] IOPE [μA] 01 0 51 5 2 0 2 5 3 0

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) S-8215A Series Rev.2.3_00 Seiko Instruments Inc. 20 3. Delay time 3. 1 tCU vs. Ta VDD = 19 V tCU [s] 6.0 5.0 4.0 3.0 2.0 40 25 25 50 75 85 Ta [C] 4. Output current 4. 1 ICOL vs. VDD Ta = +25°C 4. 2 ICOH vs. VDD Ta = +25°C 0.0 2.5 5.0 7.5 10.0 VDD [V] ICOL [mA] 01 0 51 5 2 0 2 5 3 0 250 500 750 1000 VDD [V] ICOH [μA] 01 0 51 5 2 0 2 5 3 0

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.2.3_00 S-8215A Series Seiko Instruments Inc. 21  Marking Specifications 1. TMSOP-8 Top view 1 4 3 2 85 6 7 (1) (2) (3) (4) (5) (6) (7) (8) (1): Blank (2) to (4): Product code (Refer to Product name vs. Product code) (5): Blank (6) to (8): Lot number Product name vs. Product code Product Name Product Code (2) (3) (4) S-8215AAA-K8T2U V 6 A S-8215AAB-K8T2U V 6 B S-8215AAC-K8T2U V 6 C S-8215AAD-K8T2U V 6 D S-8215AAE-K8T2U V 6 E S-8215AAF-K8T2U V 6 F S-8215AAH-K8T2U V 6 H S-8215AAI-K8T2U V 6 I S-8215AAJ-K8T2U V 6 J S-8215AAK-K8T2U V 6 K S-8215AAL-K8T2U V 6 L S-8215AAM-K8T2U V 6 M S-8215AAN-K8T2U V 6 N S-8215AAO-K8T2U V 6 O S-8215AAP-K8T2U V 6 P S-8215AAQ-K8T2U V 6 Q 2. SNT-8A Top view 14 3 2 85 6 7 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (1): Blank (2) to (4): Product code (Refer to Product name vs. Product code) (5), (6): Blank (7) to (11): Lot number Product name vs. Product code Product Name Product Code (2) (3) (4) S-8215AAA-I8T1U V 6 A S-8215AAG-I8T1U V 6 G

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