S8213

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www.sii-ic.com BATTERY PROTECTION IC FOR 2- SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) © Seiko Instruments Inc., 2012-2015 Rev.1.3_01 Seiko Instruments Inc. 1 The S-8213 Series is used for secondary protection of lithium-i on rechargeable batteries, and incorporates a high-accuracy voltage detection circuit and a delay circuit. Short-circuits between VC3 to VSS accommodate serial connection of two cells or three cells.  Features

• High-accuracy voltage detection circuit for each cell Overcharge detection voltage n (n = 1 to 3) 4.10 V to 4.50 V (in 50 mV steps) Accuracy: ±25 mV (Ta = +25°C) Accuracy: ±30 mV (Ta = 0°C to +60°C) Overcharge hysteresis voltage n (n = 1 to 3) 0 V ± 25 mV, −0.05 V ± 25 mV, −0.40 V ± 80 mV
• Delay times for overcharge detection can be set by an internal circuit only (external capacitors are unnecessary)
• Output form is selectable: CMOS output, Nch open-drain output
• Output logic is selectable : Active "H", Active "L"
• High withstand voltage devices: Absolute maximum rating 26 V
• Wide operation voltage range: 3.6 V to 24 V
• Wide operation temperature range: Ta = −40°C to +85°C
• Low current consumption At V CUn − 1.0 V for each cell: 2.0 μA max. (Ta = +25°C) At 2.0 V for each cell: 0.3 μ A max. (Ta = +25°C)
• Lead-free (Sn 100%), halogen-free *1 *1. Refer to "  Product Name Structure" for details.  Application
• Lithium-ion rechargeable battery pack (for secondary protection)  Packages
• SOT-23-6
• SNT-6A

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) S-8213 Series Rev.1.3_01 Seiko Instruments Inc. 2  Block Diagram 1. CMOS output product VSS VC3 VC2 CO VC1 VDD Overcharge detection com parator 1 Overcharge detection comparator 2 Overcharge detection comparator 3 Reference voltage 1 Reference voltage 2 Reference voltage 3 Oscillator Overcharge detection / release delay circuit Control logic Remark The diodes in the figure are parasitic diodes. Figure 1

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_01 S-8213 Series Seiko Instruments Inc. 3 2. Nch open-drain output product VSS VC3 VC2 CO VC1 VDD Overcharge detection com parator 1 Overcharge detection comparator 2 Overcharge detection comparator 3 Reference voltage 1 Reference voltage 2 Reference voltage 3 Oscillator Overcharge detection / release delay circuit Control logic Remark The diodes in the figure are parasitic diodes. Figure 2

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) S-8213 Series Rev.1.3_01 Seiko Instruments Inc. 4  Product Name Structure 1. Product name S-8213 xxx - xxxx U Package abbreviation and IC packing specifications*1 M6T1: SOT-23-6, Tape I6T1: SNT-6A, Tape Serial code*2 Sequentially set from AAA to AAZ Environmental code U: Lead-free (Sn 100%), halogen-free *1. Refer to the tape drawing. *2. Refer to "3. Product name list". 2. Packages Table 1 Package Drawing Codes Package Name Dimension Tape Reel Land SOT-23-6 MP006-A-P-SD MP006-A-C-SD MP006-A-R-SD − SNT-6A PG006-A-P-SD PG006-A-C- SD PG006-A-R-SD PG006-A-L-SD 3. Product name list 3. 1 SNT-6A Table 2 Product Name Overcharge Detection Voltage [VCU] Overcharge Hysteresis Voltage [VHC] Overcharge Detection Delay Time [tCU] Output Form Output Logic S-8213AAB-I6T1U 4.300 V −0.40 V 2.0 s CMOS output Active "H" S-8213AAC-I6T1U 4.350 V −0.40 V 2.0 s CMOS output Active "H" S-8213AAD-I6T1U 4.400 V −0.40 V 2.0 s CMOS output Active "H" S-8213AAE-I6T1U 4.450 V −0.40 V 2.0 s CMOS output Active "H" S-8213AAF-I6T1U 4.500 V −0.40 V 2.0 s CMOS output Active "H" S-8213AAG-I6T1U 4.300 V −0.40 V 4.0 s CMOS output Active "H" S-8213AAH-I6T1U 4.350 V −0.40 V 4.0 s CMOS output Active "H" S-8213AAI-I6T1U 4.400 V −0.40 V 4.0 s CMOS output Active "H" S-8213AAJ-I6T1U 4.450 V −0.40 V 4.0 s CMOS output Active "H" S-8213AAK-I6T1U 4.500 V −0.40 V 4.0 s CMOS output Active "H" S-8213AAL-I6T1U 4.300 V −0.40 V 8.0 s CMOS output Active "H" S-8213AAM-I6T1U 4.350 V −0.40 V 8.0 s CMOS output Active "H" S-8213AAN-I6T1U 4.400 V −0.40 V 8.0 s CMOS output Active "H" S-8213AAO-I6T1U 4.450 V −0.40 V 8.0 s CMOS output Active "H" S-8213AAP-I6T1U 4.500 V −0.40 V 8.0 s CMOS output Active "H" S-8213AAQ-I6T1U 4.150 V −0.05 V 2.0 s CMOS output Active "L" S-8213AAR-I6T1U 4.250 V −0.05 V 2.0 s CMOS output Active "L" S-8213AAS-I6T1U 4.150 V −0.05 V 2.0 s Nch open-drain output Active "H" S-8213AAT-I6T1U 4.250 V −0.05 V 2.0 s Nch open-drain output Active "H" Remark Please contact our sales department for the products with detection voltage value other than those specified above.

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_01 S-8213 Series Seiko Instruments Inc. 5  Pin Configurations 1. SOT-23-6 13 2 546 Top view Figure 3 Table 3 Pin No. Symbol Description

1 VSS Input pin for negative power supply,

connection pin for negative voltage of battery 3

2 VC3 Connection pin for negative voltage of battery 2,

connection pin for positive voltage of battery 3

3 VC2 Connection pin for negative voltage of battery 1,

connection pin for positive voltage of battery 2

4 VC1 Connection pin for positive voltage of battery 1

5 VDD Input pin for positive power supply

6 CO Connection pin of charge control FET gate

1. SNT-6A Top view Figure 4 Table 4 Pin No. Symbol Description

1 CO Connection pin of charge control FET gate

2 VDD Input pin for positive power supply

3 VC1 Connection pin for positive voltage of battery 1

4 VC2 Connection pin for negative voltage of battery 1,

connection pin for positive voltage of battery 2

5 VC3 Connection pin for negative voltage of battery 2,

connection pin for positive voltage of battery 3

6 VSS Input pin for negative power supply,

connection pin for negative voltage of battery 3

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) S-8213 Series Rev.1.3_01 Seiko Instruments Inc. 6  Absolute Maximum Ratings Table 5 (Ta = +25°C unless otherwise specified) Item Symbol Applied Pin Absolute Maximum Rating Unit Input voltage between VDD and VSS VDS VDD V SS − 0.3 to VSS + 26 V Input pin voltage VIN VC1, VC2, VC3 V SS − 0.3 to VDD + 0.3 V CO output pin voltage CMOS output product VCO CO VSS − 0.3 to VDD + 0.3 V Nch open-drain output product VSS − 0.3 to VSS + 26 V Power dissipation SOT-23-6 PD − 650*1 mW SNT-6A 400 *1 mW Operation ambient temperature Topr − −40 to +85 °C Storage temperature Tstg − −40 to +125 °C *1. When mounted on board [Mounted board] (1) Board size: 114.3 mm × 76.2 mm × t1.6 mm (2) Name: JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 0 50 100 150 800 Power Dissipation (PD) [mW] Ambient Temperature (Ta) [°C] SOT-23-6 400 600 200 SNT-6A Figure 5 Power Dissipation of Package (When Mounted on Board)

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_01 S-8213 Series Seiko Instruments Inc. 7  Electrical Characteristics Table 6 (Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit DETECTION VOLTAGE Overcharge detection voltage n (n = 1, 2, 3) VCUn − VCU − 0.025 VCU VCU + 0.025 V 1 Ta = 0°C to +60°C*1 VCU − 0.030 VCU VCU + 0.030 V 1 Overcharge hysteresis voltage n (n = 1, 2, 3) VHCn VHC = −0.40 V VHC − 0.080 VHC VHC + 0.080 V 1 VHC = 0 V, −0.05 V VHC − 0.025 VHC VHC + 0.025 V 1 INPUT VOLTAGE Operation voltage between VDD and VSS VDSOP − 3.6 − 24 V − INPUT CURRENT Current consumption during operation IOPE V1 = V2 = V3 = VCU − 1.0 V − − 2.0 μA 3 Current consumption during overdischarge IPDN V1 = V2 = V3 = 2.0 V − − 0.3 μA 3 VC1 pin current IVC1 V1 = V2 = V3 = VCU − 1.0 V − − 0.3 μA 4 VC2 pin, VC3 pin current IVC2, IVC3 V1 = V2 = V3 = VCU − 1.0 V −0.3 0 0.3 μA 4 OUTPUT CURRENT CO pin sink current ICOL − 0.4 − − mA 5 CO pin source current (CMOS output product) I COH − 20 − − μA 5 CO pin leakage current (Nch open-drain output product) ICOLL − − − 0.1 μA 5 DELAY TIME Overcharge detection delay time tCU − tCU × 0.8 tCU tCU × 1.2 s 1 Transition time to test mode tTST − − − 20 ms 2 *1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production.

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) S-8213 Series Rev.1.3_01 Seiko Instruments Inc. 8  Test Circuits 1. Overcharge detection voltage, overcharge hysteresis voltage (Test circuit 1) Set SW1 to OFF and ON in CMOS output product and Nch open-drain output product, respectively. 1. 1 Overcharge detection voltage n (VCUn) Set V1 = V2 = V3 = VCU − 0.05 V. The Overcharge detection voltage 1 (VCU1) is the V1 voltage when the CO pin’s output changes after the voltage of V1 has been gradually increased. Overcharge detection voltage VCUn (n = 2, 3) can be determined in the same way as when n = 1. 1. 2 Overcharge hysteresis voltage n (VHCn) Set V1 = VCU + 0.05 V, V2 = V3 = 2.5 V. The overcharge hysteresis voltage 1 (VHC1) is the difference between V1 voltage and VCU1 when the CO pin’s output changes after the V1 voltage has been gradually decreased. Overcharge hysteresis voltage VHCn (n = 2, 3) can be determined in the same way as when n = 1. 2. Output current (Test circuit 5) Set SW1 and SW2 to OFF. 2. 1 Active "H" 2. 1. 1 CO pin source current (ICOH) Set SW1 to ON after setting V1 = 5.0 V, V2 = V3 = 3.0 V, V4 = 0.5 V. I1 is the CO pin source current (ICOH) at that time. 2. 1. 2 CO pin sink current (ICOL) Set SW2 to ON after setting V1 to V3 = 3.5 V, V5 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 2. 1. 3 CO pin leakage current (ICOLL) Set SW2 to ON after setting V1 = 5.0 V, V2 = V3 = 3.0 V, V5 = 26 V. I2 is the CO pin leakage current (ICOLL) at that time. 2. 2 Active "L" 2. 2. 1 CO pin source current (ICOH) Set SW1 to ON after setting V1 to V3 = 3.5 V, V4 = 0.5 V. I1 is the CO pin source current (ICOH) at that time. 2. 2. 2 CO pin sink current (ICOL) Set SW2 to ON after setting V1 = 5.0 V, V2 = V3 = 3.0 V, V5 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 2. 2. 3 CO pin leakage current (ICOLL) Set SW2 to ON after setting V1 to V3 = 3.5 V, V5 = 26 V. I2 is the CO pin leakage current (ICOLL) at that time.

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_01 S-8213 Series Seiko Instruments Inc. 9 3. Overcharge detection delay time (tCU) (Test circuit 1) Set SW1 to OFF and ON in CMOS output product and Nch open-drain output product, respectively. Increase V1 up to 5.0 V after setting V1 = V2 = V3 = 3.5 V. The overcharge detection delay time (tCU) is the time period until the CO pin output changes. 4. Transition time to test mode (tTST) (Test circuit 2) Set SW1 to OFF and ON in CMOS output product and Nch open-drain output product, respectively. Increase V4 up to 4.0 V, and decrease V4 again to 0 V after setting V1 = V2 = V3 = 3.5 V, and V4 = 0 V. When the period from when V4 was raised to when it has fallen is short, if an overcharge detection operation is performed subsequently, the delay time is tCU. However, when the period from when V4 is raised to when it has fallen is gradually made longer, the delay time during the s ubsequent overcharge detection operation is shorter than t CU. The transition time to test mode (tTST) is the period from when V4 was raised to when it has fallen at that time.

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_01 S-8213 Series Seiko Instruments Inc. 11  Operation Remark Refer to " Battery Protection IC Connection Examples". 1. Normal status If the voltage of each of the batteries is lower than "the overcharge detection voltage (VCUn) + the overcharge hysteresis voltage (VHCn)", CO pin output changes to "L" (Active "H") or "H" (Active "L"). This is called normal status. 2. Overcharge status When the voltage of one of the batteries exceeds V CUn during charging under normal c onditions and the status is retained for the overcharge detection delay time (t CU) or longer, CO pin output chang es. This is called overcharge status. Connecting FET to the CO pin provides charge control and a second protection. If the voltage of each of the batteries is lower than VCUn + VHCn and the status is retained for 2.0 ms typ. or longer, the S-8213 Series changes to normal status.

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) S-8213 Series Rev.1.3_01 Seiko Instruments Inc. 12 3. Test mode The overcharge detection delay time (tCU) can be shortened by entering the test mode. The test mode can be set by retaining the VDD pin voltage 4.0 V or more higher than the VC1 pin voltage for 20 ms or longer. The status is retained by the internal latch and the test mode is retained even if the VDD pin voltage is decreased to the same voltage as that of the VC1 pin voltage. After that, the latch for retaining the test mode is reset and the S-8213 Series exits from test mode under the overcharge status. VCUn Pin voltage CO pin (Active "H") Test mode VDD pin voltage

4.0 V or

tTST = 20 ms max. VC1 pin voltage (n = 1 to 3) 32 ms typ. CO pin (Active "L") 2.0 ms typ. Figure 11

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_01 S-8213 Series Seiko Instruments Inc. 13  Timing Charts 1. Overcharge detection operation 1. 1 CMOS output product VCUn Battery voltage CO pin (Active "H") VHCn (n = 1 to 3) tCU tCU or shorter CO pin (Active "L") 2.0 ms typ. Figure 12

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) S-8213 Series Rev.1.3_01 Seiko Instruments Inc. 14 1. 2 Nch open-drain output product VCUn Battery voltage CO pin (Active "H") VHCn (n = 1 to 3) tCU tCU or shorter CO pin (Active "L") 2.0 ms typ. High-Z High-Z High-Z Figure 13

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_01 S-8213 Series Seiko Instruments Inc. 15  Battery Protection IC Connection Examples 1. 3-serial cell (CMOS output product) SC PROTECTOR EB− EB+ BAT1 BAT2 BAT3 FET CVDD RVDD DP VC1 VC2 VC3 VSS CO VDD S-8213 Series Figure 14 Table 7 Constants for External Components No. Part Min. Typ. Max. Unit 1 R1 to R3 0.2 1 2 kΩ 2 C1 to C3, C VDD 0.01 0.1 1 μF

3 R VDD 50 100 500 Ω

Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1 to R3 and to C1 to C3 and C VDD. 4. Set R VDD, C1 to C3, and CVDD so that the condition (RVDD) × (C1 to C3, CVDD) ≥ 5 × 10−6 is satisfied. 5. Set R1 to R3, C1 to C3, and C VDD so that the condition (R1 to R3) × (C1 to C3, CVDD) ≥ 1 × 10−4 is satisfied. 6. Since CO pin may become de tection status transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff.

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) S-8213 Series Rev.1.3_01 Seiko Instruments Inc. 16 2. 2-serial cell (CMOS output product) SC PROTECTOR EB− EB+ BAT1 BAT2 FET CVDD RVDD DP VC3 VC1 VC2 CO VDD S-8213 Series VSS Figure 15 Table 8 Constants for External Components No. Part Min. Typ. Max. Unit 1 R1, R2 0.2 1 2 kΩ 2 C1, C2, CVDD 0.01 0.1 1 μF Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1, R2 and to C1, C2 and C VDD. 4. Set R VDD, C1, C2, and CVDD so that the condition (RVDD) × (C1, C2, CVDD) ≥ 5 × 10−6 is satisfied. 5. Set R1, R2, C1, C2, and C VDD so that the condition (R1, R2) × (C1, C2, CVDD) ≥ 1 × 10−4 is satisfied. 6. Since CO pin may become de tection status transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff.

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_01 S-8213 Series Seiko Instruments Inc. 17 [For SC PROTECTOR, contact] Device Sales Dept., Advanced Process Device Division, Dexerials Corporation Gate City Osaki East Tower 8F, 1-11-2 Osaki, Shinagawa-ku, Tokyo, 141-0032 Japan TEL +81-3-5435-3946 Contact Us: http://www.dexerials.jp/en/  Precautions

• Do not connect batteries charged with V CUn + VHCn or higher. If the connected batteries include a battery charged with VCUn + VHCn or more, the S-8213 series may become overcharge status after all pins are connected.
• In some application circuits, even if an overcharged battery is not included, the order of connecting batteries may be restricted to prevent transient output of CO detection pulses when the batteries are connected. Perform thorough evaluation with the actual application circuit.
• Before the battery connection, shor t-circuit the battery side pins R VDD and R1, shown in the figure in "  Battery Protection IC Connection Examples".
• The application conditions for the inpu t voltage, output voltage, and load current should not exceed the package power dissipation.
• Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic protection circuit.
• SII claims no responsibility for any disputes arising out of or in connection with any infringement of patents owned by a third party by products including this IC.

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) S-8213 Series Rev.1.3_01 Seiko Instruments Inc. 18  Characteristics (Typical Data) 1. Detection voltage 1. 1 VCU vs. Ta VCU = 4.3 V 1. 2 VCU + VHC vs. Ta VHC = −0.4 V Ta [°C] 4.40 4.20 4.25 4.30 4.35 −40 0 25 50−25 85 75 VCU [V] Ta [°C] 4.00 3.80 3.85 3.90 3.95 −40 0 25 50−25 85 75 VCU + VHC [V] 2. Current consumption 2. 1 IOPE vs. Ta VDD = 9.9 V 2. 2 IPDN vs. Ta VDD = 6.0 V Ta [°C] 2.0 0.5 1.0 1.5 −40 0 25 50−25 85 75 IOPE [μA] Ta [°C] 0.3 −40 0 25 50−25 85 75 IPDN [μA] 0.2 0.1 2. 3 IOPE vs. VDD Ta = +25°C IOPE [μA] 0 305 1 01 52 02 5 VDD [V]

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_01 S-8213 Series Seiko Instruments Inc. 19 3. Delay time 3. 1 tCU vs. Ta VDD = 12 V Ta [°C] 3.0 1.0 1.5 2.0 2.5 −40 0 25 50−25 85 75 tCU [s] 4. Output current 4. 1 ICOL vs. VDD Ta = +25°C 4. 2 ICOH vs. VDD Ta = +25°C 2.0 ICOL [mA] 0 305 1 01 52 02 5 VDD [V] 0.5 1.0 1.5 100 ICOH [μA] 0 305 1 01 52 02 5 VDD [V] 4. 3 ICOLL vs. VDD Ta = +25°C 0.100 ICOLL [A] 0 305 1 01 52 02 5 VDD [V] 0.025 0.050 0.075

BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) S-8213 Series Rev.1.3_01 Seiko Instruments Inc. 20  Marking Specification 1. SNT-6A Top view 13 2 64 5 (1) (2) (3) (4) (5) (6) (1) to (3): Product code (Refer to Product name vs. Product code) (4) to (6): Lot number Product name vs. Product code Product Name Product Code (1) (2) (3) S-8213AAB-I6T1U S U B S-8213AAC-I6T1U S U C S-8213AAD-I6T1U S U D S-8213AAE-I6T1U S U E S-8213AAF-I6T1U S U F S-8213AAG-I6T1U S U G S-8213AAH-I6T1U S U H S-8213AAI-I6T1U S U I S-8213AAJ-I6T1U S U J S-8213AAK-I6T1U S U K S-8213AAL-I6T1U S U L S-8213AAM-I6T1U S U M S-8213AAN-I6T1U S U N S-8213AAO-I6T1U S U O S-8213AAP-I6T1U S U P S-8213AAQ-I6T1U S U Q S-8213AAR-I6T1U S U R S-8213AAS-I6T1U S U S S-8213AAT-I6T1U S U T

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