S8206A

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www.sii-ic.com BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) © Seiko Instruments Inc., 2015 Rev.1.1_00 Seiko Instruments Inc. 1 The S-8206A Series is used for secondary pr otection of lithium-ion / lithium polymer rechargeable batteries, and incorporates a high-accuracy voltage detection circuit and a delay circuit.  Features

• High-accuracy voltage detection circuit Overcharge detection voltage 3.50 V to 5.00 V (5 mV step) Accuracy ±20 mV Overcharge release voltage 3.10 V to 4.95 V*1 Accuracy ±50 mV
• Detection delay time is generated only by an internal circuit (external capacitors are unnecessary).
• Output logic is selectable: Active "H", active "L"
• Output form is selectable: CMOS output, Nch open-drain output
• Wide operation temperature range Ta = −40°C to +85°C
• Low current consumption During operation: 1.5 μA typ., 3.0 μA max. (Ta = +25°C)
• Lead-free (Sn 100%), halogen-free *1. Overcharge release voltage = Overcharge detection voltage − Overcharge hysteresis voltage (Overcharge hysteresis voltage can be selected from a range of 0.05 V to 0.4 V in 50 mV step.)  Applications
• Lithium-ion rechargeable battery pack
• Lithium polymer rechargeable battery pack  Packages
• SNT-6A
• HSNT-6 (1212)

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.1_00 Seiko Instruments Inc. 2  Block Diagram 1. CMOS output, active "H" VM VSS VDD CO DO Overcharge detection comparator Control logic Delay circuit Oscillator Figure 1

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) Rev.1.1_00 S-8206A Series Seiko Instruments Inc. 3 2. CMOS output, active "L" VM VSS VDD CO DO Control logic Delay circuit Oscillator Overcharge detection comparator Figure 2

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.1_00 Seiko Instruments Inc. 4 3. Nch open-drain output VM VSS VDD CO DOOvercharge detection comparator Control logic Delay circuit Oscillator Figure 3

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) Rev.1.1_00 S-8206A Series Seiko Instruments Inc. 5  Product Name Structure 1. Product name S-8206A xx - xxxx U Package abbreviation and IC packing specifications*1 I6T1: SNT-6A, Tape A6T2: HSNT-6 (1212), Tape Serial code*2 Sequentially set from AA to ZZ Environmental code U: Lead-free (Sn 100%), halogen-free *1. Refer to the tape drawing. *2. Refer to "3. Product name list". 2. Packages Table 1 Package Drawing Codes Package Name Dimension Tape Reel Land SNT-6A PG006-A-P-SD PG006-A-C-SD PG006-A-R-SD PG006-A-L-SD HSNT-6 (1212) PM006-A-P-SD PM006-A- C-SD PM006-A-R-SD PM006-A-L-SD

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.1_00 Seiko Instruments Inc. 6 3. Product name list 3. 1 SNT-6A Table 2 Product Name Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] Overcharge Detection Delay Time*1 [tCU] Output Logic*2 Output Form *3 S-8206AAA-I6T1U 4.500 V 4.150 V 2 s Active "H" CMOS output S-8206AAB-I6T1U 4.550 V 4.200 V 2 s Active "H" CMOS output S-8206AAC-I6T1U 4.150 V 4.000 V 2 s Active "L" CMOS output S-8206AAD-I6T1U 4.250 V 4.100 V 2 s Active "L" CMOS output S-8206AAE-I6T1U 4.150 V 4.000 V 2 s Active "H" Nch open-drain output S-8206AAF-I6T1U 4.250 V 4.100 V 2 s Active "H" Nch open-drain output *1. Overcharge detection delay time 1 s / 2 s / 4 s is selectable. *2. Output logic active "H" / active "L" is selectable. *3. Output form CMOS output / Nch open-drain output is selectable. Remark Please contact our sales office for the products with detection voltage value other than those specified above. 3. 2 HSNT-6 (1212) Table 3 Product Name Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] Overcharge Detection Delay Time*1 [tCU] Output Logic*2 Output Form *3 S-8206AAA-A6T2U 4.500 V 4.150 V 2 s Active "H" CMOS output S-8206AAB-A6T2U 4.550 V 4.200 V 2 s Active "H" CMOS output *1. Overcharge detection delay time 1 s / 2 s / 4 s is selectable. *2. Output logic active "H" / active "L" is selectable. *3. Output form CMOS output / Nch open-drain output is selectable. Remark Please contact our sales office for the products with detection voltage value other than those specified above.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) Rev.1.1_00 S-8206A Series Seiko Instruments Inc. 7  Pin Configurations 1. SNT-6A Top view Figure 4 Table 4 Pin No. Symbol Description

1 NC*1 No connection

2 CO Connection pin of charge control FET gate

(CMOS output)

3 DO Input pin for test signal

4 VSS Input pin for negative power supply

5 VDD Input pin for positive power supply

6 VM Negative power supply pin for CO pin

*1. The NC pin is electrically open. The NC pin can be connected to VDD pin or VSS pin. 2. HSNT-6 (1212) Top view Bottom view *1. Connect the heat sink of backside at shadowed area to the board, and set electric potential open or VDD. However, do not use it as the function of electrode. Figure 5 Table 5 Pin No. Symbol Description (CMOS output) *1. The NC pin is electrically open. The NC pin can be connected to VDD pin or VSS pin.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.1_00 Seiko Instruments Inc. 8  Absolute Maximum Ratings Table 6 (Ta = +25°C unless otherwise specified) Item Symbol Applied Pin Absolute Maximum Rating Unit Input voltage between VDD pin and VSS pin V DS VDD VSS − 0.3 to VSS + 6 V VM pin input voltage VVM VM V DD − 28 to VDD + 0.3 V DO pin input voltage VDO DO V SS − 0.3 to VDD + 0.3 V CO pin output voltage CMOS output VCO CO VVM − 0.3 to VDD + 0.3 V Nch open-drain output VVM − 0.3 to VVM + 28 V Power dissipation SNT-6A PD − 400*1 mW HSNT-6 (1212) − 480*1 mW Operation ambient temperature Topr − −40 to +85 °C Storage temperature Tstg − −55 to +125 °C *1. When mounted on board [Mounted board] (1) Board size: 114.3 mm × 76.2 mm × t1.6 mm (2) Board name: JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 0 50 100 150 400 200 Power Dissipation (PD) [mW] Ambient Temperature (Ta) [°C] 700 300 100 500 600 SNT-6A HSNT-6 (1212) Figure 6 Power Dissipation of Package (When Mounted on Board)

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) Rev.1.1_00 S-8206A Series Seiko Instruments Inc. 9  Electrical Characteristics 1. Ta = +25°C Table 7 (Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection Voltage Overcharge detection voltage VCU − V CU − 0.020 V CU V CU + 0.020 V 1 Ta = −10°C to +60°C*1 VCU − 0.025 V CU V CU + 0.025 V 1 Overcharge release voltage VCL VCL ≠ VCU V CL − 0.050 V CL V CL + 0.050 V 1 VCL = VCU V CL − 0.025 V CL V CL + 0.020 V 1 Input Voltage Operation voltage between VDD pin and VSS pin VDSOP − 1.5 − 6.0 V − Input Current Current consumption during operation IOPE V DD = 3.4 V, VVM = 0 V − 1.5 3.0 μA 2 Output Resistance CO pin resistance "H" 1 RCOH1 CMOS output 5 10 20 k Ω 3 CO pin resistance "L" 1 RCOL1 − 5 10 20 k Ω 3 DO pin resistance "H" RDOH − 5 10 20 k Ω 3 DO pin resistance "L" RDOL − 5 10 20 k Ω 3 CO pin resistance "H" 2 RCOH2 CMOS output, active "L" 1 4 − MΩ 3 CO pin resistance "L" 2 RCOL2 CMOS output, active "H" 1 4 − MΩ 3 Output Current CO pin leakage current "L" ICOLL Nch open-drain output − − 0.1 μA 3 Delay Time Overcharge detection delay time tCU − t CU × 0.7 tCU tCU × 1.3 − 4 *1. Since products are not screened at high and low temperature, the specif ication for this temperatur e range is guaranteed by design, not tested in production.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.1_00 Seiko Instruments Inc. 10  Test Circuits Caution 1. Unless otherwise specified, the output voltage levels "H" and "L" at CO pin (V CO) are judged by the threshold voltage (1.0 V) of the N-channel FET. Judge the CO pin level with respect to V VM. 2. Set SW to ON and OFF in Nch open-drain output and CMOS output, respectively. 1. Overcharge detection voltage, overcharge release voltage (Test circuit 1) 1. 1 Active "H" Overcharge detection voltage (VCU) is defined as the voltage V1 at which VCO goes from "L" to "H" when the voltage V1 is gradually increased from the starting condit ion of V1 = 3.4 V. Overcharge release voltage (V CL) is defined as the voltage V1 at which V CO goes from "H" to "L" when the voltage V1 is then gradually decreased. Overcharge hysteresis voltage (VHC) is defined as the difference between VCU and VCL. 1. 2 Active "L" Overcharge detection voltage (V CU) is defined as the voltage V1 at which V CO goes from "H" to "L" when the voltage V1 is gradually increased from the starting condition of V1 = 3.4 V. Overcharge release voltage (V CL) is defined as the voltage V1 at which V CO goes from "L" to "H" when the voltage V1 is then gradually decreased. Overcharge hysteresis voltage (VHC) is defined as the difference between VCU and VCL. 2. Current consumption during operation (Test circuit 2) The current consumption during operation (IOPE) is the current that flows through VDD pin (IDD) under the set condition of V1 = 3.4 V. 3. CO pin resistance "H" 1 (CMOS output) (Test circuit 3) 3. 1 Active "H" The CO pin resistance "H" 1 (RCOH1) is the resistance between VDD pin and CO pin under the set conditions of V1 = 5.1 V, V2 = 4.7 V. 3. 2 Active "L" The CO pin resistance "H" 1 (RCOH1) is the resistance between VDD pin and CO pin under the set conditions of V1 = 3.4 V, V2 = 3.0 V. 4. CO pin resistance "L" 1 (Test circuit 3) 4. 1 Active "H" The CO pin resistance "L" 1 (RCOL1) is the resistance between VM pin and CO pin under the set conditions of V1 = 3.4 V, V2 = 0.4 V. 4. 2 Active "L" The CO pin resistance "L" 1 (RCOL1) is the resistance between VM pin and CO pin under the set conditions of V1 = 5.1 V, V2 = 0.4 V. 5. DO pin resistance "H" (Test circuit 3) The DO pin resistance "H" (RDOH) is the resistance between VDD pin and DO pin under the set conditions of V1 = 3.4 V, V3 = 3.0 V.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) Rev.1.1_00 S-8206A Series Seiko Instruments Inc. 11 6. DO pin resistance "L" (Test circuit 3) The DO pin resistance "L" (RDOL) is the resistance between VSS pin and DO pin under the set conditions of V1 = 1.8 V, V3 = 0.4 V. 7. CO pin resistance "H" 2 (CMOS output, active "L") (Test circuit 3) The CO pin resistance "H" 2 (RCOH2) is the resistance between VDD pin and CO pin under the set conditions of V1 = 5.1 V, V2 = 0 V. 8. CO pin resistance "L" 2 (CMOS output, active "H") (Test circuit 3) The CO pin resistance "L" 2 (RCOL2) is the resistance between VM pin and CO pin under the set conditions of V1 = 5.1 V, V2 = 5.1 V. 9. CO pin leakage current "L" (Nch open-drain output) 9. 1 Active "H" The CO pin leakage current "L" (I COLL) is the current that flows through CO pin (I CO) under the set conditions of V1 = 5.1 V, V2 = 28 V. 9. 2 Active "L" The CO pin leakage current "L" (I COLL) is the current that flows through CO pin (I CO) under the set conditions of V1 = 3.4 V, V2 = 28 V. 10. Overcharge detection delay time (Test circuit 4) 10. 1 Active "H" The overcharge detection delay time (t CU) is the time needed for V CO to go to "H" just after the voltage V1 increases and exceeds VCU under the set condition of V1 = 3.4 V. 10. 2 Active "L" The overcharge detection delay time (t CU) is the time needed for V CO to go to "L" just after the voltage V1 increases and exceeds VCU under the set condition of V1 = 3.4 V.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) Rev.1.1_00 S-8206A Series Seiko Instruments Inc. 13  Operation Remark Refer to "  Battery Protection IC Connection Example". 1. Overcharge detection status The S-8206A Series monitors the voltage of the battery co nnected between VDD pin and VSS pin to detect overcharge. When the battery voltage exceeds th e overcharge detection voltage (V CU) during charging in the normal status and the condition continues for the overcharge detection delay time (t CU) or longer, the S-8206A Series outputs overcharge detection signal from the CO pin. This condition is called overcharge status. Connecting FET to the CO pin provides charge control and a second protection. 2. Test mode tCU can be shortened by forcibly setting the DO pin to VSS level from external. When the DO pin is forcibly set to VSS level from external, tCU will be shortened to approximately 1/64.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.1_00 Seiko Instruments Inc. 14  Timing Charts 1. Overcharge detection VCU VCL (VCU − VHC) Battery voltage VDD CO pin voltage CMOS output Active "H" VVM Status*1 (1) (2) (1) Overcharge detection delay time (tCU) VDD CO pin voltage CMOS output Active "L" VVM VDD CO pin voltage Nch open-drain output Active "H" VVM VDD CO pin voltage Nch open-drain output Active "L" VVM High-Z High-Z High-Z *1. (1): Normal status (2): Overcharge status Figure 11

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.1_00 Seiko Instruments Inc. 16 [For SC PROTECTOR, contact] Device Sales Dept., Advanced Process Device Division, Dexerials Corporation Gate City Osaki East Tower 8F, 1-11-2 Osaki, Shinagawa-ku, Tokyo, 141-0032 Japan TEL +81-3-5435-3946 Contact Us: http://www.dexerials.jp/en/  Precautions

• The application conditions for the input voltage, output voltage, and load current should not exceed the package power dissipation.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit.
• SII claims no responsibility for any and all disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) Rev.1.1_00 S-8206A Series Seiko Instruments Inc. 17  Characteristics (Typical Data) 1. Current consumption 1. 1 IOPE vs. Ta 4.0 IOPE [A] 40 85 75 50 25 025 Ta [C] 0.0 3.0 2.0 1.0 2. Detection voltage 2. 1 VCU vs. Ta 2. 2 VCL vs. Ta 4.53 VCU [V] 40 85 75 50 25 025 Ta [C] 4.45 4.51 4.49 4.47 4.21 VCL [V] 40 85 75 50 25 025 Ta [C] 4.07 4.09 4.19 4.15 4.17 4.11 4.13 3. Delay time 3. 1 tCU vs. Ta 5.0 tCU [s] 40 85 75 50 25 025 Ta [C] 1.0 4.0 3.0 2.0

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) S-8206A Series Rev.1.1_00 Seiko Instruments Inc. 18 4. Output resistance 4. 1 RCOH1 vs. VCO 4. 2 RCOL1 vs. VCO RCOH1 [k] VCO [V] 321 RCOL1 [k] VCO [V] 321 4. 3 RDOH vs. VDO 4. 4 RDOL vs. VDO RDOH [k] VDO [V] 321 RDOL [k] VDO [V] 321

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION) Rev.1.1_00 S-8206A Series Seiko Instruments Inc. 19  Marking Specifications 1. SNT-6A Top view 13 2 64 5 (1) (2) (3) (4) (5) (6) (1) to (3): Product code (refer to Product name vs. Product code) (4) to (6): Lot number Product name vs. Product code Product Name Product Code (1) (2) (3) S-8206AAA-I6T1U J N A S-8206AAB-I6T1U J N B S-8206AAC-I6T1U J N C S-8206AAD-I6T1U J N D S-8206AAE-I6T1U J N E S-8206AAF-I6T1U J N F 2. HSNT-6 (1212) 13 2 465 Top view (1) (2) (3) (4) (5) (1) to (3): Product code (refer to Product name vs. Product code) (4), (5): Lot number Product name vs. Product code Product Name Product Code (1) (2) (3) S-8206AAA-A6T2U J N A S-8206AAB-A6T2U J N B

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