S8203A

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www.sii-ic.com BATTERY PROTECTION IC FOR 3-SERIES CELL PACK © SII Semiconductor Corporation, 2016 Rev.1.0_00 The S-8203A Series includes high-accuracy voltage detection circuits and delay circuits, in single use, makes it possible for users to monitor the status of 3-series cell lithium-ion rechargeable battery. The S-8203A Series is suitable for protecting lithium-ion rechargeable battery pack from overcharge, overdischarge, and overcurrent.  Features

• High-accuracy voltage detection function for each cell Overcharge detection voltage n (n = 1 to 3) 3.55 V to 4.50 V *1 (50 mV step) Accuracy ±25 mV Overcharge release voltage n (n = 1 to 3) 3.30 V to 4.50 V *2 Accuracy ±50 mV Overdischarge detection voltage n (n = 1 to 3) 2.0 V to 3.2 V *1 (100 mV step) Accuracy ±80 mV Overdischarge release voltage n (n = 1 to 3) 2.0 V to 3.4 V *3 Accuracy ±100 mV
• Discharge overcurrent detection in 2-step Discharge overcurrent detection voltage 0.05 V to 0.30 V *4 (50 mV step) Accuracy ±15 mV Short-circuiting detection voltage 0.50 V to 1.0 V *4 (100 mV step) Accuracy ±100 mV
• Charge overcurrent detection function Charge overcurrent detection voltage −0.30 V to −0.05 V (50 mV step) Accuracy ±30 mV
• Settable by external capacitor; overcharge detection delay time, overdischarge detection delay time, discharge overcurrent detection delay time, charge overcurrent detection delay time (Load short-circuiting detection delay time is internally fixed.)
• Independent charge and discharge control by the control pins
• Power-down function is selectable: Available, unavailable
• High-withstand voltage: Absolute maximum rating 28 V
• Wide operation voltage range: 2 V to 24 V
• Wide operation temperature range: Ta = −40°C to +85°C
• Low current consumption During operation: 40 μA max. (Ta = +25°C) During power-down: 0.1 μA max. (Ta = +25°C)
• Lead-free (Sn 100%), halogen-free *1. The overcharge detection voltage n (n = 1 to 3) and overdischarge detection volt age (n = 1 to 3) cannot be selected if the voltage difference between them is 0.6 V or lower. *2. Overcharge hysteresis voltage n (n = 1 to 3) can be selected as 0 V or from a range of 0.1 V to 0.4 V in 50 mV step. (Overcharge hysteresis voltage = Overcharge detection voltage − Overcharge release voltage) *3. Overdischarge hysteresis voltage n (n = 1 to 3) can be se lected as 0 V or from a range of 0.2 V to 0.7 V in 100 mV step. (Overdischarge hysteresis voltage = Overdischarge release voltage − Overdischarge detection voltage) *4. The discharge overcurrent detection voltage and load short-circuiting detecti on voltage cannot be selected if the voltage difference between them is 0.3 V or lower.  Application
• Rechargeable lithium-ion battery pack  Package
• 16-Pin TSSOP

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK S-8203A Series Rev.1.0_00  Block Diagram VM DO VINI Discharge overcurrent CTLC CTLD CCT RVMD RVMS VDD VC1 VC2 VC3 VC4 Overcharge 1 Overdisacharge 1 Overcharge 2 Overdisacharge 2 Overcharge 3 Overdisacharge 3 Delay circuit Delay circuit Delay circuit Delay circuit Load short-circuiting Charge overcurrent CDT CO Delay circuit VSS CIT RCTLC RCTLD Control circuit NPI Remark Diodes in the figure are parasitic diodes. Figure 1

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK Rev.1.0_00 S-8203A Series  Product Name Structure 1. Product name S-8203A xx - TCT1 U Package abbreviation and IC packing specifications*1 TCT1: 16-Pin TSSOP, Tape Serial code*2 Sequentially set from AA to ZZ Environmental code U: Lead-free (Sn 100%), halogen-free *1. Refer to the tape drawing. *2. Refer to "3. Product name list". 2. Package Table 1 Package Drawing Code Package Name Dimension Tape Reel 16-Pin TSSOP FT016-A-P-SD FT016-A-C-SD FT016-A-R-S1

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK S-8203A Series Rev.1.0_00 3. Product name list Table 2 Product Name Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] Overdischarge Detection Voltage [VDL] Overdischarge Release Voltage [VDU] Discharge Overcurrent Detection Voltage [VDIOV] Load Short- circuiting Detection Voltage [VSHORT] Charge Overcurrent Detection Voltage [VCIOV] 0 V Battery Charge Function Power- down Function Delay Time*1 *1. The delay time is set by the external capacitor. But the discharge overcurrent release delay time (t DIOVR) and charge overcurrent release delay time (t CIOVR) are calculated by discharge overcurrent detection delay time (t DIOV) and charge overcurrent detection delay time (t CIOV) as the following equations. 1 [ms] (typ.) is the internal delay time of the S-8203A Series. (1) tDIOVR = tDIOV × 10 + 1 [ms] (typ.), tCIOVR = tCIOV × 10 + 1 [ms] (typ.) (2) tDIOVR = tDIOV × 0.05 + 1 [ms] (typ.), tCIOVR = tCIOV × 0.05 + 1 [ms] (typ.) Moreover, refer to "7. Delay time setting" in " Operation" for calculational methods of delay times. Remark Please contact our sales office for products with detection voltage values other than those specified above.

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK Rev.1.0_00 S-8203A Series  Pin Configuration Figure 2 Table 3 Pin No. Symbol Description

1 VM Voltage detec tion pin between VSS pin and VM pin

2 CO FET gate connection pin for charge control (Pch open-drain output)

Pin for voltage detection between VSS pin and CO pin

3 DO FET gate connection pin for discharge control (CMOS output)

4 VINI Voltage detec tion pin between VSS pin and VINI pin

5 CTLC Control pin for charge FET

6 CTLD Control pin for discharge FET

7 CCT Capacitor connection pin for delay for overcharge detection voltage

8 CDT Capacitor connection pin for delay for overdischarge detection voltage

9 CIT Capacitor connection pin for delay for discharge overcurrent detection,

charge overcurrent detection

10 VSS Input pin for negative power supply*1

11 NPI Input pin for negative power supply*1

12 VC4 Connection pin for battery 3's negative voltage

Input pin for negative power supply

13 VC3 Connection pin for battery 2's negative voltage

Connection pin for battery 3's positive voltage

14 VC2 Connection pin for battery 1's negative voltage

Connection pin for battery 2's positive voltage

15 VC1 Connection pin for battery 1's positive voltage

16 VDD Input pin for positive power supply

Connection pin for battery 1's positive voltage *1. Be sure to short the VSS pin and the NPI pin when using them.

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK S-8203A Series Rev.1.0_00  Absolute Maximum Ratings Table 4 (Ta = +25°C unless otherwise specified) Item Symbol Applied Pin Abso lute Maximum Rating Unit Input voltage between VDD pin and VSS pin VDS VDD VSS − 0.3 to VSS + 28 V Input pin voltage 1 VIN1 VC1, VC2, VC3, VC4, NPI, CTLC, CTLD, CCT, CDT, CIT V SS − 0.3 to VDD + 0.3 V Input pin voltage 2 VIN2 VM, VINI VDD − 28 to VDD + 0.3 V DO pin output voltage VDO DO VSS − 0.3 to VDD + 0.3 V CO pin input and output voltage V CO CO VDD − 28 to VDD + 0.3 V Power dissipation PD − 1100*1 mW Operation ambient temperature T opr − −40 to +85 °C Storage temperature Tstg − −40 to +125 °C *1. When mounted on board [Mounted board] (1) Board size: 114.3 mm × 76.2 mm × t1.6 mm (2) Board name: JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 0 50 100 150 800 400 Power Dissipation (PD) [mW] Ambient Temperature (Ta) [°C] 1000 600 200 1200 Figure 3 Power Dissipation of Package (When Mounted on Board)

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK Rev.1.0_00 S-8203A Series  Electrical Characteristics Table 5 (1 / 2) (Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection Voltage Overcharge detection voltage n (n = 1, 2, 3) VCUn V1 = V2 = V3 = V CU − 0.05 V VCU − 0.025 VCU VCU + 0.025 V 2 Overcharge release voltage n (n = 1, 2, 3) V CLn − VCL − 0.05 VCL VCL + 0.05 V 2 Overdischarge detection voltage n (n = 1, 2, 3) V DLn − VDL − 0.08 VDL VDL + 0.08 V 2 Overdischarge release voltage n (n = 1, 2, 3) V DUn − VDU − 0.10 VDU VDU + 0.10 V 2 Discharge overcurrent detection voltage V DIOV − VDIOV − 0.015 VDIOV VDIOV + 0.015 V 2 Load short-circuiting detection voltage V SHORT − VSHORT − 0.10 VSHORT VSHORT + 0.10 V 2 Charge overcurrent detection voltage V CIOV − VCIOV − 0.03 VCIOV VCIOV + 0.03 V 2 Temperature coefficient 1*1 TCOE1 Ta = 0°C to +50°C*3 −1.0 0 1.0 mV/°C − Temperature coefficient 2*2 TCOE2 Ta = 0°C to +50°C*3 −0.5 0 0.5 mV/°C − Delay Time Function*4 CDT pin internal resistance RCDT V1 = 1.5 V, V2 = V3 = 3.5 V 615 831 1020 kΩ 3 CIT pin internal resistance RCIT − 123 166 204 kΩ 3 CCT pin detection voltage VCCT V1 = 4.5 V, V2 = V3 = 3.5 V VDS × 0.68 VDS × 0.70 VDS × 0.72 V 3 CDT pin detection voltage VCDT V1 = 1.5 V, V2 = V3 = 3.5 V VDS × 0.68 VDS × 0.70 VDS × 0.72 V 3 CIT pin detection voltage VCIT V6 = VDIOV + 0.015 V VDS × 0.68 VDS × 0.70 VDS × 0.72 V 3 Load short-circuiting detection delay time t SHORT − 100 300 600 μs 2 CTLC pin response time tCTLC − − − 2.5 ms 2 CTLD pin response time tCTLD − − − 2.5 ms 2

0 V Battery Charge Function

0 V battery charge starting charger

"available" V1 = V2 = V3 = 0 V − 0.8 1.5 V 4

0 V battery charge inhibition battery

voltage V0INH 0 V battery charge function "unavailable" 0.4 0.7 1.1 V 2 Internal Resistance CTLC pin internal resistance R CTLC − 7 10 13 M Ω 5 CTLD pin internal resistance R CTLD − 7 10 13 M Ω 5 Resistance between VM pin and VDD pin *5 RVMD V1 = V2 = V3 = 1.8 V 450 900 1800 k Ω 5 Resistance between VM pin and VSS pin RVMS − 250 500 750 k Ω 5

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK S-8203A Series Rev.1.0_00 Table 5 (2 / 2) (Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Input Voltage Operation voltage between VDD pin and VSS pin *6 VDSOP Fixed output voltage of DO pin and CO pin 2 − 24 V − CTLC pin change voltage*6 VCTLC − 2.1 3.0 4.0 V 2 CTLD pin change voltage*6 VCTLD − 2.1 3.0 4.0 V 2 Input Current Current consumption during operation I OPE − − 20 40 μA 1 Current consumption during power-down*5 IPDN V1 = V2 = V3 = 1.5 V − − 0.1 μA 1 VC1 pin current IVC1 − 0 0.8 2.0 μA 5 VC2 pin current IVC2 − −0.3 0 0.3 μA 5 VC3 pin current IVC3 − −0.3 0 0.3 μA 5 VC4 pin current IVC4 − −2.0 −0.8 0 μA 5 Output Current CO pin source current ICOH V13 = 0.5 V 10 − − μA 5 CO pin leakage current ICOL V1 = V2 = V3 = 8 V − − 0.1 μA 5 DO pin source current IDOH V14 = 0.5 V 10 − − μA 5 DO pin sink current IDOL V15 = 0.5 V − − −10 μA 5 *1. Voltage temperature coefficient 1: Overcharge detection voltage *2. Voltage temperature coefficient 2: Discharge overcurrent detection voltage *3. Since products are not screened at high and low temperature, the specification for th is temperature range is guaranteed by design, not tested in production. *4. Refer to "  Operation" for details of delay time function. *5. For products with power-down function *6. The S-8203A Series does not operate detection if t he operation voltage between VDD pin and VSS pin (V DSOP) is CTLC pin change voltage (VCTLC) or CTLD pin change voltage (VCTLD) or lower.

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK Rev.1.0_00 S-8203A Series  Test Circuits 1. Current consumption during operation, current consumption during power-down (Test circuit 1) Set S1 and S2 to OFF. 1. 1 Current consumption during operation (IOPE) Set V1 = V2 = V3 = 3.5 V, S2 to ON. ISS is the current consumption during operation (IOPE) at that time. 1. 2 Current consumption during power-down (IPDN) (With power-down function) Set V1 = V2 = V3 = 1.5 V, S1 to ON. ISS is the current consumption during power-down (IPDN) at that time. 2. Overcharge detection voltage, overcharge release voltage, overdischarge detection voltage, overdischarge release voltage, discharge overcurrent detection voltage, load short-circuiting detection voltage, charge overcurrent detection voltage, CTLC pin change voltage, CTLD pin change voltage, load short-circuiting detectio n delay time, CTLC pin response time, CTLD pin response time (Test circuit 2) Set S3 to OFF. Confirm both VCO and VDO are in "H" (the voltage level is VDS × 0.9 V or higher) after setting V1 = V2 = V3 = 3.5 V, V6 = V7 = V8 = 0 V (this status is referred to as initial status 1). 2. 1 Overcharge detection voltage (VCU1), Overcharge release voltage (VCL1) The overcharge detection voltage (VCU1) is V1 when the VCO is set to "L" (the voltage level is VDS × 0.1 V or lower) after increasing V1 gradually after setting V1 = V2 = V3 = V CU − 0.05 V from the initial status 1. After that, decreasing V1 gradually, V1 is the overcharge release voltage (V CL1) when the VCO is set to "H" after setting V2 = V3 = 3.5 V. 2. 2 Overdischarge detection voltage (VDL1), overdischarge release voltage (VDU1) The overdischarge detection voltage (VDL1) is V1 when the VDO is set to "L" after decreasing V1 gradually from the initial status 1. After that, increasing V1 gradually, V1 is the overdischarge release voltage (VDU1) when VDO is set to "H". By changing Vn (n = 2 to 3), users can define the overcharge detection voltage (V CUn), the overcharge release voltage (VCLn), the overdischarge detection voltage (V DLn), the overdischarge release voltage (V DUn) as well when n = 1. 2. 3 Discharge overcurrent detection voltage (VDIOV) The discharge overcurrent detection voltage (VDIOV) is V6 when VDO is set to "L" after increasing V6 gradually from the initial status 1. 2. 4 Load short-circuiting detection voltage (VSHORT) The load short-circuiting detection voltage (VSHORT) is V6 when VDO is set to "L" after increasing V6 gradually after setting S3 to ON from the initial status 1. 2. 5 Charge overcurrent detection voltage (VCIOV) The charge overcurrent detection voltage (V CIOV) is V6 when V CO is set to "L" after decr easing V6 gradually from the initial status 1. 2. 6 CTLC pin change voltage (VCTLC) The CTLC pin change voltage (V CTLC) is V7 when V CO is set to "L" after increasing V7 gradually from the initial status 1. 2. 7 CTLD pin change voltage (VCTLD) The CTLD pin change voltage (V CTLD) is V8 when V DO is set to "L" after increasing V8 gradually from the initial status 1. 2. 8 Load short-circuiting detection delay time (tSHORT) Load short-circuiting detection delay time (t SHORT) is a period in which V DO changes to "L" after changing V6 to 1.5 V instantaneously, after setting S3 to ON from the initial status 1.

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK S-8203A Series Rev.1.0_00 2. 9 CTLC pin response time (tCTLC) CTLC pin response time (t CTLC) is a period in which V CO changes to "L" after changing V7 = V DS instantaneously from the initial status 1. 2. 10 CTLD pin response time (tCTLD) CTLD pin response time (t CTLD) is a period in which V DO changes to "L" after changing V8 = V DS instantaneously from the initial status 1. 3. CCT pin internal resistance, CDT pin internal resistance, CIT pin internal resistance, CCT pin detection voltage, CDT pin detection voltage, CIT pin detection voltage (Test circuit 3) Confirm both VCO and VDO are in "H" after setting V1 = V2 = V3 = 3.5 V, V6 = V9 = V10 = V11 = 0 V (this status is referred to as initial status 2). 3. 1 CCT pin internal resistance (RCCT) The CCT pin internal resistance (R CCT) can be defined by R CCT = VDS / ICCT by using ICCT when setting V1 = 4.5 V from the initial status 2. 3. 2 CDT pin internal resistance (RCDT) The CDT pin internal resistance (R CDT) can be defined by R CDT = VDS / ICDT by using ICDT when setting V1 = 1.5 V from the initial status 2. 3. 3 CIT pin internal resistance (RCIT) The CIT pin internal resistance (R CIT) can be defined by R CIT = V DS / ICIT by using I CIT when setting V6 = V DIOV + 0.015 V from the initial status 2. 3. 4 CCT pin detection voltage (VCCT) The CCT pin detection voltage (VCCT) is V9 when VCO is set to "L" after increasing V9 gradually, after setting V1 = 4.5 V from the initial status 2. 3. 5 CDT pin detection voltage (VCDT) The CDT pin detection voltage (VCDT) is V10 when VDO is set to "L" after increasing V10 gradually, after setting V1 = 1.5 V from the initial status 2. 3. 6 CIT pin detection voltage (VCIT) The CIT pin detection voltage (VCIT) is V11 when VDO is set to "L" after increasing V11 gradually, after setting V6 = VDIOV + 0.015 V from the initial status 2.

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK Rev.1.0_00 S-8203A Series 4. 0 V battery charge starting charger voltage (0 V battery charge function "available") (Test circuit 4), 0 V battery charge inhibition battery voltage (0 V battery charge function "unavailable") (Test circuit 2) 4. 1 0 V battery charge starting charger voltage (V0CHA) (0 V battery charge function "available") The 0 V battery charge starting charger voltage (V 0CHA) is V12 when V CO is 0.1 V or higher after increasing V12 gradually after setting V1 = V2 = V3 = 0 V, V12 = 0 V. 4. 2 0 V Battery charge inhibition battery voltage (V0INH) (0 V battery charge function "unavailable") The 0 V battery charge inhibition battery voltage (V 0INH) is V1 when V CO is set to "L" after decreasing V1 gradually from the initial status 1. 5. CTLC pin internal resistance, CTLD pin inte rnal resistance, resistance between VM pin and VDD pin, resistance between VM pin and VSS pi n, VC1 pin current, VC2 pin current, VC3 pin current, VC4 pin current, CO pin source current, CO pin leakage current, DO pin source current, DO pin sink current (Test circuit 5) Set S1, S5, S6 and S7 to OFF, set S2 and S4 to ON. Set V1 = V2 = V3 = 3.5 V, V6 = V13 = V14 = V15 = V16 = 0 V (this status is referred to as initial status 3). 5. 1 CTLC pin internal resistance (RCTLC) In the initial status 3, the CTLC pin internal resistance (RCTLC) can be defined by RCTLC = VDS / ICTLC by using ICTLC. 5. 2 CTLD pin internal resistance (RCTLD) In the initial status 3, the CTLD pin internal resistance (RCTLD) can be defined by RCTLD = VDS / ICTLD by using ICTLD. 5. 3 Resistance between VM pin and VDD pin (RVMD) (With power-down function) The resistance between VM pin and VDD pin (RVMD) can be defined by RVMD = VDS / IVM by using IVM when setting V1 = V2 = V3 = 1.8 V from the initial status 3. 5. 4 Resistance between VM pin and VSS pin (RVMS) The resistance between VM pin and VSS pin (R VMS) can be defined by RVMS = VDS / IVM by using IVM when setting V6 = 1.5 V, S2 to OFF, S1 to ON from the initial status 3. 5. 5 VC1 pin current (IVC1), VC2 pin current (IVC2), VC3 pin current (IVC3), VC4 pin current (IVC4) In the initial status 3, I1 is the VC1 pin current (IVC1), I2 is the VC2 pin current (IVC2), I3 is the VC3 pin current (IVC3), I4 is the VC4 pin current (IVC4). 5. 6 CO pin source current (ICOH), CO pin leakage current (ICOL) The CO pin source current (I COH) is I CO when setting V13 = 0.5 V from the init ial status 3. After that, the CO pin leakage current (ICOL) is ICO when setting V1 = V2 = V3 = 8 V, S4 to OFF, S5 to ON. 5. 7 DO pin source current (IDOH), DO pin sink current (IDOL) The DO pin source current (IDOH) is IDO when setting V14 = 0.5 V, S6 to ON from the initial status 3. After that, the DO pin sink current (IDOL) is IDO when setting V1 = V2 = V3 = 1.8 V, V15 = 0.5 V, S6 to OFF, S7 to ON.

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK S-8203A Series Rev.1.0_00 C1 = 0.1 μF 1 VM 2 CO 3 DO

4 VINI

5 CTLC

6 CTLD

7 CCT

C1 = 0.1 μF 1V M 2C O 3D O 4V I N I 5C T L C 6C T L D 7C C T VC2 VC3 VC4 NPI VSS VDD VC1 CIT 9 S-8203A Series CDT V V R1 = 1 MΩ V8 S3 VDO VCO Figure 4 Test Circuit 1 Figure 5 Test Circuit 2 C1 = 0.1 μF 1V M 2C O 3D O A A A R1 = 1 MΩ V V VCO VDO V10 V11 ICIT ICDT ICCT C1 = 0.1 μF 1V M 2C O 3D O 4V I N I 5C T L C 6C T L D R1 = 1 MΩ VVCO V12 Figure 6 Test Circuit 3 Figure 7 Test Circuit 4 S-8203A Series C1 = 0.1 μF 1V M 2C O 3D O A A A A A A A A A IVM ICO IDO ICTLC ICTLD V13 V14 V15 Figure 8 Test Circuit 5

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK Rev.1.0_00 S-8203A Series  Operation Remark Refer to " Connection Examples of Battery Protection IC". 1. Normal status In the S-8203A Series, when the voltage of each of the batteries is in the range from overdischarge detection voltage (VDLn) to overcharge detection voltage (V CUn), and the VINI pin voltage is in the range from charge overcurrent detection voltage (V CIOV) to discharge overcurrent detection voltage (V DIOV), both of CO pin a nd DO pin get the V DD level. This is the normal status. At this time, the charge and discharge FETs are on. 2. Overcharge status In the S-8203A Series, when the voltage of one of the batteries increases to the level of higher than V CUn, the CO pin is set in high impedance. This is the overcharge status. The CO pin is pulled down to EB − by an external resistor so that the charge FET is turned off and it stops charging. The overcharge status is released if either condition mentioned below is satisfied; (1) In case that the CO pin voltage is 1 / 50 × VDS or lower, and the voltage of each of the batteries which are VCUn or higher is in the level of overcharge release voltage (VCLn) or lower. (2) In case that the CO pin voltage is 1 / 50 × VDS or higher, and the voltage of each of the batteries is in the level of VCUn or lower. 3. Overdischarge status In The S-8203A Series, when the voltage of one of the batteries decreases to the level of V DLn or lower, the DO pin voltage gets the VSS level. This is the overdischarge status. The discharge FET is turned off and it stops discharging. The overdischarge status is released if either condition mentioned below is satisfied; (1) In case that the VM pin voltage is in the level of lower than V SS, and the voltage of each of the batteries is in the level of VDLn or higher. (2) In case that the VM pin voltage is V DS / 5 (typ.) or lower and the VM pin voltage is in the level of higher than VSS, and the voltage of each of the batteries which are V DLn or lower is in the level of overdischarge release voltage (VDUn) or higher. 3. 1 With power-down function In The S-8203A Series, when it reaches the overdi scharge status, the VM pin is pulled up to the V DD level by a resistor between VM pin and VDD pin (RVMD). If the VM pin voltage and the CO pin voltage increase to the level of VDS / 5 (typ.) or higher, respectively, the power-down func tion starts to operate and almost every circuit in the S-8205A/B Series stops working. The power-down function is released if either condition mentioned below is satisfied; (1) The VM pin voltage gets V DS / 5 (typ.) or lower. (2) The CO pin voltage gets V DS / 5 (typ.) or lower. 4. Discharge overcurrent status The discharging current increases to a certain value or higher . As a result, if the status in which the VINI pin voltage increases to the level of V DIOV or higher, the DO pin gets the V SS level. This is the disc harge overcurrent status. The discharge control FET is turned off and it stops discharging. In the status of discharge ov ercurrent, the CO pin is set in high impedance. The VM pin is pulled down to the VSS level by a resistor between VM pin and VSS pin (RVMS). The S-8203A Series has two levels for discharge overcurrent detection (V DIOV, VSHORT). The S-8203A Series' actions against load short-circuiting detection voltage (VSHORT) are as well in VDIOV. The discharge overcurrent status is released if the following condition is satisfied. (1) The VM pin voltage gets V DS / 10 (typ.) or lower.

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK S-8203A Series Rev.1.0_00 5. Charge overcurrent status In the S-8203A Series, the charge current increases to a certain value or higher. As a result, if the status in which the VINI pin voltage decreas es to the level of V CIOV or lower, the CO pin is set in high impedance. This is the charge overcurrent status. The charge control FET is turned off and it stops chargi ng. In this charge overcurrent status, DO pin gets the VSS level. The VM pin is pulled up to the VDD level by resistance between VM pin and VDD pin (RVMD). The charge overcurrent status is released if the following condition is satisfied. (1) The CO pin voltage gets 1 / 50 × VDS (typ.) or higher. 6. 0 V Battery charge function In the S-8203A Series, regarding how to charge a discharged battery (0 V battery), users are able to select either function mentioned below. (1) Enable to charge a 0 V battery A 0 V battery is charged when charger voltage is hi gher than 0 V battery char ge starting charger voltage (V0CHA). (2) Inhibit charging a 0 V battery A 0 V battery is not charged when the voltage of one of the batteries is 0 V battery charge inhibition battery voltage (V0INH) or lower. Caution When the VDD pin voltage is lower than the minimum value of operation voltage between VDD pin and VSS pin (VDSOP), the S-8203A Series' action is not assured. 7. Delay time setting In the S-8203A Series, users are able to se t delay time for the period; from detecting the voltage of one of the batteries or detecting changes in the voltage at the VINI pin, to the output to the CO pin, DO pin. Each delay time is determined by a resistor in the IC and an external capacitor. In the overchage detection, when the voltage of one of the batteries gets V CUn or higher, the S-8203A Series starts charging to the CCT pin's capacitor (CCCT) via the CCT pin's internal resistor (RCCT). After a certain period, the CO pin is set in high impedance if the voltage at the CCT pin reaches the CCT pin detection voltage (V CCT). This period is overcharge detection delay time (tCU). tCU is calculated using the following equation (VDS = V1 + V2 + V3). tCU [s] = −ln ( 1 − VCCT / VDS ) × CCCT [μF] × RCCT [MΩ] = −ln ( 1 − 0.7 (typ.)) × CCCT [μF] × 8.31 [MΩ] (typ.) = 10.0 [MΩ ] (typ.) × CCCT [μF] Overdischarge detection delay time (t DL), discharge overcurrent detection delay time (t DIOV), charge overcurrent detection delay time (tCIOV) are calculated using the following equations as well. tDL [ms] = −ln ( 1 − VCDT / VDS) × CCDT [μF] × RCDT [kΩ] tDIOV [ms] = −ln ( 1 − VCIT / VDS) × CCIT [μF] × RCIT [kΩ] tCIOV [ms] = −ln ( 1 − VCIT / VDS) × CCIT [μF] × RCIT [kΩ] In case CCCT = CCDT = CCIT = 0.1 [μF], each delay time tCU, tDL, tDIOV, tCIOV is calculated as follows. tDL [ms] = 1000 [kΩ] (typ.) × 0.1 [μF] = 100 [ms] (typ.) tDIOV [ms] = 200 [kΩ] (typ.) × 0.1 [μF] = 20 [ms] (typ.) tCIOV [ms] = 200 [kΩ] (typ.) × 0.1 [μF] = 20 [ms] (typ.) Discharge overcurrent release delay time (t DIOVR) and charge overcurrent release delay time (t CIOVR) can be selected from two types, and they are calculated by t DIOV and tCIOV as the following equations. 1 [ms] (typ.) is the internal delay time of the S-8203A Series. (1) tDIOVR = tDIOV × 10 + 1 [ms] (typ.), tCIOVR = tCIOV × 10 + 1 [ms] (typ.) (2) tDIOVR = tDIOV × 0.05 + 1 [ms] (typ.), tCIOVR = tCIOV × 0.05 + 1 [ms] (typ.) Load short-circuiting detection delay time (tSHORT) is fixed internally.

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK Rev.1.0_00 S-8203A Series 8. CTLC pin and CTLD pin The S-8203A Series has two pins to control. The CTLC pin controls the CO pin, the CTLD pin controls t he DO pin. Thus it is possible for users to control the CO pin and DO pin independently. These controls precede the battery protection circuit. Table 6 Conditions Set by CTLC Pin CTLC Pin CO Pin CTLC pin voltage ≥ VCTLC High-Z Open*1 High-Z CTLC pin voltage < VCTLC Normal status*2 *1. Pulled up by RCTLC when CTLC pin is open. *2. The status is controlled by the voltage detection circuit. Table 7 Conditions Set by CTLD Pin CTLD Pin DO Pin CTLD pin voltage ≥ VCTLD VSS level Open*1 VSS level CTLD pin voltage < VCTLD Normal status*2 *1. Pulled up by RCTLD when CTLD pin is open. *2. The status is controlled by the voltage detection circuit.

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK S-8203A Series Rev.1.0_00  Timing Charts 1. Overcharge detection and overdischarge detection VCUn VDUn VDLn VCLn Battery voltage CO pin voltage DO pin voltage VSS Charger connection Load connection Status*1 (With power-down function) Overcharge detection delay time (tCU) VSS VDD VDD VEB− High-Z VDD (4) VEB− (1)(3) (1)(2)(1) VM pin voltage 1 / 5 × VDD Status*1 (Without power-down function) Overdischarge detection delay time (tDL) (n = 1 to 3) *1. (1): Normal status (2): Overcharge status (3): Overdischarge status (4): Power-down status Remark The charger is assumed to charge with a constant current. V EB− indicates the open voltage of the charger. Figure 9

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK Rev.1.0_00 S-8203A Series 2. Discharge overcurrent detection VCUn VDUn VDLn (n = 1 to 3) VCLn Battery voltage VHC VHD VDD DO pin voltage VSS High-Z VDD VEB− CO pin voltage VDD VSS VM pin voltage VSHORT VSS VINI pin voltage VDD VDIOV Load connection Status*1 Discharge overcurrent detection delay time (tDIOV) (1) (2) (1) Load short circuit detection delay time (tSHORT) (2) High-Z (1) *1. (1): Normal status (2): Discharge overcurrent status Remark The charger is assumed to charge with a constant current. VEB− indicates the open voltage of the charger. Figure 10

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK S-8203A Series Rev.1.0_00 3. Charge overcurrent detection VCUn VDUn VDLn (n = 1 to 3) VCLn Battery voltage VHC VHD VDD DO pin voltage VSS CO pin voltage VDD VSS VM pin voltage VINI pin voltage VDD VDIOV Charger connection (3) (2) (1) (1)(2) VSS VCIOV High-Z (1) High-Z (4) VEB− VDD VEB− Load connection (Without power-down function) Status*1 (With power-down function) Charge overcurrent detection delay time (tCIOV) Charge overcurrent detection delay time (tCIOV) *1. (1): Normal status (2): Charge overcurrent status (3): Overdischarge status (4): Power-down status Remark The charger is assumed to charge with a constant current. V EB− indicates the open voltage of the charger. Figure 11

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK Rev.1.0_00 S-8203A Series  Connection Example of Battery Protection IC RVM EB+ EB− 1 VM 2 CO 3 DO

8 CDT

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK S-8203A Series Rev.1.0_00  Application Circuit RVM EB+ EB− 1 VM 2 CO 3 DO Figure 13 Overheat Protection via PTC [For PTC, contact] Murata Manufacturing Co., Ltd. Thermistor Products Department Nagaokakyo-shi, Kyoto 617-8555 Japan TEL +81-75-955-6863 Contact Us: http://www.murata.com/contact/index.html

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK Rev.1.0_00 S-8203A Series Table 8 Constants for External Components Symbol Min. Typ. Max. Unit RVC1 *1 0.47 1 1 k Ω RVC2 *1 0.47 1 1 k Ω RVC3 *1 0.47 1 1 k Ω RVC4 *1 0.47 1 1 k Ω RDO 1 5.1 10 k Ω RCO 0.1 1 1 M Ω RVM 3 5.1 10 k Ω RCTLC 0.1 1 1 k Ω RCTLD 0.1 1 1 k Ω RVINI 0.1 1 1 k Ω RSENSE 0 − − m Ω RVDD *1 43 100 100 Ω CVC1 *1 0.068 0.1 1 μF CVC2 *1 0.068 0.1 1 μF CVC3 *1 0.068 0.1 1 μF CCCT 0.01 0.1 − μF CCDT 0.01 0.1 − μF CCIT 0.02 0.1 − μF CVDD *1 0 1 10 μF *1. Set up a filter constant to be R VDD × CVDD = 68 μF•Ω or more, and to be R VC1 × CVC1 = RVC2 × CVC2 = RVC3 × C VC3 = RVDD × CVDD. Caution 1. The above constants may be changed without notice. 2. It is recommended that filter constants betw een VDD pin and VSS pin should be set approximately to 100 μF•Ω. e.g., C VDD × RVDD = 1.0 μF × 100 Ω = 100 μF•Ω Sufficient evaluation of transient power supply fluctuation and overcurrent protection function with the actual application is needed to determine the proper constants. Contact our sales office in case the constants should be set to other than 100 μF•Ω. 3. It has not been confirmed whether the operation is normal or not in circuits other than the example of connection. In addition, th e example of connection and the co nstant do not guarantee proper operation. Perform thorough evaluation using the actual application to set the constant.

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK S-8203A Series Rev.1.0_00  Precautions

• The application conditions for the in put voltage, output volt age, and load current should not exceed the package power dissipation.
• Batteries can be connected in any order, however, ther e may be cases when discharging cannot be performed when a battery is connected. In this case, short the VM pin and VSS pin or connect the battery charger to return to the normal status.
• If both an overcharge battery and an overdischarge battery are included among the whole batteries, the condition is set in overcharge status and overdischarge status. Therefore either charging or discharging is impossible.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit.
• SII Semiconductor Corporation claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party.

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK Rev.1.0_00 S-8203A Series  Characteristics (Typical Data) 1. Current consumption 1. 1 IOPE vs VDS 1. 2 IOPE vs Ta 0 5 10 25 IOPE [A] VDS [V] 15 20 IOPE [A] 40 0 25 50 75 Ta [°C] 25 85 1. 3 IPDN vs VDS 1. 4 IPDN vs Ta 0 5 10 25 IPDN [μA]0.06 0.07 0.04 0.01 0.02 0.00 VDS [V] 0.09 15 20 0.08 0.05 0.03 0.10 IPDN [μA] 0.07 0.06 0.04 0.01 0.02 0.00 0.09 0.08 0.05 0.03 0.10 −40 0 25 50 75 Ta [°C] −25 85

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK S-8203A Series Rev.1.0_00 2. Overcharge detection / release voltage, overdischarge detection / release voltage, discharge overcurrent detection voltage, load short-circuiting detection voltage, charge overcurrent detection voltage 2. 1 VCU vs Ta 2. 2 VCL vs Ta 40 0 25 50 75 Ta [°C] 25 85 VCU [V] 4.260 4.250 4.240 4.225 4.270 4.265 4.255 4.245 4.275 4.230 4.235 40 0 25 50 75 Ta [°C] 25 85 VCL [V] 4.170 4.150 4.130 4.100 4.190 4.180 4.160 4.140 4.200 4.110 4.120 2. 3 VDL vs Ta 2. 4 VDU vs Ta VDL [V] 2.720 2.680 2.640 2.620 2.760 2.740 2.700 2.660 2.780 40 0 25 50 75 Ta [°C] 25 85 −40 0 25 50 75 Ta [°C] −25 85 VDU [V] 3.040 3.000 2.960 2.900 3.080 3.060 3.020 2.980 3.100 2.920 2.940 2. 5 VDIOV vs Ta 2. 6 VSHORT vs Ta VDIOV [V] 0.155 0.150 0.140 0.135 0.160 0.145 0.165 −40 0 25 50 75 Ta [°C] −25 85 −40 0 25 50 75 Ta [°C] −25 85 VSHORT [V] 0.540 0.500 0.460 0.400 0.580 0.560 0.520 0.480 0.600 0.420 0.440 2. 7 VCIOV vs Ta VCIOV [V] −0.090 −0.100 −0.120 −0.130 −0.080 −0.110 −0.070 −40 0 25 50 75 Ta [°C] −25 85

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK Rev.1.0_00 S-8203A Series 3. CCT pin internal resistance / detection voltage, CDT pin internal resistance / detection voltage, CIT pin internal resistance / detection voltage and short-circuiting detection voltage delay time 3. 1 RCCT vs Ta 3. 2 VCCT vs Ta (VDS = 11.5 V) RCCT [M] 10.0 9.0 7.0 6.0 11.0 8.0 12.0 −40 0 25 50 75 Ta [°C] −25 85 VCCT [V] 8.1 8.0 7.8 8.2 7.9 8.3 40 0 25 50 75 Ta [°C] 25 85 3. 3 RCDT vs Ta 3. 4 VCDT vs Ta (VDS = 8.5 V) RCDT [k] 1000 900 700 600 1100 800 1200 −40 0 25 50 75 Ta [°C] −25 85 VCDT [V] 6.0 5.9 5.7 6.1 5.8 6.2 40 0 25 50 75 Ta [°C] 25 85 3. 5 RCIT vs Ta 3. 6 VCIT vs Ta (VDS = 10.5 V) RCIT [k] 200 180 140 120 220 160 240 −40 0 25 50 75 Ta [°C] −25 85 VCCT [V] 7.4 7.3 7.1 7.5 7.2 7.6 40 0 25 50 75 Ta [°C] 25 85 3. 7 tSHORT vs Ta tSHORT [μs]400.0 300.0 100.0 500.0 200.0 600.0 −40 0 25 50 75 Ta [°C] −25 85

BATTERY PROTECTION IC FOR 3-SERIES CELL PACK S-8203A Series Rev.1.0_00 4. CO pin source / leakage current, DO pin source / sink current 4. 1 ICOH vs VCO 4. 2 ICOL vs VCO 0 5 15 ICOH [mA] VCO [V] 10 20 0 5 10 25 ICOL [μA] 0.08 0.06 0.02 VCO [V] 15 20 0.04 0.10 4. 3 IDOH vs VDO 4. 4 IDOL vs VDO 0 5 15 IDOH [mA] V DO [V] 0 1 25 IDOL [mA] 0.5 1.0 2.0 2.5 VDO [V] 1.5

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