S8200A

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www.sii-ic.com BATTERY PROTECTION IC FOR 1-CELL PACK © Seiko Instruments Inc., 2010-2014 Rev.4.0_00 Seiko Instruments Inc. 1 The S-8200A Series is a protection IC for lithium-ion / lithium polymer rechargeable batteries and includes high-accuracy voltage detection circuits and delay circuits. The S-8200A Series is suitable for protecting 1-cell lithium-ion / lithium polymer rechargeable battery packs from overcharge, overdischarge, and overcurrent.  Features

• High-accuracy voltage detection circuit Overcharge detection voltage 3.5 V to 4.5 V (5 mV step) Accuracy ±20 mV (Ta = +25°C) Accuracy ±25 mV (Ta = −10°C to +60°C) Overcharge release voltage 3.1 V to 4.5 V*1 Accuracy ±30 mV Overdischarge detection voltage 2.0 V to 3.4 V (10 mV step) Accuracy ±35 mV Overdischarge release voltage 2.0 V to 3.4 V *2 Accuracy ±50 mV Discharge overcurrent detection voltage 0. 05 V to 0.20 V (10 mV step) Accuracy ±10 mV Charge overcurrent detection voltage −0.20 V to −0.05 V (25 mV step) Accuracy ±15 mV
• Detection delay times are generated only by an internal circuit (external capacitors are unnecessary). Accuracy ±20%
• High-withstand voltage device is used for charger connection pins (VM pin and CO pin: Absolute maximum rating = 28 V)
• 0 V battery charge function "available" / "unavailable" is selectable.
• Power-down function "available" / "unavailable" is selectable.
• Wide operation temperature range Ta = −40°C to +85°C
• Low current consumption During operation 2.8 μA typ., 5.0 μA max. (Ta = +25°C) During power-down 0.1 μ A max. (Ta = +25°C)
• Lead-free (Sn 100%), halogen-free *1. Overcharge release voltage = Overcharge detection voltage − Overcharge hysteresis voltage (Overcharge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.4 V in 50 mV step.) *2. Overdischarge release voltage = Overdischarge detection voltage + Overdischarge hysteresis voltage (Overdischarge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.7 V in 100 mV step.)  Applications
• Lithium-ion rechargeable battery pack
• Lithium polymer rechargeable battery pack  Packages
• SOT-23-6
• SNT-6A

BATTERY PROTECTION IC FOR 1-CELL PACK S-8200A Series Rev.4.0_00 Seiko Instruments Inc. 2  Block Diagram VM VSS VDD CO DO Output control circuit RVMD RVMS

0 V battery charge /

Discharge overcurrent detection comparator Charge overcurrent detection comparator Load short-circuiting detection comparator Overcharge detection comparator Overdischarge detection comparator Remark All diodes shown in figure are parasitic diodes. Figure 1

BATTERY PROTECTION IC FOR 1-CELL PACK Rev.4.0_00 S-8200A Series Seiko Instruments Inc. 3  Product Name Structure 1. Product name S-8200A xx - xxxx U Package abbreviation and IC packing specifications *1 M6T1: SOT-23-6, Tape I6T1: SNT-6A, Tape Serial code*2 Sequentially set from AA to ZZ Environmental code U: Lead-free (Sn 100%), halogen-free *1. Refer to the tape drawing. *2. Refer to "3. Product name list". 2. Packages Table 1 Package Drawing Codes Package Name Dimension Tape Reel Land SOT-23-6 MP006-A-P-SD MP006-A-C-SD MP006-A-R-SD − SNT-6A PG006-A-P-SD PG006-A-C-SD PG006-A-R-SD PG006-A-L-SD

BATTERY PROTECTION IC FOR 1-CELL PACK S-8200A Series Rev.4.0_00 Seiko Instruments Inc. 4 3. Product name list 3. 1 SOT-23-6 Table 2 Product Name Over- charge Detection Voltage [VCU] Over- charge Release Voltage [VCL] Over- discharge Detection Voltage [VDL] Over- discharge Release Voltage [VDU] Discharge Overcurrent Detection Voltage [VDIOV] Load short- circuiting Detection Voltage [VSHORT] Charge Overcurrent Detection Voltage [VCIOV]

0 V Battery

Combination*1 Power- down Function *1. Refer to Table 4 about the details of the delay time combinations. 3. 2 SNT-6A Table 3 Product Name Over- charge Detection Voltage [VCU] Over- charge Release Voltage [VCL] Over- discharge Detection Voltage [VDL] Over- discharge Release Voltage [VDU] Discharge Overcurrent Detection Voltage [VDIOV] Load short- circuiting Detection Voltage [VSHORT] Charge Overcurrent Detection Voltage [VCIOV] Combination*1 Power- down Function *1. Refer to Table 4 about the details of the delay time combinations. Remark Please contact our sales office for the products with detection voltage value other than those specified above.

BATTERY PROTECTION IC FOR 1-CELL PACK Rev.4.0_00 S-8200A Series Seiko Instruments Inc. 5 Table 4 Delay Time Combination Overcharge Detection Delay Time [tCU] Overdischarge Detection Delay Time [tDL] Discharge Overcurrent Detection Delay Time [tDIOV] Load Short-circuiting Detection Delay Time [tSHORT] Charge Overcurrent Detection Delay Time [tCIOV] (1) 1.0 s 64 ms 8 ms 250 μs 8 ms (2) 1.0 s 32 ms 8 ms 250 μs 8 ms (3) 256 ms 32 ms 8 ms 250 μs 16 ms (4) 1.0 s 128 ms 8 ms 250 μs 8 ms (5) 1.0 s 128 ms 16 ms 500 μs 16 ms (6) 1.0 s 128 ms 16 ms 250 μs 8 ms Remark The delay times can be changed within the range listed in Table 5. For details, please contact our sales office. Table 5 Delay Time Symbol Selection Range Remark Overcharge detection delay time tCU 256 ms 512 ms 1.0 s*1 Select a value from the left. Overdischarge detection delay time t DL 32 ms 64 ms*1 128 ms Select a value from the left. Discharge overcurrent detection delay time t DIOV 4 ms 8 ms*1 16 ms Select a value from the left. Load short-circuiting detection delay Time t SHORT 250 μs*1 500 μs 1 ms Select a value from the left. Charge overcurrent detection delay time t CIOV 4 ms 8 ms*1 16 ms Select a value from the left. *1. This value is the delay time of the standard product.

BATTERY PROTECTION IC FOR 1-CELL PACK S-8200A Series Rev.4.0_00 Seiko Instruments Inc. 6  Pin Configurations 1. SOT-23-6 13 2 546 Top view Table 6 Pin No. Symbol Description

1 DO Connection pin of discharge control FET gate

(CMOS output)

2 VM Voltage detection pin between VM pin and VSS pin

(Overcurrent / charger detection pin)

3 CO Connection pin of charge control FET gate

(CMOS output)

4 NC*1 No connection

Figure 2 5 VDD Connection pin for positive power supply input

6 VSS Connection pin for negative power supply input

*1. The NC pin is electrically open. The NC pin can be connected to VDD pin or VSS pin. 2. SNT-6A Top view Figure 3 Table 7 Pin No. Symbol Description

1 NC*1 No connection

2 CO Connection pin of charge control FET gate

(CMOS output)

3 DO Connection pin of discharge control FET gate

(CMOS output)

4 VSS Connection pin for negative power supply input

5 VDD Connection pin for positive power supply input

6 VM Voltage detection pin between VM pin and VSS pin

(Overcurrent / charger detection pin) *1. The NC pin is electrically open. The NC pin can be connected to VDD pin or VSS pin.

BATTERY PROTECTION IC FOR 1-CELL PACK Rev.4.0_00 S-8200A Series Seiko Instruments Inc. 7  Absolute Maximum Ratings Table 8 (Ta = +25°C unless otherwise specified) Item Symbol Applied Pin Absolute Maximum Rating Unit Input voltage between VDD pin and VSS pin V DS VDD VSS − 0.3 to VSS + 12 V VM pin input voltage VVM VM V DD − 28 to VDD + 0.3 V DO pin output voltage VDO DO V SS − 0.3 to VDD + 0.3 V CO pin output voltage VCO CO V VM − 0.3 to VDD + 0.3 V Power dissipation SOT-23-6 PD − 650*1 mW SNT-6A − 400*1 mW Operation ambient temperature Topr − −40 to +85 °C Storage temperature Tstg − −55 to +125 °C *1. When mounted on board [Mounted board] (1) Board size: 114.3 mm × 76.2 mm × t1.6 mm (2) Board name: JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 0 50 100 150 400 200 700 300 100 500 600 SNT-6A SOT-23-6 Power Dissipation (PD) [mW] Ambient Temperature (Ta) [°C] Figure 4 Power Dissipation of Package (When Mounted on Board)

BATTERY PROTECTION IC FOR 1-CELL PACK S-8200A Series Rev.4.0_00 Seiko Instruments Inc. 8  Electrical Characteristics 1. Ta = +25°C Table 9 (Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection Voltage Overcharge detection voltage VCU − V CU − 0.020 V CU V CU + 0.020 V 1 Ta = −10°C to +60°C*1 VCU − 0.025 V CU V CU + 0.025 V 1 Overcharge release voltage VCL VCL ≠ VCU V CL − 0.030 V CL V CL + 0.030 V 1 VCL = VCU V CL − 0.025 V CL V CL + 0.020 V 1 Overdischarge detection voltage VDL − V DL − 0.035 V DL V DL + 0.035 V 2 Overdischarge release voltage VDU VDL ≠ VDU V DU − 0.050 V DU V DU + 0.050 V 2 VDL = VDU V DU − 0.035 V DU V DU + 0.035 V 2 Discharge overcurrent detection voltage VDIOV − V DIOV − 0.010 V DIOV V DIOV + 0.010 V 2 Load short-circuiting detection voltage VSHORT − V SHORT − 0.100 V SHORT V SHORT + 0.100 V 2 Charge overcurrent detection voltage VCIOV − V CIOV − 0.015 V CIOV V CIOV + 0.015 V 2

0 V Battery Charge Function

0 V battery charge starting charger voltage V0CHA 0 V battery charge function

"available" 0.0 0.7 1.0 V 2

0 V battery charge inhibition battery

voltage V0INH 0 V battery charge function "unavailable" 0.6 0.8 1.1 V 2 Internal Resistance Resistance between VM pin and VDD pin RVMD V DD = 1.8 V, VVM = 0 V 100 300 900 kΩ 3 Resistance between VM pin and VSS pin RVMS V DD = 3.4 V, VVM = 1.0 V 10 20 40 k Ω 3 Input Voltage Operation voltage between VDD pin and VSS pin V DSOP1 − 1.5 − 6.5 V − Operation voltage between VDD pin and VM pin V DSOP2 − 1.5 − 28 V − Input Current (With Power-down Function) Current consumption during operation IOPE V DD = 3.4 V, VVM = 0 V 1.0 2.8 5.0 μA2 Current consumption during power-down IPDN V DD = VVM = 1.5 V − − 0.1 μA 2 Input Current (Without Power-down Function) Current consumption during operation IOPE V DD = 3.4 V, VVM = 0 V 1.0 2.8 5.0 μA2 Current consumption during overdischarge IOPED V DD = VVM = 1.5 V − − 3.5 μA 2 Output Resistance CO pin resistance "H" RCOH VCO = 3.0 V, VDD = 3.4 V, VVM = 0 V 5 10 20 k Ω 4 CO pin resistance "L" RCOL VCO = 0.4 V, VDD = 4.6 V, VVM = 0 V 5 10 20 k Ω 4 DO pin resistance "H" RDOH VDO = 3.0 V, VDD = 3.4 V, VVM = 0 V 5 10 20 k Ω 4 DO pin resistance "L" RDOL VDO = 0.4 V, VDD = 1.8 V, VVM = 0 V 5 10 20 k Ω 4 Delay Time Overcharge detection delay time tCU − tCU × 0.8 t CU t CU × 1.2 − 5 Overdischarge detection delay time tDL − tDL × 0.8 t DL t DL × 1.2 − 5 Discharge overcurrent detection delay time tDIOV − tDIOV × 0.8 t DIOV t DIOV × 1.2 − 5 Load short-circuiting detection delay time tSHORT − tSHORT × 0.8 t SHORT t SHORT × 1.2 − 5 Charge overcurrent detection delay time tCIOV − tCIOV × 0.8 t CIOV t CIOV × 1.2 − 5 *1. Since products are not screened at high and low temperature, the specif ication for this temperatur e range is guaranteed by design, not tested in production.

BATTERY PROTECTION IC FOR 1-CELL PACK Rev.4.0_00 S-8200A Series Seiko Instruments Inc. 9 2. Ta = −40°C to +85°C*1 Table 10 (Ta = −40°C to +85°C*1 unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection Voltage Overcharge detection voltage VCU − V CU − 0.045 V CU V CU + 0.030 V 1 Overcharge release voltage VCL VCL ≠ VCU V CL − 0.070 V CL V CL + 0.040 V 1 VCL = VCU V CL − 0.050 V CL V CL + 0.030 V 1 Overdischarge detection voltage VDL − V DL − 0.070 V DL V DL + 0.045 V 2 Overdischarge release voltage VDU VDL ≠ VDU V DU − 0.090 V DU V DU + 0.060 V 2 VDL = VDU V DU − 0.070 V DU V DU + 0.045 V 2 Discharge overcurrent detection voltage VDIOV − V DIOV − 0.010 V DIOV V DIOV + 0.010 V 2 Load short-circuiting detection voltage VSHORT − V SHORT − 0.100 V SHORT V SHORT + 0.100 V 2 Charge overcurrent detection voltage VCIOV − V CIOV − 0.015 V CIOV V CIOV + 0.015 V 2

0 V battery charge starting charger voltage V0CHA 0 V battery charge

function "available" 0.0 0.7 1.5 V 2 voltage V0INH 0 V battery charge function "unavailable" 0.4 0.8 1.3 V 2 Internal Resistance Resistance between VM pin and VDD pin RVMD V DD = 1.8 V, VVM = 0 V 78 300 1310 kΩ 3 Resistance between VM pin and VSS pin RVMS V DD = 3.4 V, VVM = 1.0 V 7.2 20 44 kΩ 3 Input Voltage Operation voltage between VDD pin and VSS pin V DSOP1 − 1.5 − 6.5 V − Operation voltage between VDD pin and VM pin V DSOP2 − 1.5 − 28 V − Input Current (With Power-down Function) Current consumption during operation IOPE V DD = 3.4 V, VVM = 0 V 0.7 2.8 5.5 μA2 Current consumption during power-down IPDN V DD = VVM = 1.5 V − − 0.15 μA 2 Input Current (Without Power-down Function) Current consumption during operation IOPE V DD = 3.4 V, VVM = 0 V 0.7 2.8 5.5 μA2 Current consumption during overdischarge IOPED V DD = VVM = 1.5 V − − 3.8 μA 2 Output Resistance CO pin resistance "H" RCOH VCO = 3.0 V, VDD = 3.4 V, VVM = 0 V 2.4 10 30 k Ω 4 CO pin resistance "L" RCOL VCO = 0.4 V, VDD = 4.6 V, VVM = 0 V 2.4 10 30 k Ω 4 DO pin resistance "H" RDOH VDO = 3.0 V, VDD = 3.4 V, VVM = 0 V 2.4 10 30 k Ω 4 DO pin resistance "L" RDOL VDO = 0.4 V, VDD = 1.8 V, VVM = 0 V 2.4 10 30 k Ω 4 Delay Time Overcharge detection delay time tCU − tCU × 0.6 t CU t CU × 1.6 − 5 Overdischarge detection delay time tDL − tDL × 0.6 t DL t DL × 1.6 − 5 Discharge overcurrent detection delay time tDIOV − tDIOV × 0.6 t DIOV t DIOV × 1.6 − 5 Load short-circuiting detection delay time tSHORT − tSHORT × 0.6 t SHORT t SHORT × 1.6 − 5 Charge overcurrent detection delay time tCIOV − tCIOV × 0.6 t CIOV t CIOV × 1.6 − 5 *1. Since products are not screened at high and low temperature, the specif ication for this temperatur e range is guaranteed by design, not tested in production.

BATTERY PROTECTION IC FOR 1-CELL PACK S-8200A Series Rev.4.0_00 Seiko Instruments Inc. 10  Test Circuits Caution Unless otherwise specified, the output voltage levels "H" and "L" at CO pin (V CO) and DO pin (V DO) are judged by the threshold voltage (1.0 V) of the N-channel FET. Judge the CO pin level with respect to V VM and the DO pin level with respect to VSS. 1. Overcharge detection voltage, overcharge release voltage (Test circuit 1) Overcharge detection voltage (VCU) is defined as the voltage V1 at which V CO goes from "H" to "L" when the voltage V1 is gradually increased from the starting conditi on of V1 = 3.4 V. Over charge release voltage (V CL) is defined as the voltage V1 at which V CO goes from "L" to "H" when the voltage V1 is then gradually decreased. Overcharge hysteresis voltage (VHC) is defined as the difference between VCU and VCL. 2. Overdischarge detection voltage, overdischarge release voltage (Test circuit 2) Overdischarge detection voltage (VDL) is defined as the voltage V1 at which V DO goes from "H" to "L" when the voltage V1 is gradually decreased from the star ting condition of V1 = 3.4 V, V2 = 0 V. Overdischarge release voltage (V DU) is defined as the voltage V1 at which V DO goes from "L" to "H" when the voltage V1 is then gradually increased. Overdischarge hysteresis voltage (VHD) is defined as the difference between VDU and VDL. 3. Discharge overcurrent detection voltage (Test circuit 2) Discharge overcurrent detection voltage (V DIOV) is defined as the voltage V2 whose delay time for changing V DO from "H" to "L" is discharge overcurrent delay time (t DIOV) when the voltage V2 is increased from the starting condition of V1 = 3.4 V, V2 = 0 V. 4. Load short-circuiting detection voltage (Test circuit 2) Load short-circuiting detection voltage (V SHORT) is defined as the voltage V2 whose delay time for changing V DO from "H" to "L" is load short-circuiting delay time (t SHORT) when the voltage V2 is increased from the starting condition of V1 = 3.4 V, V2 = 0 V. 5. Charge overcurrent detection voltage (Test circuit 2) Charge overcurrent detection voltage (VCIOV) is defined as the voltage V2 whose delay time for changing VCO from "H" to "L" is charge overcurrent delay time (t CIOV) when the voltage V2 is decreased from the starting condition of V1 = 3.4 V, V2 = 0 V. 6. Current consumption during operation (Test circuit 2) The current consumption during operation (I OPE) is the current that flows through the VDD pin (I DD) under the set conditions of V1 = 3.4 V and V2 = 0 V. 7. Current consumption during power-down, current consumption during overdischarge (Test circuit 2) 7. 1 With power-down function The current consumption during power-down (IPDN) is IDD under the set conditions of V1 = V2 = 1.5 V. 7. 2 Without power-down function The current consumption during overdischarge (IOPED) is IDD under the set conditions of V1 = V2 = 1.5 V.

BATTERY PROTECTION IC FOR 1-CELL PACK Rev.4.0_00 S-8200A Series Seiko Instruments Inc. 11 8. Resistance between VM pin and VDD pin (Test circuit 3) RVMD is the resistance between VM pin and VDD pin under the set conditions of V1 = 1.8 V, V2 = 0 V. 9. Resistance between VM pin and VSS pin (Test circuit 3) RVMS is the resistance between VM pin and VSS pin under the set conditions of V1 = 3.4 V, V2 = 1.0 V. 10. CO pin resistance "H" (Test circuit 4) The CO pin resistance "H" (RCOH) is the resistance between VDD pin and CO pin under the set conditions of V1 = 3.4 V, V2 = 0 V, V3 = 3.0 V. 11. CO pin resistance "L" (Test circuit 4) The CO pin resistance "L" (RCOL) is the resistance between VM pin and CO pin under the set conditions of V1 = 4.6 V, V2 = 0 V, V3 = 0.4 V. 12. DO pin resistance "H" (Test circuit 4) The DO pin resistance "H" (RDOH) is the resistance between VDD pin and DO pin under the set conditions of V1 = 3.4 V, V2 = 0 V, V4 = 3.0 V. 13. DO pin resistance "L" (Test circuit 4) The DO pin resistance "L" (RDOL) is the resistance between VSS pin and DO pin under the set conditions of V1 = 1.8 V, V2 = 0 V, V4 = 0.4 V. 14. Overcharge detection delay time (Test circuit 5) The overcharge detection delay time (tCU) is the time needed for VCO to go to "L" just after the voltage V1 increases and exceeds VCU under the set conditions of V1 = 3.4 V, V2 = 0 V. 15. Overdischarge detection delay time (Test circuit 5) The overdischarge detection delay time (tDL) is the time needed for VDO to go to "L" after the voltage V1 decreases and falls below VDL under the set conditions of V1 = 3.4 V, V2 = 0 V. 16. Discharge overcurrent detection delay time (Test circuit 5) The discharge overcurrent detection delay time (t DIOV) is the time needed for V DO to go to "L" after the voltage V2 increases and exceeds VDIOV under the set conditions of V1 = 3.4 V, V2 = 0 V.

BATTERY PROTECTION IC FOR 1-CELL PACK S-8200A Series Rev.4.0_00 Seiko Instruments Inc. 12 17. Load short-circuiting detection delay time (Test circuit 5) The load short-circuiting detection delay time (t SHORT) is the time needed for V DO to go to "L" after the voltage V2 increases and exceeds VSHORT under the set conditions of V1 = 3.4 V, V2 = 0 V. 18. Charge overcurrent detection delay time (Test circuit 5) The charge overcurrent detection delay time (t CIOV) is the time needed for V CO to go to "L" after the voltage V2 decreases and falls below VCIOV under the set conditions of V1 = 3.4 V, V2 = 0 V. 19. 0 V battery charge starting charger voltage (0 V battery charge function "available") (Test circuit 2) The 0 V charge starting charger voltage (V 0CHA) is defined as the absolute value of voltage V2 at which V CO goes to "H" (VCO = VDD) when the voltage V2 is gradually decreased from the starting conditions of V1 = V2 = 0 V. 20. 0 V battery charge inhibition battery voltage (0 V battery charge function "unavailable") (Test circuit 2) The 0 V charge inhibition battery voltage (V 0INH) is defined as the voltage V1 at which V CO goes to "H" (V CO = V DD) when the voltage V1 is gradually increased, after setting V1 = 0 V, V2 = −4.0 V.

BATTERY PROTECTION IC FOR 1-CELL PACK S-8200A Series Rev.4.0_00 Seiko Instruments Inc. 14  Operation Remark Refer to " Battery Protection IC Connection Example". 1. Normal status The S-8200A Series monitors the voltage of the battery connected between the VDD pi n and VSS pin, the voltage between the VM pin and VSS pin to control charging and disc harging. When the battery volt age is in the range from overdischarge detection voltage (VDL) to overcharge detection voltage (VCU), and the VM pin voltage is in the range from charge overcurrent detection voltage (VCIOV) to discharge overcurrent detection voltage (VDIOV), the S-8200A Series turns both the charge and discharge control FETs on. This condition is called the normal status, and in this condition charging and discharging can be carried out freely. The resistance (RVMD) between the VM pin and VDD pin, and the resistance (RVMS) between the VM pin and VSS pin are not connected in the normal status. Caution When the battery is connected for the first time, the S-8200A Series may not be in the normal status. In this case, short the VM pin and VSS pin, or set the VM pin voltage at the level of V CIOV or more and at the level of V DIOV or less by connecting the charger. The S-8200A Series then becomes the normal status. 2. Overcharge status 2. 1 VCL ≠ VCU (Product in which overcharge release voltage differs from overcharge detection voltage) When the battery voltage becomes higher than V CU during charging in the normal status and detection continues for the overcharge detection delay time (t CU) or longer, the S-8200A Series turn s the charge control FEToff to stop charging. This condition is called the overcharge status. RVMD and RVMS are not connected in the overcharge status. The overcharge status is released in the following two cases. (1) In the case that the VM pin voltage is lower than VDIOV, the S-8200A Series releases the overcharge status when the battery voltage falls below overcharge release voltage (VCL). (2) In the case that the VM pin voltage is higher than or equal to V DIOV, the S-8200A Series releases the overcharge status when the battery voltage falls below V CU. When the discharge is started by connecting a load after the overcharge detection, the VM pin voltage rises by the Vf voltage of the parasitic diode than the VSS pin voltage, be cause the discharge current flows through the parasitic diode in the charge control FET. If this VM pin voltage is higher than or equal to V DIOV, the S-8200A Series releases the overcharge status when the battery voltage is lower than or equal to VCU. Caution If the battery is charged to a voltage higher than V CU and the battery voltage does not fall below V CU even when a heavy load is connected, discharge overcurrent detection and load short-circuiting detection do not function until the battery voltage falls below V CU. Since an actual battery has an internal impedance of tens of m Ω, the battery voltage drops immediately after a heavy load that causes overcurrent is connected, and discharge overcurrent detection and load short-circuiting detection function.

BATTERY PROTECTION IC FOR 1-CELL PACK Rev.4.0_00 S-8200A Series Seiko Instruments Inc. 15 2. 2 VCL = VCU (Product in which overcharge release voltage is the same as overcharge detection voltage) When the battery voltage becomes higher than V CU during charging in the normal status and detection continues for tCU or longer, the S-8200A Series turns the charge control FET off to stop charging. This condition is called the overcharge status. RVMD and RVMS are not connected in the overcharge status. The overcharge status is released in the following two cases. (1) In the case that the VM pin vo ltage is higher than or equal to V CIOV, and is lower than VDIOV, the S-8200A Series releases the overcharge status when the battery voltage falls below VCL. (2) In the case that the VM pin voltage is higher than or equal to VDIOV, the S-8200A Series releases the overcharge status when the battery voltage falls below VCU. The discharge is started by connecting a load after the overcharge detection, the VM pin voltage rises more than the VSS pin voltage due to the V f voltage of the parasitic di ode, because the discharge current flows through the parasitic diode in the charging control FET. If this VM pin voltage is higher than or equal to VDIOV, the S-8200A Series releases the overcharge status when the battery voltage is lower than or equal to VCU. For the actual application boards, chang ing the battery voltage and the charger voltage simultaneously enables to measure V CL. In this case, the charger is always necessary to have the equivalent voltage level to the battery voltage. The charger keeps VM pin voltage higher than or equal to V CIOV and lower than or equal to V DIOV. The S-8200A Series releases the overcharge status when the battery voltage falls below VCL. Caution 1. If the battery is charged to a voltage higher than V CU and the battery voltage does not fall below VCU even when a heavy load is connected, discharge overcurrent detection and load short-circuiting detection do not function until the battery voltage falls below V CU. Since an actual battery has an internal impedance of tens of m Ω, the battery voltage drops immediately after a heavy load that causes overcurrent is connected, and discharge overcurrent detection and load short-circuiting detection function. 2. When a charger is connected after overcharge detection, the overcharge status is not released even if the battery voltage is below V CL. The overcharge status is released when the VM pin voltage goes over VCIOV by removing the charger. 3. Overdischarge status When the battery voltage falls below overdischarge detection voltage (V DL) during discharging in the normal status and the detection continues for the overdischarge detection delay time (tDL) or longer, the S-8200A Series turns the discharge control FET off to stop discharging. This condition is called the overdischarge status. Under the overdischarge status, the VM pin and VDD pin are shorted by R VMD in the S-8200A Series. The VM pin voltage is pulled up by RVMD. When a battery in the overdischarge status is connected to a charger and provided that the VM pin voltage is lower than −0.7 V typ., the S-8200A Series releases the overdischarge status when the battery voltage reaches V DL or higher. When VM pin voltage is not lower than −0.7 V typ., the S-8200A Series releas es the overdischarge status when the battery voltage reaches VDU or higher. RVMS is not connected in the overdischarge status. 3. 1 With power-down function Under the overdischarge status, when voltage between the VDD pin and VM pin is 0.8 V typ. or lower, the power- down function works and the current c onsumption is reduced to the curr ent consumption during power-down (I PDN). By connecting a battery charger, the power-down function is released when the VM pin voltage is 0.7 V typ. or lower.

BATTERY PROTECTION IC FOR 1-CELL PACK S-8200A Series Rev.4.0_00 Seiko Instruments Inc. 16 4. Discharge overcurrent status (discharge overcurrent, load short-circuiting) When a battery in the normal status is in the status where the VM pin vo ltage is equal to or higher than V DIOV because the discharge current is equal to or hi gher than the specified val ue and the status lasts fo r the discharge overcurrent detection delay time (t DIOV), the discharge control FET is turned off and disc harging is stopped. This status is called the discharge overcurrent status. In the discharge overcurrent status, the VM pin and VSS pin are shorted by the R VMS in the S-8200A Series. However, the VM pin voltage is the VDD pin vo ltage due to the load as long as the load is connected. When the load is disconnected, the VM pin returns to the VSS pin voltage. The VM pin voltage returns to V DIOV or lower, the S-8200A Series releases the discharge overcurrent status. RVMD is not connected in the discharge overcurrent status. 5. Charge overcurrent status When a battery in the normal status is in the status where the VM pin voltage is equal to or lower than VCIOV because the charge current is equal to or higher th an the specified value and the status lasts for the charge overcurrent detection delay time (t CIOV), the charge control FET is turned off and chargi ng is stopped. This status is called the charge overcurrent status. The S-8200A Series releases the charge overcurrent status when the VM pin voltage returns to V CIOV or higher by removing the charger. The charge overcurrent detection function does not work in the overdischarge status. R VMD and RVMS are not connected in the charge overcurrent status. 6. 0 V battery charge function "available" This function is used to recharge a connected battery whose voltage is 0 V due to self-discharge. When the 0 V battery charge starting charger voltage (V 0CHA) or a higher voltage is applied between the EB + and EB − pins by connecting a charger, the charge control FET gate is fixed to the VDD pin voltage. When the voltage between the gate and source of the charge control FET becomes equal to or higher than the threshold voltage due to the charger voltage, the charge control FET is turned on to st art charging. At this time, the discharge control FET is off and the charging current flows through t he internal parasitic diode in the discharging control FET. When the battery voltage becomes equal to or higher than VDU, the S-8200A Series enters the normal status. Caution 1. Some battery providers do not recommend charging for a completely self-discharged battery. Please ask the battery provider to determine whether to enable or inhibit the 0 V battery charge function. 2. The 0 V battery charge function has higher priority than the charge overcurrent detection function. Consequently, a product in which use of the 0 V battery charge function is enabled charges a battery forcibly and the charge overcurrent cannot be detected when the battery voltage is lower than V DL. 7. 0 V battery charge function "unavailable" This function inhibits recharging when a battery that is inte rnally short-circuited (0 V ba ttery) is connected. When the battery voltage is the 0 V battery charge inhibition battery voltage (V 0INH) or lower, the charge control FET gate is fixed to the EB− pin voltage to inhibit charging. When the battery voltage is V0INH or higher, charging can be performed. Caution Some battery providers do not recommend charging for a completely self-discharged battery. Please ask the battery provider to determine whether to enable or inhibit the 0 V battery charge function.

BATTERY PROTECTION IC FOR 1-CELL PACK Rev.4.0_00 S-8200A Series Seiko Instruments Inc. 17 8. Delay circuit The detection delay times are determined by dividing a clock of approximately 4 kHz by the counter. Remark tDIOV and t SHORT start when V DIOV is detected. When V SHORT is detected over t SHORT after V DIOV, the S-8200A Series turns the discharge control FET off within tSHORT from the time of detecting VSHORT. DO pin voltage VM pin voltage VDD VDD Time VDIOV VSS VSS VSHORT tSHORT Time tD 0 ≤ tD ≤ tSHORT Figure 10

BATTERY PROTECTION IC FOR 1-CELL PACK S-8200A Series Rev.4.0_00 Seiko Instruments Inc. 18  Timing Charts 1. Overcharge detection, overdischarge detection VCU VDU (VDL + VHD) VDL VCL (VCU − VHC) Battery voltage VSS CO pin voltage VDD DO pin voltage VSS Charger connection Load connection Status*1 Overcharge detection delay time(tCU) Overdischarge detection delay time (tDL) VDIOV VSS VM pin voltage VDD VEB− VDD VCIOV VEB− *1. (1): Normal status (2): Overcharge status (3): Overdischarge status Remark The charger is assumed to charge with a constant current. Figure 11

BATTERY PROTECTION IC FOR 1-CELL PACK Rev.4.0_00 S-8200A Series Seiko Instruments Inc. 19 2. Discharge overcurrent detection VDD VSS VSHORT (1) (2) (1) (1) Load short-circuiting detection delay time (tSHORT) (2) VDIOV Discharge overcurrent detection dela y time (tDIOV) VCU VDU (VDL + VHD) VDL VCL (VCU − VHC) Battery voltage VSS CO pin voltage VDD DO pin voltage VSS Load connection Status*1 VM pin voltage VDD *1. (1): Normal status (2): Discharge overcurrent status Remark The charger is assumed to charge with a constant current. Figure 12

BATTERY PROTECTION IC FOR 1-CELL PACK S-8200A Series Rev.4.0_00 Seiko Instruments Inc. 20 3. Charge overcurrent detection VDD DO pin voltage VSS VDD VSS CO pin voltage VDD VSS VM pin voltage VCIOV Status*1 (3) (1) Charger connection VEB− VEB− Charge overcurrent detection delay time (tCIOV) VCU VDU (VDL + VHD) VDL VCL (VCU − VHC) Battery voltage (2) Load connection (1) (1) (2) Overdischarge detection delay time (tDL) Charge overcurrent detection delay time (t CIOV) *1. (1): Normal status (2): Charge overcurrent status (3): Overdischarge status Remark The charger is assumed to charge with a constant current. Figure 13

BATTERY PROTECTION IC FOR 1-CELL PACK Rev.4.0_00 S-8200A Series Seiko Instruments Inc. 21  Battery Protection IC Connection Example Battery C1 VSS DO VDD CO VM S-8200A Series FET1 FET2 EB− EB+ Figure 14 Table 11 Constants for External Components Symbol Part Purpose Min. Typ. Max. Remark FET1 N-channel MOS FET Discharge control − − − Threshold voltage ≤ Overdischarge detection voltage*1 Gate to source withstand voltage ≥ Charger voltage*2 FET2 N-channel MOS FET Charge control − − − Threshold voltage ≤ Overdischarge detection voltage Gate to source withstand voltage ≥ Charger voltage*2 R1 Resistor ESD protection, For power fluctuation 150 Ω 330 Ω 1 k Ω Resistance should be as small as possible to avoid lowering the overcharge detection accuracy due to current consumption. C1 Capacitor For power fluctuation 0.068 μF 0.1 μF 1.0 μF Connect a capacitor of 0.068 μF or higher between VDD pin and VSS pin.*4 R2 Resistor Protection for reverse connection of a charger 300 Ω 2 k Ω 4 k Ω Select as large a resistance as possible to prevent current when a charger is connected in reverse. *1. If the threshold voltage of an FET is low, the FET may not cut the charge current. If an FET with a threshold voltage equal to or higher than the overdischarge detec tion voltage is used, discharging ma y be stopped before overdischarge is detected. *2. If the withstand voltage between the gate and source is lower than the charger voltage, the FET may be destroyed. *3. An accuracy of overcharge detection voltage is guaranteed by R1 = 330 Ω. Connecting resistors with other values worsen the accuracy. In case of connecting larger resistor to R1, the voltage between the VDD pin and VSS pin may exceed the absolute maximum rating because the current flows to the S-82 00A Series from the charger due to reverse connection of charger. Connect a resistor of 150 Ω or more to R1 for ESD protection. *4. When connecting a resistor of 150 Ω or less to R1 or a capacitor of 0.068 μF or less to C1, the S-8200A Series may malfunction when power dissipation is largely fluctuated. *5. When a resistor more than 4 kΩ is connected to R2, the charge current may not be cut. Caution 1. The above constants may be changed without notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant do not guarantee proper operation. Perform thorough evaluation using the actual application to set the constant.

BATTERY PROTECTION IC FOR 1-CELL PACK S-8200A Series Rev.4.0_00 Seiko Instruments Inc. 22  Precautions

• The application conditions for the input voltage, output voltage, and load current should not exceed the package power dissipation.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit.
• SII claims no responsibility for any and all disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party.

BATTERY PROTECTION IC FOR 1-CELL PACK Rev.4.0_00 S-8200A Series Seiko Instruments Inc. 23  Characteristics (Typical Data) 1. Current consumption 1. 1 IOPE vs. Ta 1. 2 IPDN vs. Ta IOPE [μA] −4 0 0 2 55 07 5 85−25 Ta [°C] 0 2 55 07 5 85 Ta [°C] 0.100 0.075 0.050 0.025 1. 3 IOPE vs. VDD V DD [V] IOPE [μA] 02 1 34567

BATTERY PROTECTION IC FOR 1-CELL PACK S-8200A Series Rev.4.0_00 Seiko Instruments Inc. 24 2. Overcharge detection / release voltage, overdischarge detection / release voltage, overcurrent detection voltage, charge overcurrent detection voltage, and delay time 2. 1 VCU vs. Ta 2. 2 VCL vs. Ta 4.26 4.24 4.22 4.20

4.18 VCU [V]

−4 0 0 2 55 07 5 85−25 Ta [°C] 4.07 4.03 4.05 4.01 3.99 3.97

3.95 VCL [V]

−4 0 0 2 55 07 5 85−25 Ta [°C] 2. 3 VDL vs. Ta 2. 4 VDU vs. Ta 2.55 2.51 2.53 2.49 2.47 2.45

2.43 VDL [V]

−4 0 0 2 55 07 5 85−25 Ta [°C] 2.96 2.92 2.88 2.84

2.80 VDU [V]

−4 0 0 2 55 07 5 85−25 Ta [°C] 2. 5 tCU vs. Ta 2. 6 tDL vs. Ta 0.8 0.6 tCU [s] −4 0 0 2 55 07 5 85−25 Ta [°C] 1.0 1.2 1.4 1.6 tDL [ms] −4 0 0 2 55 07 5 85−25 Ta [°C] 110 2. 7 VDIOV vs. Ta 2. 8 tDIOV vs. VDD 0.160 0.155 0.150 0.145

0.140 VDIOV [V]

−4 0 0 2 55 07 5 85−25 Ta [°C] V DD [V] tDIOV [ms]

BATTERY PROTECTION IC FOR 1-CELL PACK Rev.4.0_00 S-8200A Series Seiko Instruments Inc. 25 2. 9 tDIOV vs. Ta 2. 10 VCIOV vs. Ta tDIOV [ms] −4 0 0 2 55 07 5 85−25 Ta [°C] −0.135 −0.140 −0.145 −0.150 −0.155 −0.160 −0.165 VCIOV [V] −4 0 0 2 55 07 5 85−25 Ta [°C] 2. 11 tCIOV vs. VDD 2. 12 tCIOV vs. Ta V DD [V] tCIOV [ms] tCIOV [ms] −4 0 0 2 55 07 5 85−25 Ta [°C] 2. 13 VSHORT vs. Ta 2. 14 tSHORT vs. VDD

0.40 VSHORT [V]

−4 0 0 2 55 07 5 85−25 Ta [°C] 0.45 0.50 0.55 0.60 200 150 250 300 350 400 V DD [V] tSHORT [μs] 2. 15 tSHORT vs. Ta 200 150 −4 0 0 2 55 07 5 85−25 Ta [°C] 250 300 350 400tSHORT [μs]

BATTERY PROTECTION IC FOR 1-CELL PACK S-8200A Series Rev.4.0_00 Seiko Instruments Inc. 26 3. CO pin / DO pin 3. 1 RCOH vs. VCO 3. 2 RCOL vs. VCO RCOH [kΩ] VCO [V] 43210 RCOL [kΩ] VCO [V] 5 4 3 2 1 0 3. 3 RDOH vs. VDO 3. 4 RDOL vs. VDO RDOH [kΩ] VDO [V] 43210 RDOL [kΩ] VDO [V] 2.01.51.00.50

BATTERY PROTECTION IC FOR 1-CELL PACK Rev.4.0_00 S-8200A Series Seiko Instruments Inc. 27  Marking Specifications 1. SOT-23-6 123 465 Top view (1) (2) (3) (4) (1) to (3): Product code (refer to Product name vs. Product code) (4): Lot number Product name vs. Product code Product Name Product Code (1) (2) (3) S-8200AAC-M6T1U V 3 C S-8200AAH-M6T1U V 3 H S-8200AAY-M6T1U V 3 Y S-8200ABE-M6T1U V 4 E S-8200ABM-M6T1U V 4 M S-8200ABX-M6T1U V 4 X S-8200ABZ-M6T1U V 4 Z S-8200ACF-M6T1U S Y F S-8200ACV-M6T1U S Y V S-8200ACW-M6T1U S Y W

BATTERY PROTECTION IC FOR 1-CELL PACK S-8200A Series Rev.4.0_00 Seiko Instruments Inc. 28 2. SNT-6A Top view 13 2 64 5 (1) (2) (3) (4) (5) (6) (1) to (3): Product code (refer to Product name vs. Product code) (4) to (6): Lot number Product name vs. Product code Product Name Product Code (1) (2) (3) S-8200AAA-I6T1U V 3 A S-8200AAB-I6T1U V 3 B S-8200AAC-I6T1U V 3 C S-8200AAD-I6T1U V 3 D S-8200AAF-I6T1U V 3 F S-8200AAG-I6T1U V 3 G S-8200AAH-I6T1U V 3 H S-8200ABA-I6T1U V 4 A S-8200ABI-I6T1U V 4 I S-8200ABK-I6T1U V 4 K S-8200ABL-I6T1U V 4 L S-8200ABM-I6T1U V 4 M S-8200ACN-I6T1U S Y N S-8200ACO-I6T1U S Y O S-8200ACP-I6T1U S Y P S-8200ACQ-I6T1U S Y Q S-8200ACR-I6T1U S Y R

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