S25C010A

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S-25C010A/020A/040A H Series www.sii-ic.com 105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE © Seiko Instruments Inc., 2010-2015 Rev.2.3_00_C Seiko Instruments Inc. 1 The S-25C010A/020A/040A H series devices are high-temperat ure operation SPI serial E 2PROMs for automotive components. The S-25C010A/ 020A/040A H series has the c apacity of 1 K-bit, 2 K-bit, and 4 K-bit, and the organization is 128 words × 8-bit, 256 words × 8- bit, and 512 words × 8-bit, respectively. Page write and sequential read are available. Caution Before using the product in automobile control unit or medical equipment, contact to SII is indispensable.  Features

• Operating voltage range: Read 2.5 V to 5.5 V Write 2.5 V to 5.5 V
• Operation frequency: 6.5 MHz (4.5 V to 5.5 V)
• Write time: 4.0 ms max.
• SPI mode (0, 0) and (1, 1)
• Page write: 16 bytes / page
• Sequential read
• Monitors write to the memory by a status register
• Write protect: Software, Hardware Protect area: 25%, 50%, 100%
• Function to prevent malfunction by monitoring clock pulse
• Write protect function during the low power supply voltage
• CMOS schmitt input ( CS , SCK, SI, WP , HOLD )
• Endurance: 10 6cycles/word*1 (Ta = +85°C) 8 × 105 cycles/word*1 (Ta = +105°C)
• Data retention: 100 years (Ta = +25°C) 50 years (Ta = +105°C)
• Memory capacitance: S-25C010A 1 K-bit S-25C020A 2 K-bit S-25C040A 4 K-bit
• Initial delivery state: FFh, BP1 = 0, BP0 = 0
• Operation temperature range: Ta = −40°C to +105°C
• Lead-free (Sn 100%), halogen-free
• AEC-Q100 qualified*3 *1. For each address (Word: 8-bit) *2. Refer to “ Product Name Structure” for details. *3. Contact our sales office for details.  Packages
• 8-Pin SOP (JEDEC)
• 8-Pin TSSOP

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE S-25C010A/020A/040A H Series Rev.2.3_00_C Seiko Instruments Inc. 2  Pin Configurations 8-Pin SOP (JEDEC) Top view Table 1 SO CS 1 SCKWP GND SI HOLD VCC Figure 1 S-25C010A0H-J8T2UD S-25C020A0H-J8T2UD S-25C040A0H-J8T2UD Pin No. Symbol Description

1 CS *1 Chip select input

2 SO Serial data output

3 WP *1 Write protect input

4 GND Ground

5 SI*1 Serial data input

6 SCK*1 Serial clock input

7 HOLD *1 Hold input

8 VCC Power supply

*1. Do not use it in high impedance. Remark See Dimensions for details of the package drawings. 8-Pin TSSOP Top view Table 2 SO CS WP GND SCK SI HOLD VCC1 Figure 2 S-25C010A0H-T8T2UD S-25C020A0H-T8T2UD S-25C040A0H-T8T2UD Pin No. Symbol Description *1. Do not use it in high impedance.

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE Rev.2.3_00_C S-25C010A/020A/040A H Series Seiko Instruments Inc. 3  Block Diagram Mode Decoder Status RegisterAddress Register Data Register WP CS HOLD SI SCK SO VCC GND Memory Cell Array Status Memory Cell Array Voltage Detector Read Circuit Clock Counter Y Decoder X Decoder Input Control Circuit Output Control Circuit Step-up Circuit Page Latch Figure 3

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE S-25C010A/020A/040A H Series Rev.2.3_00_C Seiko Instruments Inc. 4  AEC-Q100 Qualified This IC supports AEC-Q100 for operation temperature grade 2. Contact our sales office for details of AEC-Q100 reliability specification.  Absolute Maximum Ratings Table 3 Item Symbol Absolute Maximum Rating Unit Power supply voltage VCC −0.3 to +7.0 V Input voltage VIN −0.3 to +7.0 V Output voltage VOUT −0.3 to VCC + 0.3 V Operating ambient temperature T opr −40 to +105 °C Storage temperature Tstg −65 to +150 °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions.  Recommended Operating Conditions Table 4 Item Symbol Condition Ta = −40°C to +105°C Unit Min. Max. Power supply voltage VCC Read operation 2.5 5.5 V Write operation 2.5 5.5 V High level input voltage VIH VCC = 2.5 V to 5.5 V 0.7 × VCC V CC + 1.0 V Low level input voltage VIL VCC = 2.5 V to 5.5 V −0.3 0.3 × VCC V  Pin Capacitance Table 5 (Ta = +25°C, f = 1.0 MHz, VCC = 5 V) Item Symbol Condition Min. Max. Unit Input capacitance CIN VIN = 0 V ( CS , SCK, SI, WP , HOLD ) − 8 pF Output capacitance C OUT VOUT = 0 V (SO) − 10 pF  Endurance Table 6 Item Symbol Operating Ambient Temperature Min. Max. Unit Endurance N W −40°C to +85°C 10 6 − cycles / word*1 −40°C to +105°C 8 × 105 − cycles / word*1 *1. For each address (Word: 8 bits)  Data Retention Table 7 Item Symbol Operation Ambient Temperature Min. Max. Unit Data retention − +25°C 100 − year −40°C to +105°C 50 − year

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE Rev.2.3_00_C S-25C010A/020A/040A H Series Seiko Instruments Inc. 5  DC Electrical Characteristics Table 8 Item Symbol Condition Ta = −40°C to +105°C UnitVCC = 2.5 V to 3.0 V fSCK = 3.5 MHz VCC = 3.0 V to 4.5 V fSCK = 5.0 MHz VCC = 4.5 V to 5.5 V fSCK = 6.5 MHz Current consumption (READ) I CC1 No load at SO pin − 1.5 − 2.0 − 2.5 mA Table 9 Item Symbol Condition Ta = −40°C to +105°C UnitVCC = 2.5 V to 3.0 V fSCK = 3.5 MHz VCC = 3.0 V to 4.5 V fSCK = 5.0 MHz VCC = 4.5 V to 5.5 V fSCK = 6.5 MHz Current consumption (WRITE) I CC2 No load at SO pin − 2.0 − 2.5 − 3.0 mA Table 10 Item Symbol Condition Ta = −40°C to +105°C UnitVCC = 2.5 V to 4.5 V V CC = 4.5 V to 5.5 V Min. Max. Min. Max. Standby current consumption ISB CS = VCC, SO = Open Other inputs are V CC or GND − 8.0 − 10.0 μA Input leakage current ILI VIN = GND to VCC − 2.0 − 2.0 μA Output leakage current ILO VOUT = GND to VCC − 2.0 − 2.0 μA Low level output voltage VOL1 IOL = 2.0 mA − − − 0.4 V VOL2 IOL = 1.5 mA − 0.4 − 0.4 V High level output voltage VOH1 IOH = −2.0 mA − − 0.8 × VCC − V VOH2 IOH = −0.4 mA 0.8 × VCC − 0.8 × VCC − V

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE S-25C010A/020A/040A H Series Rev.2.3_00_C Seiko Instruments Inc. 6  AC Electrical Characteristics Table 11 Measurement Conditions Input pulse voltage 0.2 × VCC to 0.8 × VCC Output reference voltage 0.5 × VCC Output load 100 pF Table 12 Item Symbol Ta = −40°C to +105°C SCK clock frequency f SCK − 3.5 − 5.0 − 6.5 MHz CS setup time during CS falling tCSS.CL 90 − 90 − 65 − ns CS setup time during CS rising tCSS.CH 90 − 90 − 65 − ns CS deselect time tCDS 160 − 140 − 110 − ns CS hold time during CS falling tCSH.CL 90 − 90 − 65 − ns CS hold time during CS rising tCSH.CH 90 − 90 − 65 − ns SCK clock time “H” *1 tHIGH 125 − 95 − 65 − ns SCK clock time “L” *1 tLOW 125 − 95 − 65 − ns Rising time of SCK clock *2 tRSK − 1 − 1 − 1 μs Falling time of SCK clock *2 tFSK − 1 − 1 − 1 μs SI data input setup time t DS 20 − 20 − 20 − ns SI data input hold time t DH 30 − 30 − 30 − ns SCK “L” hold time during HOLD rising tSKH.HH 70 − 70 − 45 − ns SCK “L” hold time during HOLD falling tSKH.HL 40 − 40 − 30 − ns SCK “L” setup time during HOLD falling tSKS.HL 0 − 0 − 0 − ns SCK “L” setup time during HOLD rising tSKS.HH 0 − 0 − 0 − ns Disable time of SO output *2 tOZ − 100 − 100 − 75 ns Delay time of SO output t OD − 120 − 90 − 60 ns Hold time of SO output t OH 0 − 0 − 0 − ns Rising time of SO output *2 tRO − 80 − 70 − 50 ns Falling time of SO output *2 tFO − 80 − 70 − 50 ns Disable time of SO output during HOLD falling *2 tOZ.HL − 100 − 100 − 75 ns Delay time of SO output during HOLD rising *2 tOD.HH − 80 − 80 − 60 ns WP setup time tWS1 0 − 0 − 0 − ns WP hold time tWH1 0 − 0 − 0 − ns WP release / setup time tWS2 0 − 0 − 0 − ns WP release / hold time tWH2 150 − 150 − 100 − ns *1. The clock cycle of the SCK clock (frequency f SCK) is 1/fSCK μs. This clock cycle is determined by a combination of several AC characteristics. Note that the clock cycle cannot be set as (1/fSCK) = tLOW (Min.) + tHIGH (Min.) by minimizing the SCK clock cycle time. *2. These are values of sample and not 100% tested.

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE Rev.2.3_00_C S-25C010A/020A/040A H Series Seiko Instruments Inc. 9  Pin Function 1. CS (Chip select input) pin This is an input pin to set a chip in the select status. In the “H” input level, the device is in the non-select status and its output is high impedance. The devic e is in standby as long as it is not in Write inside. The device goes in active by setting the chip select to “L”. Input any instruction code after power-on and a falling of chip select. 2. SI (Serial data input) pin This pin is to input serial data. This pin receives an instruction code, an address and Write data. This pin latches data at rising edge of serial clock. 3. SO (Serial data output) pin This pin is to output serial data. The data output changes at falling edge of serial clock. 4. SCK (Serial clock input) pin This is a clock input pin to set the timing of serial data. An instruction code, an address and Write data are received at a rising edge of clock. Data is output at falling edge of clock. 5. WP (Write protect input) pin This is an input pin to protect memory data when Write instruction (WRITE, WRSR) is being input. By setting this pin to “L”, the WEL bit in the status register is set to “L”. Therefore S-25C010A/020A/040A does not Write to the E2PROM, however, it accepts other instructions. Fix this pin “H” or “L” not to set it in the floating state. Refer to “ Protect Operation” for details. 6. HOLD (HOLD input) pin This pin is used to pause serial communications without setting the device in the non-select status. In the hold status, the serial output goes in high impedance, t he serial input and the serial clock go in “Don’t care”. During the hold operation, be sure to set the device in active by setting the chip select ( CS pin) to “L”. Refer to “ Hold Operation” for details.  Initial Delivery State Initial delivery state of all addresses is “FFh”. Moreover, initial delivery stat e of the status register nonvolatile memory is as follows.

• BP1 = 0
• BP0 = 0

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE S-25C010A/020A/040A H Series Rev.2.3_00_C Seiko Instruments Inc. 10  Instruction Setting Tables 14 and 15 are the lists of instructions for the S-25C010A/020A/040A. The inst ruction is able to be input by changing the CS pin “H” to “L”. Input the instruction in the MSB first. Each instruct ion code is organized with 1-byte as shown below. If the S-25C010A/020A/040A re ceives any invalid instruction code, the device goes in the non-select status. 1. S-25C010A/020A Table 14 Instruction Set Instruction Operation Instruction code Address Data SCK input clock 1 to 8 SCK input clock 9 to 16 SCK input clock 17 to 24 WREN Write enable 0000 X110 − − WRDI Write disable 0000 X100 − − RDSR Read the status register 0000 X101 b7 to b0 output*1 − WRSR Write in the status r egister 0000 X001 b7 to b0 input − READ Read memory data 0000 X011 A7*2 to A0 D7 to D0 output *3 WRITE Write memory data 0000 X010 A7*2 to A0 D7 to D0 input *1. Sequential data reading is possible. *2. In the S-25C010A, A7 = Don’t care because the address range is A6 to A0. *3. After outputting data in the specified address, data in the following address is output. Remark X = Don’t care. 2. S-25C040A Table 15 Instruction Set Instruction Operation Instruction code Address Data SCK input clock 1 to 8 SCK input clock 9 to 16 SCK input clock 17 to 24 WREN Write enable 0000 X110 − − WRDI Write disable 0000 X100 − − RDSR Read the status register 0000 X101 b7 to b0 output*1 − WRSR Write in the status r egister 0000 X001 b7 to b0 input − READ Read memory data 0000 [A8*2]011 A7 to A0 D7 to D0 output*3 WRITE Write memory data 0000 [A8*2]010 A7 to A0 D7 to D0 input *1. Sequential data reading is possible. *2. In the S-25C040A, assign bit A8 in the address into the fifth bit in an instruction code. *3. After outputting data in the specified address, data in the following address is output. Remark X = Don’t care.

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE Rev.2.3_00_C S-25C010A/020A/040A H Series Seiko Instruments Inc. 11  Operation 1. Status register The status register’s organization is below. The status register can Write and Read by a specific instruction. b7 b6 BP1 BP0 WEL WIP Block Protect Write Enable Latch Write In Progress Figure 9 Organization of Status Register The status/control bits of the status register are as follows.

1.1 BP1, BP0 (b3, b2) : Block protect

Bit BP1 and BP0 are composed of the nonvolatile bit. The ar ea size of Software Protect with respect to WRITE instructions is defined by the BP1 and BP0 bits. Rewriting these bits is possible by the WRSR instruction. To protect the memory area against the WRITE instruction, set either or both of bit BP1 and BP0 to “1”. Rewriting bit BP1 and BP0 is possible unless they are in Hardware Protect mode. Refer to “ Protect Operation” for details of “Block Protect”.

1.2 WEL (b1) : Write enable latch

Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL is “1”, this is the status that Write Enable Latch is set. If bit WEL is “0”, Write Enable Latch is in reset, so that the S- 25C010A/020A/040A does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;

• The power supply voltage is dropping
• Power-on
• After performing WRDI
• After the Write operation by the WRSR instruction
• After the Write operation by the WRITE instruction
• After setting the WP pin to “L”

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE S-25C010A/020A/040A H Series Rev.2.3_00_C Seiko Instruments Inc. 12

1.3 WIP (b0) : Write in progress

Bit WIP is a Read Only bit. It indicates whether the inter nal memory is in the Write operation or not by the WRITE or WRSR instruction. Bit WIP is “1” during the Write operation but “0” during any other status. Figure 10 shows the usage example. 1111 1111 1111 00 B P B P B P B P B tPR P B P WEL, WIP WEL, WIP WEL, WIP CS SI SO RDSR instruction RDSR inst ruction RDSR instruction RDSR RDSR RDSR 11 11 WRITE or WRSR instruction D2 D1D0 Figure 10 Usage Example of WEL, WIP Bits during Write

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE Rev.2.3_00_C S-25C010A/020A/040A H Series Seiko Instruments Inc. 13 2. Write enable (WREN) Before writing data (WRITE and WRSR), be sure to set bit Write Enable Latch (WEL). This instruction is to set bit WEL. Its operation is below. After selecting the device by the chip select ( CS ), input the instruction code from serial data input (SI). To set bit WEL, set the device in the non-select status by CS at the 8th clock of the serial clock (SCK). To cancel the WREN instruction, input the clock different from a specified value (n = 8 clock) while CS is in “L”. SO SCK WP CS SI Instruction High-Z 12345678 High X Remark X = Don’t care. Figure 11 WREN Operation

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE S-25C010A/020A/040A H Series Rev.2.3_00_C Seiko Instruments Inc. 14 3. Write disable (WRDI) The WRDI instruction is one of ways to reset bit Write Enable Latch (WEL). After selecting the device by the chip select ( CS ), input the instruction code from serial data input (SI). To reset bit WEL, set the device in the non-select status by CS at the 8th clock of the serial clock. To cancel the WRDI instruction, input the clock different from a specified value (n = 8 clock) while CS is in “L”. Bit WEL is reset after the operations shown below.

• The power supply voltage is dropping
• Power-on
• After performing WRDI
• After the completion of Write operation by the WRSR instruction
• After the completion of Write operation by the WRITE instruction
• After setting the WP pin to “L” SO SCK WP CS SI Instruction High-Z 12345678 High / Low X Remark X = Don’t care. Figure 12 WRDI Operation

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE Rev.2.3_00_C S-25C010A/020A/040A H Series Seiko Instruments Inc. 15 4. Read the status register (RDSR) Reading data in the status regi ster is possible by the RDSR instruction. During the Write operation, it is possible to confirm the progress by checking bit WIP. Set the chip select ( CS ) “L” first. After that, input the instruction code from serial data input (SI). The status of bit in the status register is output from serial data output (SO). Sequent ial Read is available for the status register. To stop the Read cycle, set CS to “H”. It is possible to read the status register always. The bits in it are valid and can be read by RDSR even in the Write cycle. The 2 bits WEL and WIP are updated during the write cy cle. The updated nonvolatile bits BP1 and BP0 can be acquired by performing a new RDSR instruction after verifying the completion of the write cycle. b7, b6, b5, and b4 are “1” when they are read by the RDSR instruction. SO SCK WP CS SI Instruction High-Z 12345678 High / Low 9 1 01 11 21 31 41 51 6 Outputs Data in the Status Register b7 b6 b5 b7 b0b1b2b3b4 X Remark X = Don’t care. Figure 13 RDSR Operation

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE S-25C010A/020A/040A H Series Rev.2.3_00_C Seiko Instruments Inc. 16 5. Write in the status register (WRSR) The values of status register (BP1, BP0) can be rewritten by inputting the WRSR instruction. But b7, b6, b5, b4, b1, b0 of status register cannot be rewritten. b7 to b4 are always “1” when reading the status register. Before inputting the WRSR instruction, set bit WEL by the WREN instruction. The operation of WRSR is shown below. Set the chip select ( CS ) “L” first. After that, input the instruction c ode and data from serial data input (SI). To start WRSR Write (tPR), set the chip select ( CS ) to “H” after inputting data or before inputting a rising of the next serial clock. It is possible to confirm the operation st atus by reading the value of bit WIP dur ing WRSR Write. Bit WIP is “1” during Write, “0” during any other status. Bit WEL is reset when Write is completed. With the WRSR instruction, the val ues of BP1 and BP0; which determine the area size the users can handle as the Read Only memory; can be changed. When signal WP is “L”, however, the WRSR instruction is not be performed (Refer to “ Protect Operation”). Bits BP1 and BP0 keep the value which is the one prior to the WRSR instruction during the WRSR instruction. The newly updated value is changed when the WRSR instruction has completed. To cancel the WRSR instruction, input the clock different from a specified value (n = 16 clock) while CS is in “L”. SO SCK WP CS SI Instruction High-Z 12345678 High 9 1 01 11 21 31 41 51 6 Inputs Data in the Status Register b7 b6 b5 b0 b1b2b3b4X Remark X = Don’t care. Figure 14 WRSR Operation

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE Rev.2.3_00_C S-25C010A/020A/040A H Series Seiko Instruments Inc. 17 6. Read memory data (READ) The READ operation is shown below. I nput the instruction code and the address from serial data input (SI) after inputting “L” to the chip select ( CS ). The input address is loaded to the internal address counter, and data in the address is output from the serial data output (SO). Next, by inputting the serial clock (SCK) keeping the chip select ( CS ) in “L”, the address is automatically incremented so that data in the following address is sequentially output. The address counter rolls over to the first address by increment in the last address. To finish the Read cycle, set CS to “H”. It is possible to raise the chip select always during the cycle. During Write, the READ instruction code is not be accepted or operated. SO SCK WP CS SI Instruction High-Z 12345678 High / Low 9 1 01 1 1 31 41 51 61 7 8-bit Address A7*1 A6 A5 A0 A1A2A3 Outputs the First Byte D4D5D6D7 18 19 20 21 22 23 24 D0D1D2D3 D7 Outputs the Second X A4 *1 In the S-25C010A, A7 = Don’t care because the address range is A6 to A0. Remark X = Don’t care. Figure 15 READ Operation (S-25C010A/020A)

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE S-25C010A/020A/040A H Series Rev.2.3_00_C Seiko Instruments Inc. 18 SO SCK WP CS SI Instruction High-Z 12345678 High / Low 9 1 01 1 1 31 41 51 61 7 8-bit Address A7 A6 A5 A0 A1A2A3 Outputs the First Byte D4D5D6D7 18 19 20 21 22 23 24 D0D1D2D3 D7 Outputs the Second A8*1 A4 *1 In the S-25C040A, assign bit A8 in the address into the fifth bit in an instruction code. Figure 16 READ Operation (S-25C040A)

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE Rev.2.3_00_C S-25C010A/020A/040A H Series Seiko Instruments Inc. 19 7. Write memory data (WRITE) Figures 17 and 18 show the timing charts when inputting 1-byte data. Input the instruction code, the address and data from serial data input (SI) after inputting “L” to the chip select (CS ). To start WRITE (t PR), set the chip select ( CS ) to “H” after inputting data or before inputting a rising of the next serial clock. Bit WIP and WEL are reset to “0” when Write has completed. The S-25C010A/020A/040A can Page Write of 16 bytes. Its function to trans mit data is as same as Byte Write basically, but it operates Page Write by receiving sequential 8-bit Write dat a as much data as page size has. Input the instruction code, the address and data from serial data input (SI) after inputting “L” in CS , as the WRITE operation (page) shown in Figures 19 and 20. Input the next data while keeping CS in “L”. After that, repeat inputting data of 8- bit sequentially. At the end, by setting CS to “H”, the WRITE operation starts (tPR). 4 of the lower bits in the address are automatically incremented every time when receiving Write data of 8-bit. Thus, even if Write data exceeds 16 bytes, t he higher bits in the address do not change. And lower 4 bits in the address roll over so that Write data which is previously input is overwritten. These are cases when the WRITE instruction is not accepted or operated.

• Bit WEL is not set to “1” (not set to “1” beforehand immediately before the WRITE instruction)
• During Write
• The address to be written is in the protect area by BP1 and BP0.
• The WP signal is in “L”. To cancel the WRITE instruction, input the clock different from a specified value (n = 16 + m × 8 clocks) while CS is in “L”.

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE S-25C010A/020A/040A H Series Rev.2.3_00_C Seiko Instruments Inc. 22  Protect Operation Table 16 shows the block settings of Write protect. Setting value in Protect Bits (BP1, BP0) in the status register protect data in the area of all/50%/25% of the memory address. Setting signal WP to “L” provides the following settings.

• Write protect for the WRITE, WRSR instructions
• Reset bit WEL Figures 7 and 8 show the Valid timing in Write protect and Invalid timing in Write protect. Table 16 Block Settings of Write Protect Status Register Area of Write Protect Address of Write protect block BP1 BP0 S-25C040A S-25C020A S-25C010A 0 0 0% None None None 0 1 25% 180h to 1FFh C0h to FFh 60h to 7Fh 1 0 50% 100h to 1FFh 80h to FFh 40h to 7Fh 1 1 100% 000h to 1FFh 00h to FFh 00h to 7Fh

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE S-25C010A/020A/040A H Series Rev.2.3_00_C Seiko Instruments Inc. 26  Precaution

• Do not apply an electrostatic discharge to this IC that ex ceeds the performance ratings of the built-in electrostatic protection circuit.
• SII claims no responsibility for any and all disputes arisi ng out of or in connection wi th any infringement of the products including this IC upon patents owned by a third party.  Product Name Structure 1. Product name S-25CxxxA 0H − xxxx U D Environmental code U: Lead-free (Sn 100%), halogen-free Product name S-25C010A : 1 K-bit S-25C020A : 2 K-bit S-25C040A : 4 K-bit Fixed Package name (abbreviation) and IC packing specification J8T2: 8-Pin SOP (JEDEC), Tape T8T2: 8-Pin TSSOP, Tape Burn-in specification D: Wafer level burn-in Remark Please contact our sales office for products with product name structure ot her than those specified above. 2. Package Package name Drawing code Package Tape Reel 8-Pin SOP (JEDEC) FJ008-A-P-SD FJ008-D-C-SD FJ008-D-R-S1 8-Pin TSSOP FT008-A-P-SD FT008-E-C-SD FT008-E-R-S1

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