S25A640

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S-25A640A, S-25A640B www.sii-ic.com FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM © Seiko Instruments Inc., 2008-2014 Rev.3.2_00 Seiko Instruments Inc. 1 This IC is a SPI serial E2PROM which operates under the high temperature, at high speed, with the wide range operation for automotive components. This IC has the capacity of 64 K-bit and the organization of 8192 words × 8-bit. Page write and Sequential read are available. Caution Before using the product in automobile control uni t or medical equipment, contact to SII is indispensable.  Features

• Operating voltage range Read: 2.5 V ~ 5.5 V Write: 2.5 V ~ 5.5 V
• Operation frequency S-25A640A: 5.0 MHz max. S-25A640B: 6.5 MHz max.
• Write time S-25A640A: 4.0 ms max. S-25A640B: 5.0 ms max.
• SPI mode (0, 0) and (1, 1)
• Page write: 32 bytes / page
• Sequential read
• Write protect: Software, Hardware Protect area: 25%, 50%, 100%
• Monitoring of a write memory state by the status register
• Function to prevent malfunction by monitoring clock pulse
• Write protect function duri ng the low power supply voltage
• CMOS schmitt input ( CS , SCK, SI, WP , HOLD )
• Endurance *1 S-25A640A: 106 cycle / word*2 (Ta = +25°C) 5 × 105 cycle / word*2 (Ta = +125°C) S-25A640B: 10 6 cycle / word*2 (Ta = +25°C) 3 × 105 cycle / word*2 (Ta = +125°C)
• Data retention: 100 years (Ta = +25°C) 50 years (Ta = +125°C)
• Memory capacity: 64 K-bit
• Initial delivery state: FFh, SRWD = 0, BP1 = 0, BP0 = 0
• Burn-in specification: Wafer level burn-in
• Operation temper ature range: Ta = −40°C to +125°C
• Lead-free (Sn 100%), halogen-free
• AEC-Q100 qualified *4 *1. Refer to " Endurance" for details. *2. For each address (Word: 8-bit) *3. Refer to "  Product Name Structure" for details. *4. Contact our sales office for details.  Packages
• 8-Pin SOP (JEDEC)
• 8-Pin TSSOP
• TMSOP-8 Remark Refer to "3. Product name list " in " Product Name Structure" for details of package and product.

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A640A, S-25A640B Rev.3.2_00 Seiko Instruments Inc. 2  Block Diagram Mode Decoder Status RegisterAddress Register Data Register WP CS HOLD SI SCK SO VCC GND Memory Cell Array Status Memory Cell Array Voltage Detector Read Circuit Clock Counter Y Decoder X Decoder Input Control Circuit Output Control Circuit Step-up Circuit Page Latch Figure 1  AEC-Q100 Qualified This IC supports AEC-Q100 for operation temperature grade 1. Contact our sales office for details of AEC-Q100 reliability specification.  Product Name Structure 1. Product name 1. 1 S-25A640A S-25A640A 0A − J8T2 U D Fixed Environmental code U: Lead-free (Sn 100%), halogen-free Package name (abbreviation) and IC packing specification*1 J8T2: 8-Pin SOP (JEDEC), Tape Fixed Product name S-25A640A: 64 K-bit

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM Rev.3.2_00 S-25A640A, S-25A640B Seiko Instruments Inc. 3 1. 2 S-25A640B S-25A640B 0A − xxxx U 3 Fixed Environmental code U: Lead-free (Sn 100%), halogen-free Package name (abbreviation) and IC packing specification*1 J8T2: 8-Pin SOP (JEDEC), Tape T8T2: 8-Pin TSSOP, Tape K8T2: TMSOP-8, Tape Fixed Product name S-25A640B: 64 K-bit *1. Refer to the tape drawing. Remark This IC is wafer level burn-in specification. 2. Packages Table 1 Package Drawing Codes Package Name Dimension Tape Reel 8-Pin SOP (JEDEC) FJ008-A-P-SD FJ008-D-C-SD FJ008-D-R-S2 8-Pin TSSOP FT008-A-P-SD FT008-E-C-SD FT008-E-R-S2 TMSOP-8 FM008-A-P-SD FM008-A-C-SD FM008-A-R-SD 3. Product name list Table 2 Product Name Capacity Package Quantity S-25A640A0A-J8T2UD 64 K bit 8-Pin SOP (JEDEC) 2000 pcs / reel S-25A640B0A-J8T2U3 64 K bit 8-Pin SOP (JEDEC) 4000 pcs / reel S-25A640B0A-T8T2U3 64 K bit 8-Pin TSSOP 4000 pcs / reel S-25A640B0A-K8T2U3 64 K bit TMSOP-8 4000 pcs / reel Remark 1. Please contact our sales office for products with product name structure other than those specified above. 2. This IC is wafer level burn-in specification.

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A640A, S-25A640B Rev.3.2_00 Seiko Instruments Inc. 4  Pin Configurations 1. 8-Pin SOP (JEDEC) Top view Figure 2 Table 3 Pin No. Symbol Description

1 CS *1 Chip select input

2 SO Serial data output

3 WP *1 Write protect input

4 GND Ground

5 SI*1 Serial data input

6 SCK*1 Serial clock input

7 HOLD *1 Hold input

8 VCC Power supply

1. 8-Pin TSSOP Top view Figure 3 Table 4 Pin No. Symbol Description
2. TMSOP-8 Top view Figure 4 Table 5 Pin No. Symbol Description

*1. Do not use it in "High-Z".

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM Rev.3.2_00 S-25A640A, S-25A640B Seiko Instruments Inc. 5  Absolute Maximum Ratings Table 6 Item Symbol Absolute Maximum Rating Unit S-25A640A S-25A640B Power supply voltage VCC −0.3 to +7.0 −0.3 to +6.5 V Input voltage VIN −0.3 to +7.0 −0.3 to +6.5 V Output voltage VOUT −0.3 to VCC + 0.3 V Operation ambient temperature T opr −40 to +125 °C Storage temperature Tstg −65 to +150 °C Caution The absolute maximum ratings are rated values exceeding whic h the product could suffer physical damage. These values must therefore not be exceeded under any conditions.  Recommended Operating Conditions Table 7 Item Symbol Condition Ta = −40°C to +125°C Unit Min. Max. Power supply voltage V CC Read 2.5 5.5 V Write 2.5 5.5 V High level input voltage V IH V CC = 2.5 V to 5.5 V 0.7 × VCC V CC + 1.0 V Low level input voltage V IL V CC = 2.5 V to 5.5 V −0.3 0.3 × VCC V  Pin Capacitance Table 8 (Ta = +25°C, f = 1.0 MHz, VCC = 5.0 V) Item Symbol Condition Min. Max. Unit Input capacitance C IN VIN = 0 V ( CS , SCK, SI, WP , HOLD ) － 8 pF Output capacitance C OUT V OUT = 0 V (SO) － 10 pF  Endurance 1. S-25A640A Table 9 Item Symbol Operation Ambient Temperature Min. Max. Unit Endurance N W Ta = −40°C to +85°C 106 － cycle / word*1 Ta = −40°C to +105°C 8 × 105 － cycle / word*1 Ta = −40°C to +125°C 5 × 105 － cycle / word*1 *1. For each address (Word: 8-bit) 2. S-25A640B Table 10 Item Symbol Operation Ambient Temperature Min. Max. Unit Endurance N W Ta = +25°C 106 － cycle / word*1 Ta = −40°C to +85°C 7 × 105 － cycle / word*1 Ta = −40°C to +105°C 5 × 105 － cycle / word*1 Ta = −40°C to +125°C 3 × 105 － cycle / word*1 *1. For each address (Word: 8-bit)  Data Retention Table 11 Item Symbol Operation Ambient Temperature Min. Max. Unit Data retention － Ta = +25°C 100 － year Ta = −40°C to +125°C 50 － year

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A640A, S-25A640B Rev.3.2_00 Seiko Instruments Inc. 6  DC Electrical Characteristics 1. S-25A640A Table 12 Item Symbol Condition Ta = −40°C to +125°C UnitVCC = 2.5 V to 3.0 V fSCK = 2.5 MHz VCC = 3.0 V to 4.5 V fSCK = 3.5 MHz VCC = 4.5 V to 5.5 V fSCK = 5.0 MHz Current consumption (read) ICC1 No load at SO pin － 1.5 － 2.0 － 2.5 mA Table 13 Item Symbol Condition Ta = −40°C to +125°C UnitVCC = 2.5 V to 3.0 V fSCK = 2.5 MHz VCC = 3.0 V to 4.5 V fSCK = 3.5 MHz VCC = 4.5 V to 5.5 V fSCK = 5.0 MHz Current consumption (write) I CC2 No load at SO pin － 4.0 － 5.0 － 6.0 mA Table 14 Item Symbol Condition Ta = −40°C to +125°C UnitVCC = 2.5 V to 4.5 V V CC = 4.5 V to 5.5 V Min. Max. Min. Max. Standby current consumption I SB CS = V CC, SO = Open Other inputs are V CC or GND － 8.0 － 10.0 μA Input leakage current I LI V IN = GND to VCC － 2.0 － 2.0 μA Output leakage current I LO V OUT = GND to VCC － 2.0 － 2.0 μA Low level output voltage V OL1 I OL = 2.0 mA － － － 0.4 V VOL2 I OL = 1.5 mA － 0.4 － 0.4 V High level output voltage V OH1 I OH = −2.0 mA － － 0.8 × VCC － V VOH2 I OH = −0.4 mA 0.8 × VCC － 0.8 × VCC － V

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM Rev.3.2_00 S-25A640A, S-25A640B Seiko Instruments Inc. 7 2. S-25A640B Table 15 Item Symbol Condition Ta = −40°C to +125°C UnitVCC = 2.5 V to 4.5 V fSCK = 6.5 MHz VCC = 4.5 V to 5.5 V fSCK = 6.5 MHz Min. Max. Min. Max. Current consumption (read) ICC1 No load at SO pin － 2.0 － 2.5 mA Table 16 Item Symbol Condition Ta = −40°C to +125°C UnitVCC = 2.5 V to 5.5 V fSCK = 6.5 MHz Min. Max. Current consumption (write) I CC2 No load at SO pin － 4.0 mA Table 17 Item Symbol Condition Ta = −40°C to +125°C UnitVCC = 2.5 V to 4.5 V V CC = 4.5 V to 5.5 V Min. Max. Min. Max. Standby current consumption I SB CS = V CC, SO = Open Other inputs are V CC or GND － 8.0 － 10.0 μA Input leakage current I LI V IN = GND to VCC － 2.0 － 2.0 μA Output leakage current I LO V OUT = GND to VCC － 2.0 － 2.0 μA Low level output voltage V OL1 I OL = 2.0 mA － － － 0.4 V VOL2 I OL = 1.5 mA － 0.4 － 0.4 V High level output voltage V OH1 I OH = −2.0 mA － － 0.8 × VCC － V VOH2 I OH = −0.4 mA 0.8 × VCC － 0.8 × VCC － V

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A640A, S-25A640B Rev.3.2_00 Seiko Instruments Inc. 8  AC Electrical Characteristics 1. S-25A640A Table 18 Measurement Conditions Input pulse voltage 0.2 × VCC to 0.8 × VCC Output reference voltage 0.5 × VCC Output load 100 pF Table 19 Item Symbol Ta = −40°C to +125°C SCK clock frequency fSCK － 2.5 － 3.5 － 5.0 MHz CS setup time during CS falling tCSS.CL 120 － 90 － 90 － ns CS setup time during CS rising tCSS.CH 120 － 90 － 90 － ns CS deselect time tCDS 210 － 160 － 140 － ns CS hold time during CS falling tCSH.CL 120 － 90 － 90 － ns CS hold time during CS rising tCSH.CH 120 － 90 － 90 － ns SCK clock time "H"*1 tHIGH 160 － 125 － 95 － ns SCK clock time "L"*1 tLOW 160 － 125 － 95 － ns Rising time of SCK clock*2 tRSK － 1 － 1 － 1 μs Falling time of SCK clock*2 tFSK － 1 － 1 － 1 μs SI data input setup time tDS 30 － 20 － 20 － ns SI data input hold time tDH 40 － 30 － 30 － ns SCK "L" hold time during HOLD rising tSKH.HH 90 － 70 － 70 － ns SCK "L" hold time during HOLD falling tSKH.HL 50 － 40 － 40 － ns SCK "L" setup time during HOLD falling tSKS.HL 0 － 0 － 0 － ns SCK "L" setup time during HOLD rising tSKS.HH 0 － 0 － 0 － ns Disable time of SO output*2 tOZ － 130 － 100 － 100 ns Delay time of SO output tOD － 160 － 120 － 90 ns Hold time of SO output tOH 0 － 0 － 0 － ns Rising time of SO output*2 tRO － 110 － 80 － 80 ns Falling time of SO output*2 tFO － 110 － 80 － 80 ns Disable time of SO output during HOLD falling*2 tOZ.HL － 130 － 100 － 100 ns Delay time of SO output during HOLD rising*2 tOD.HH － 110 － 80 － 80 ns WP setup time tWS1 0 － 0 － 0 － ns WP hold time tWH1 0 － 0 － 0 － ns WP release / setup time tWS2 0 － 0 － 0 － ns WP release / hold time tWH2 200 － 150 － 150 － ns *1. The clock cycle of the SCK clock (frequency f SCK) is 1 / f SCK μs. This clock cycle is determined by a combination of several AC characteristics. Note that the clock cycle cannot be set as (1 / f SCK) = t LOW (min.) + t HIGH (min.) by minimizing the SCK clock cycle time. *2. These are values of sample and not 100% tested. Table 20 Item Symbol Ta = −40°C to +125°C Unit VCC = 2.5 V to 5.5 V Min. Max. Write time tPR － 4.0 ms

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM Rev.3.2_00 S-25A640A, S-25A640B Seiko Instruments Inc. 9 2. S-25A640B Table 21 Measurement Conditions Input pulse voltage 0.2 × VCC to 0.8 × VCC Output reference voltage 0.5 × VCC Output load 100 pF Table 22 Item Symbol Ta = −40°C to +125°C Unit VCC = 2.5 V to 5.5 V Min. Max. SCK clock frequency fSCK － 6.5 MHz CS setup time during CS falling tCSS.CL 65 － ns CS setup time during CS rising tCSS.CH 65 － ns CS deselect time tCDS 65 － ns CS hold time during CS falling tCSH.CL 65 － ns CS hold time during CS rising tCSH.CH 65 － ns SCK clock time "H" *1 tHIGH 65 － ns SCK clock time "L"*1 tLOW 65 － ns Rising time of SCK clock*2 tRSK － 1 μs Falling time of SCK clock*2 tFSK － 1 μs SI data input setup time tDS 15 － ns SI data input hold time tDH 20 － ns SCK "L" hold time during HOLD rising tSKH.HH 45 － ns SCK "L" hold time during HOLD falling tSKH.HL 30 － ns SCK "L" setup time during HOLD falling tSKS.HL 0 － ns SCK "L" setup time during HOLD rising tSKS.HH 0 － ns Disable time of SO output*2 tOZ － 75 ns Delay time of SO output tOD － 50 ns Hold time of SO output tOH 0 － ns Rising time of SO output*2 tRO － 30 ns Falling time of SO output*2 tFO － 30 ns Disable time of SO output during HOLD falling*2 tOZ.HL － 75 ns Delay time of SO output during HOLD rising*2 tOD.HH － 50 ns WP setup time tWS1 0 － ns WP hold time tWH1 0 － ns WP release / setup time tWS2 0 － ns WP release / hold time tWH2 20 － ns *1. The clock cycle of the SCK clock (frequency f SCK) is 1 / f SCK μs. This clock cycle is determined by a combination of several AC characteristics. Note that the clock cycle cannot be set as (1 / f SCK) = tLOW (min.) + tHIGH (min.) by minimizing the SCK clock cycle time. *2. These are values of sample and not 100% tested. Table 23 Item Symbol Ta = −40°C to +125°C Unit VCC = 2.5 V to 5.5 V Min. Max. Write time tPR － 5.0 ms

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A640A, S-25A640B Rev.3.2_00 Seiko Instruments Inc. 12  Pin Functions 1. CS (chip select input) pin This is an input pin to set a chip in the select status. In the "H" input level, this IC is in the non-select status and its output is "High-Z". This IC is in standby as long as it is not in write inside. Th is IC goes in active by setting the chip select to "L". Input any instruction code after power-on and a falling of chip select. 2. SI (serial data input) pin This pin is to input serial data. This pin receives an instruction code, an address and write data. This pin latches data at rising edge of serial clock. 3. SO (serial data output) pin This pin is to output serial data. The data output changes at falling edge of serial clock. 4. SCK (serial clock input) pin This is a clock input pin to set the timing of serial data. An instruction code, an address and write data are received at a rising edge of clock. Data is output during falling edge of clock. 5. WP (write protect input) pin Write protect is purposed to pr otect the area size against the write instruction (BP1, BP0 in the status register). Fix this pin "H" or "L" not to set it in the floating state. Refer to " Protect Operation" for details. 6. HOLD (hold input) pin This pin is used to pause serial communications without setting this IC in the non-select status. In the hold status, the serial output goes in "High-Z", the serial input and the serial clock go in "Don't care". During the hold operation, be sure to set this IC in active by setting the chip select ( CS pin) to "L". Refer to " Hold Operation" for details.  Initial Delivery State Initial delivery state of all addresses is "FFh". Moreover, initial delivery state of the status register nonvolatile memory is as follows.

• S R W D = 0
• BP1 = 0
• BP0 = 0

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM Rev.3.2_00 S-25A640A, S-25A640B Seiko Instruments Inc. 13  Instruction Set Table 24 is the list of instruction for This IC. The instruction is able to be input by changing the CS pin "H" to "L". Input the instruction in the MSB first. Each in struction code is organized with 1-byte as shown below. If This IC receives any invalid instruction code, this IC goes in the non-select status. Table 24 Instruction Set Instruction Operation Instruction Code Address Data SCK Input Clock 1 to 8 SCK Input Clock 9 to 16 SCK Input Clock 17 to 24 SCK Input Clock 25 to 32 WREN Write enable 0000 0110 － － － WRDI Write disable 0000 0100 － － － RDSR Read the status register 0000 0101 b7 to b0 output*1 － － WRSR Write in the status register 0000 0001 b7 to b0 input － － READ Read memory data 0000 0011 A15 to A8*2 A7 to A0 D7 to D0 output*3 WRITE Write memory data 0000 0010 A15 to A8*2 A7 to A0 D7 to D0 input *1. Sequential data reading is possible. *2. The higher addresses A15 to A13 = Don't care. *3. After outputting data in the specified addr ess, data in the following address is output.  Operation 1. Status register The status register's organization is below. The status register can write and read by a specific instruction. SRWD 0 b7 b6 BP1 BP0 WEL WIP Status Register Write Disable Block Protect Write Enable Latch Write In Progress Figure 10 Organization of Status Register The status / control bits of the status register are as follows. 1. 1 SRWD (b7) : Status Register Write Disable Bit SRWD operates in conjunction with the write protect signal ( WP ). With a combination of bit SRWD and signal WP (SRWD = "1", WP = "L"), this IC goes in Hardware Protect st atus. In this case, the bits composed of the nonvolatile memory in the status register (SRWD, BP1, BP0) go in read only, so that the WRSR in struction is not be performed.

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A640A, S-25A640B Rev.3.2_00 Seiko Instruments Inc. 14 1. 2 BP1, BP0 (b3, b2) : Block Protect Bit BP1 and BP0 are composed of the nonvolatile memory . The area size of Software Protect against WRITE instruction is defined by them . Rewriting these bits is possible by the WRSR instruction. To protect the memory area against the WRITE instruction, set either or both of bit BP1 and BP0 to "1". Rewriting bit BP1 and BP0 is possible unless they are in Hardware Protect mode. Refer to " Protect Operation" for details of Block Protect. 1. 3 WEL (b1) : Write Enable Latch Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL is "1", this is the status t hat Write Enable Latch is set. If bit WEL is "0", Write Enable Latch is in reset, so that this IC does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;

• The power supply voltage is dropping
• At power-on
• After performing WRDI
• After the completion of write operation by the WRSR instruction
• After the completion of write operation by the WRITE instruction 1. 4 WIP (b0) : Write In Progress Bit WIP is read only and shows whether the internal memory is in the write operation or not by the WRITE or WRSR instruction. Bit WIP is "1" during the write operation but "0" dur ing any other status. Figure 11 shows the usage example. 000 000 000 00 S R W D B P B P S R W D B P B P S R W D B tPR P B P WEL, WIP WEL, WIP WEL, WIP CS SI SO RDSR instruction RDSR inst ruction RDSR instruction RDSR RDSR RDSR 11 11 WRITE or WRSR instruction D2 D1D0 Figure 11 Usage Example of WEL, WIP Bits during Write 2. Write enable (WREN) Before writing data (WRITE and WRSR), be sure to set bit Wr ite Enable Latch (WEL). This instruction is to set bit WEL. Its operation is below. After selecting this IC by the chip select ( CS ), input the instruction code from se rial data input (SI). To set bit WEL, set this IC in the non-select status by CS at the 8th clock of the serial clock (SCK). To cancel the WREN instruction, input the clock different from a specified value (n = 8 clock) while CS is in "L".

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A640A, S-25A640B Rev.3.2_00 Seiko Instruments Inc. 16 4. Read the status register (RDSR) Reading data in the status regi ster is possible by the RDSR instruction. During the write operation, it is possible to confirm the progress by checking bit WIP. Set the chip select ( CS ) "L" first. After that, input the instruction code fr om serial data input (SI). The status of bit in the status register is output from serial data output (S O). Sequential read is available fo r the status register. To stop the read cycle, set CS to "H". It is possible to read the status register always. The bits in it are valid and can be r ead by RDSR even in the write cycle. The 2 bits WEL and WIP are updated during the write cycl e. The updated nonvolatile bits SRWD, BP1 and BP0 can be acquired by performing a new RDSR instruction after verifying the completion of the write cycle. SO SCK WP CS SI Instruction High-Z 12345678 High / Low 9 1 01 11 21 31 41 51 6 Outputs Data in the Status Register b7 b6 b5 b7 b0 b1 b2 b3 b4 Figure 14 RDSR Operation 5. Write in the status register (WRSR) The values of status register (SRWD, BP1, BP0) can be rewritten by inputting t he WRSR instruction. But b6, b5, b4, b1, b0 of status register cannot be rewritten. b6 to 4 are always data "0" when reading the status register. Before inputting the WRSR instruction, set bit WEL by the WREN instruction. The operation of WRSR is shown below. Set the chip select ( CS ) "L" first. After that, input the instruction c ode and data from serial data input (SI). To start WRSR write (t PR), set the chip select ( CS ) to "H" after inputting data or befor e inputting a rising of the next serial clock. It is possible to confirm the operat ion status by reading the value of bit WIP during WRSR write. Bit WIP is "1" during write, "0" during any other status. Bit WEL is reset when write is completed. With the WRSR instruction, the val ues of BP1 and BP0; which determine the area size the users can handle as the read only memory; can be changed. Besides bit SRWD can be set or reset by the WRSR instruction depending on the status of write protect ( WP ). With a combination of bit SRWD and write protect ( WP ), this IC can be set in Hardware Protect mode (HPM). In this case, the WRSR instruction is not be performed (Refer to "  Protect Operation"). Bit SRWD and BP1, BP0 keep the value which is the one prior to the WRSR instruction during the WRSR instruction. The newly updated value is changed when the WRSR instruction has completed. To cancel the WRSR instruction, input the clock different from a specified value (n = 16 clock) while CS is in "L".

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM Rev.3.2_00 S-25A640A, S-25A640B Seiko Instruments Inc. 19 SO SCK WP CS SI Instruction High-Z 12345678 High / Low 9 1 01 1 2 22 32 42 5 16-bit Address (n) A15 A14 A13 A0 A1 A2 Data Byte (n) Data Byte (n + x) D4 D5 D6 D7 26 27 28 29 30 31 32 D0 D1 D2 D3 D0 D1 D2 D3D4 Remark The higher addresses A15 to A13 = Don't care. Figure 18 WRITE Operation (Page)  Protect Operation Table 25 shows the block settings of write protect. Table 26 shows the protect operation for this IC. As long as bit SRWD, the Status Register Write Disable bit, in the status register is reset to "0" (it is in reset before t he shipment), the value o f status register can be changed. These are two statues when bit SRWD is set to "1".

• Write in the status register is possible; write protect ( WP ) is in "H".
• Write in the status register is impossible; write protect ( WP ) is in "L". Therefore the wr ite protect area which is set by protect bit (BP1, BP0) in t he status register cannot be changed. These operations are to set Hardware Protect (HPM).
• After setting bit SRWD, set write protect ( WP ) to "L".
• Set bit SRWD completed setting write protect ( WP ) to "L". The timing during the cycle write to the status register is showed in " Figure 8 Valid Timing in Write Protect " and "Figure 9 Invalid Timing in Write Protect ". By inputting "H" to write protect ( WP ), Hardware Protect (HPM) is released. If the write protect ( WP ) is "H", Hardware Protect (HPM) does not function, Software Protect (SPM) which is set by the protect bits in the status register (BP1, BP0) only works.

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A640A, S-25A640B Rev.3.2_00 Seiko Instruments Inc. 20 Table 25 Block Settings of Write Protect Status Register Area of Write Protect Addre ss of Write Protect Block BP1 BP0 0 0 0% None 0 1 25% 1800h to 1FFFh 1 0 50% 1000h to 1FFFh 1 1 100% 0000h to 1FFFh Table 26 Protect Operation Mode WP Pin Bit SRWD Bit WEL Write Protect Block General Block Status Register Software Protect (SPM)

1 X 0 Write disable Write disable Write disable

1 X 1 Write disable Write enable Write enable

X 0 0 Write disable Write disable Write disable X 0 1 Write disable Write enable Write enable Hardware Protect (HPM) 0 1 0 Write disable Write disable Write disable 0 1 1 Write disable Write enable Write disable Remark X = Don't care  Hold Operation The hold operation is used to pause serial communications wit hout setting this IC in the non- select status. In the hold status, the serial data output goes in "High-Z", and both of the serial data input and the serial clock go in "Don't care". Be sure to set the chip select ( CS ) to "L" to set this IC in the select status during the hold status. Generally, during the hold status, this IC hol ds the select status. But if setting this IC in the non-select status, the users can finish the operation even in progress. Figure 19 shows the hold operation. These are two statuses when the serial clock (SCK) is set to "L".

• If setting hold ( HOLD ) to "L", hold (HOLD ) is switched at the same time the hold status starts.
• If setting hold ( HOLD ) to "H", hold (HOLD ) is switched at the same time the hold status ends. These are two statuses when the serial clock (SCK) is set to "H".
• If setting hold ( HOLD ) to "L", the hold status starts when the serial clock goes in "L" after hold (HOLD ) is switched.
• If setting hold ( HOLD ) to "H", the hold status ends when the serial clock goes in "L" after hold (HOLD ) is switched. SCK HOLD Hold status Hold status Figure 19 Hold Operation

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