S25A010

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www.sii-ic.com FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM © Seiko Instruments Inc., 2008-2014 Rev.5.2_00 Seiko Instruments Inc. 1 This IC is a SPI serial E2PROM which operates under the high temperature, at high speed, with the wide range operation for automotive components. This IC has the capacity of 1 K-bit, 2 K-bi t, 4 K-bit and the organization of 128 words × 8-bit, 256 words × 8-bit, 512 words × 8-bit. Page write and Sequential read are available. Caution Before using the product in automobile control uni t or medical equipment, contact to SII is indispensable.  Features

• Operating voltage range Read: 2.5 V to 5.5 V Write: 2.5 V to 5.5 V
• Operation frequency: 6.5 MHz max.
• Write time: 4.0 ms max.
• SPI mode (0, 0) and (1, 1)
• Page write: 16 bytes / page
• Sequential read
• Write protect: Software, Hardware Protect area: 25%, 50%, 100%
• Monitoring of a write memory state by the status register
• Function to prevent malfunction by monitoring clock pulse
• Write protect function duri ng the low power supply voltage
• CMOS schmitt input ( CS , SCK, SI, WP , HOLD )
• Endurance *1: 106 cycle / word*2 (Ta = +25°C) 5 × 105 cycle / word*2 (Ta = +125°C)
• Data retention: 100 years (Ta = +25°C) 50 years (Ta = +125°C)
• Memory capacity S-25A010A: 1 K-bit S-25A020A: 2 K-bit S-25A040A: 4 K-bit
• Initial delivery state: FFh, BP1 = 0, BP0 = 0
• Burn-in specification: Wafer level burn-in
• Operation temper ature range: Ta = −40°C to +125°C
• Lead-free (Sn 100%), halogen-free
• AEC-Q100 qualified *4 *1. Refer to " Endurance" for details. *2. For each address (Word: 8-bit) *3. Refer to "  Product Name Structure" for details. *4. Contact our sales office for details.  Packages
• 8-Pin SOP (JEDEC)
• 8-Pin TSSOP
• TMSOP-8 Remark Refer to "3. Product name list " in " Product Name Structure" for details of package and product.

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_00 Seiko Instruments Inc. 2  Block Diagram Mode Decoder Status RegisterAddress Register Data Register WP CS HOLD SI SCK SO VCC GND Memory Cell Array Status Memory Cell Array Voltage Detector Read Circuit Clock Counter Y Decoder X Decoder Input Control Circuit Output Control Circuit Step-up Circuit Page Latch Figure 1

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM Rev.5.2_00 S-25A010A/020A/040A Seiko Instruments Inc. 3  AEC-Q100 Qualified This IC supports AEC-Q100 for operation temperature grade 1. Contact our sales office for details of AEC-Q100 reliability specification.  Product Name Structure 1. Product name S-25AxxxA 0 A − xxxx U D Burn-in specification D: Wafer level burn-in Environmental code U: Lead-free (Sn 100%), halogen-free Package name (abbreviation) and IC packing specification J8T2: 8-Pin SOP (JEDEC), Tape T8T2: 8-Pin TSSOP, Tape K8T2: TMSOP-8, Tape Fixed Product name S-25A010A: 1 K-bit S-25A020A: 2 K-bit S-25A040A: 4 K-bit *1. Refer to the tape drawing. 2. Packages Table 1 Package Drawing Codes Package Name Dimension Tape Reel 8-Pin SOP (JEDEC) FJ008-A-P-SD FJ008-D-C-SD FJ008-D-R-SD 8-Pin TSSOP FT008-A-P-SD FT008-E-C-SD FT008-E-R-SD TMSOP-8 FM008-A-P-SD FM008-A-C-SD FM008-A-R-SD 3. Product name list Table 2 Product Name Capacity Package Quantity S-25A010A0A-J8T2UD 1 K bit 8-Pin SOP (JEDEC) 2000 pcs / reel S-25A010A0A-T8T2UD 1 K bit 8-Pin TSSOP 3000 pcs / reel S-25A010A0A-K8T2UD 1 K bit TMSOP-8 4000 pcs / reel S-25A020A0A-J8T2UD 2 K bit 8-Pin SOP (JEDEC) 2000 pcs / reel S-25A020A0A-T8T2UD 2 K bit 8-Pin TSSOP 3000 pcs / reel S-25A020A0A-K8T2UD 2 K bit TMSOP-8 4000 pcs / reel S-25A040A0A-J8T2UD 4 K bit 8-Pin SOP (JEDEC) 2000 pcs / reel S-25A040A0A-T8T2UD 4 K bit 8-Pin TSSOP 3000 pcs / reel S-25A040A0A-K8T2UD 4 K bit TMSOP-8 4000 pcs / reel Remark 1. Please contact our sales office for products with product name structure other than those specified above. 2. This IC is wafer level burn-in specification.

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_00 Seiko Instruments Inc. 4  Pin Configurations 1. 8-Pin SOP (JEDEC) Top view Figure 2 Table 3 Pin No. Symbol Description

1 CS *1 Chip select input

2 SO Serial data output

3 WP *1 Write protect input

4 GND Ground

5 SI*1 Serial data input

6 SCK*1 Serial clock input

7 HOLD *1 Hold input

8 VCC Power supply

1. 8-Pin TSSOP Top view Figure 3 Table 4 Pin No. Symbol Description
2. TMSOP-8 Top view Figure 4 Table 5 Pin No. Symbol Description

*1. Do not use it in "High-Z".

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM Rev.5.2_00 S-25A010A/020A/040A Seiko Instruments Inc. 5  Absolute Maximum Ratings Table 6 Item Symbol Absolute Maximum Rating Unit Power supply voltage VCC −0.3 to +7.0 V Input voltage VIN −0.3 to +7.0 V Output voltage VOUT −0.3 to VCC + 0.3 V Operation ambient temperature T opr −40 to +125 °C Storage temperature Tstg −65 to +150 °C Caution The absolute maximum ratings are rated values exceeding whic h the product could suffer physical damage. These values must therefore not be exceeded under any conditions.  Recommended Operating Conditions Table 7 Item Symbol Condition Ta = −40°C to +125°C Unit Min. Max. Power supply voltage V CC Read 2.5 5.5 V Write 2.5 5.5 V High level input voltage V IH V CC = 2.5 V to 5.5 V 0.7 × VCC V CC + 1.0 V Low level input voltage V IL V CC = 2.5 V to 5.5 V −0.3 0.3 × VCC V  Pin Capacitance Table 8 (Ta = +25°C, f = 1.0 MHz, VCC = 5.0 V) Item Symbol Condition Min. Max. Unit Input capacitance C IN VIN = 0 V ( CS , SCK, SI, WP , HOLD ) － 8 pF Output capacitance C OUT V OUT = 0 V (SO) － 10 pF  Endurance Table9 Item Symbol Operation Ambient Temperature Min. Max. Unit Endurance N W Ta = −40°C to +85°C 10 6 － cycle / word*1 Ta = −40°C to +105°C 8 × 105 － cycle / word*1 Ta = −40°C to +125°C 5 × 105 － cycle / word*1 *1. For each address (Word: 8-bit)  Data Retention Table 10 Item Symbol Operation Ambient Temperature Min. Max. Unit Data retention － Ta = +25°C 100 － year Ta = −40°C to +125°C 50 － year

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_00 Seiko Instruments Inc. 6  DC Electrical Characteristics Table 11 Item Symbol Condition Ta = −40°C to +125°C Unit VCC = 2.5 V to 3.0 V fSCK = 3.5 MHz VCC = 3.0 V to 4.5 V fSCK = 5.0 MHz VCC = 4.5 V to 5.5 V fSCK = 6.5 MHz Current consumption (read) ICC1 No load at SO pin － 1.5 － 2.0 － 2.5 mA Table 12 Item Symbol Condition Ta = −40°C to +125°C Unit VCC = 2.5 V to 3.0 V fSCK = 3.5 MHz VCC = 3.0 V to 4.5 V fSCK = 5.0 MHz VCC = 4.5 V to 5.5 V fSCK = 6.5 MHz Current consumption (write) I CC2 No load at SO pin － 2.0 － 2.5 － 3.0 mA Table 13 Item Symbol Condition Ta = −40°C to +85°C Ta = +85°C to +125°C Unit Standby current consumption I SB CS = V CC, SO = Open Other inputs are V CC or GND Input leakage current I LI V IN = GND to VCC － 1.0 － 1.0 － 2.0 － 2.0 μA Output leakage current I LO V OUT = GND to VCC － 1.0 － 1.0 － 2.0 － 2.0 μA Low level output voltage V High level output voltage V OH1 I OH = −2.0 mA － － 0.8 × VCC － － － 0.8 × VCC － V VOH2 I OH = −0.4 mA 0.8 × VCC － 0.8 × VCC － 0.8 × VCC － 0.8 × VCC － V

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM Rev.5.2_00 S-25A010A/020A/040A Seiko Instruments Inc. 7  AC Electrical Characteristics Table 14 Measurement Conditions Input pulse voltage 0.2 × VCC to 0.8 × VCC Output reference voltage 0.5 × VCC Output load 100 pF Table 15 Item Symbol Ta = −40°C to +125°C SCK clock frequency fSCK － 3.5 － 5.0 － 6.5 MHz CS setup time during CS falling tCSS.CL 90 － 90 － 65 － ns CS setup time during CS rising tCSS.CH 90 － 90 － 65 － ns CS deselect time tCDS 160 － 140 － 110 － ns CS hold time during CS falling tCSH.CL 90 － 90 － 65 － ns CS hold time during CS rising tCSH.CH 90 － 90 － 65 － ns SCK clock time "H"*1 tHIGH 125 － 95 － 65 － ns SCK clock time "L"*1 tLOW 125 － 95 － 65 － ns Rising time of SCK clock*2 tRSK － 1 － 1 － 1 μs Falling time of SCK clock*2 tFSK － 1 － 1 － 1 μs SI data input setup time tDS 20 － 20 － 20 － ns SI data input hold time tDH 30 － 30 － 30 － ns SCK "L" hold time during HOLD rising tSKH.HH 70 － 70 － 45 － ns SCK "L" hold time during HOLD falling tSKH.HL 40 － 40 － 30 － ns SCK "L" setup time during HOLD falling tSKS.HL 0 － 0 － 0 － ns SCK "L" setup time during HOLD rising tSKS.HH 0 － 0 － 0 － ns Disable time of SO output*2 tOZ － 100 － 100 － 75 ns Delay time of SO output tOD － 120 － 90 － 60 ns Hold time of SO output tOH 0 － 0 － 0 － ns Rising time of SO output*2 tRO － 80 － 80 － 50 ns Falling time of SO output*2 tFO － 80 － 80 － 50 ns Disable time of SO output during HOLD falling*2 tOZ.HL － 100 － 100 － 75 ns Delay time of SO output during HOLD rising*2 tOD.HH － 80 － 80 － 60 ns WP setup time tWS1 0 － 0 － 0 － ns WP hold time tWH1 0 － 0 － 0 － ns WP release / setup time tWS2 0 － 0 － 0 － ns WP release / hold time tWH2 150 － 150 － 100 － ns *1. The clock cycle of the SCK clock (frequency f SCK) is 1 / f SCK μs. This clock cycle is determined by a combination of several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) + tHIGH (min.) by minimizing the SCK clock cycle time. *2. These are values of sample and not 100% tested.

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_00 Seiko Instruments Inc. 8 Table 16 Item Symbol Ta = −40°C to +105°C SCK clock frequency fSCK － 3.5 － 5.0 － 6.5 MHz CS setup time during CS falling tCSS.CL 90 － 90 － 65 － ns CS setup time during CS rising tCSS.CH 90 － 90 － 65 － ns CS deselect time tCDS 160 － 140 － 110 － ns CS hold time during CS falling tCSH.CL 90 － 90 － 65 － ns CS hold time during CS rising tCSH.CH 90 － 90 － 65 － ns SCK clock time "H"*1 tHIGH 125 － 95 － 65 － ns SCK clock time "L"*1 tLOW 125 － 95 － 65 － ns Rising time of SCK clock*2 tRSK － 1 － 1 － 1 μs Falling time of SCK clock*2 tFSK － 1 － 1 － 1 μs SI data input setup time tDS 20 － 20 － 20 － ns SI data input hold time tDH 30 － 30 － 30 － ns SCK "L" hold time during HOLD rising tSKH.HH 70 － 70 － 45 － ns SCK "L" hold time during HOLD falling tSKH.HL 40 － 40 － 30 － ns SCK "L" setup time during HOLD falling tSKS.HL 0 － 0 － 0 － ns SCK "L" setup time during HOLD rising tSKS.HH 0 － 0 － 0 － ns Disable time of SO output*2 tOZ － 100 － 100 － 75 ns Delay time of SO output tOD － 120 － 90 － 60 ns Hold time of SO output tOH 0 － 0 － 0 － ns Rising time of SO output*2 tRO － 80 － 70 － 50 ns Falling time of SO output*2 tFO － 80 － 70 － 50 ns Disable time of SO output during HOLD falling*2 tOZ.HL － 100 － 100 － 75 ns Delay time of SO output during HOLD rising*2 tOD.HH － 80 － 80 － 60 ns WP setup time tWS1 0 － 0 － 0 － ns WP hold time tWH1 0 － 0 － 0 － ns WP release / setup time tWS2 0 － 0 － 0 － ns WP release / hold time tWH2 150 － 150 － 100 － ns *1. The clock cycle of the SCK clock (frequency f SCK) is 1 / f SCK μs. This clock cycle is determined by a combination of several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) + tHIGH (min.) by minimizing the SCK clock cycle time. *2. These are values of sample and not 100% tested.

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM Rev.5.2_00 S-25A010A/020A/040A Seiko Instruments Inc. 9 Table 17 Item Symbol Ta = −40°C to +85°C SCK clock frequency fSCK － 4.0 － 5.0 － 7.0 MHz CS setup time during CS falling tCSS.CL 90 － 80 － 60 － ns CS setup time during CS rising tCSS.CH 90 － 80 － 60 － ns CS deselect time tCDS 150 － 120 － 100 － ns CS hold time during CS falling tCSH.CL 90 － 80 － 60 － ns CS hold time during CS rising tCSH.CH 90 － 80 － 60 － ns SCK clock time "H"*1 tHIGH 115 － 90 － 60 － ns SCK clock time "L"*1 tLOW 115 － 90 － 60 － ns Rising time of SCK clock*2 tRSK － 1 － 1 － 1 μs Falling time of SCK clock*2 tFSK － 1 － 1 － 1 μs SI data input setup time tDS 20 － 20 － 20 － ns SI data input hold time tDH 30 － 30 － 30 － ns SCK "L" hold time during HOLD rising tSKH.HH 70 － 60 － 40 － ns SCK "L" hold time during HOLD falling tSKH.HL 40 － 40 － 30 － ns SCK "L" setup time during HOLD falling tSKS.HL 0 － 0 － 0 － ns SCK "L" setup time during HOLD rising tSKS.HH 0 － 0 － 0 － ns Disable time of SO output*2 tOZ － 100 － 100 － 70 ns Delay time of SO output tOD － 110 － 85 － 55 ns Hold time of SO output tOH 0 － 0 － 0 － ns Rising time of SO output*2 tRO － 80 － 50 － 40 ns Falling time of SO output*2 tFO － 80 － 50 － 40 ns Disable time of SO output during HOLD falling*2 tOZ.HL － 100 － 100 － 70 ns Delay time of SO output during HOLD rising*2 tOD.HH － 80 － 75 － 55 ns WP setup time tWS1 0 － 0 － 0 － ns WP hold time tWH1 0 － 0 － 0 － ns WP release / setup time tWS2 0 － 0 － 0 － ns WP release / hold time tWH2 150 － 150 － 100 － ns *1. The clock cycle of the SCK clock (frequency f SCK) is 1 / f SCK μs. This clock cycle is determined by a combination of several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) + tHIGH (min.) by minimizing the SCK clock cycle time. *2. These are values of sample and not 100% tested.

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_00 Seiko Instruments Inc. 12  Pin Functions 1. CS (chip select input) pin This is an input pin to set a chip in the select status. In the "H" input level, this IC is in the non-select status and its output is "High-Z". This IC is in standby as long as it is not in write inside. Th is IC goes in active by setting the chip select to "L". Input any instruction code after power-on and a falling of chip select. 2. SI (serial data input) pin This pin is to input serial data. This pin receives an instruction code, an address and write data. This pin latches data at rising edge of serial clock. 3. SO (serial data output) pin This pin is to output serial data. The data output changes at falling edge of serial clock. 4. SCK (serial clock input) pin This is a clock input pin to set the timing of serial data. An instruction code, an address and write data are received at a rising edge of clock. Data is output during falling edge of clock. 5. WP (write protect input) pin This is an input pin to protect memory data when write instruction (WRITE, WRSR) is being input. By setting this pin to "L", the WEL bit in the status register is set to "L". Therefor e this IC does not write to the E 2PROM, however, it accepts other instructions. Fix this pin "H" or "L" not to set it in the floating state. Refer to " Protect Operation" for details. 6. HOLD (hold input) pin This pin is used to pause serial communications without setting this IC in the non-select status. In the hold status, the serial output goes in "High-Z", the serial input and the serial clock go in "Don't care". During the hold operation, be sure to set this IC in active by setting the chip select ( CS pin) to "L". Refer to " Hold Operation" for details.  Initial Delivery State Initial delivery state of all addresses is "FFh". Moreover, initial delivery state of the status register nonvolatile memory is as follows.

• BP1 = 0
• BP0 = 0

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM Rev.5.2_00 S-25A010A/020A/040A Seiko Instruments Inc. 13  Instruction Sets Table 19 and Table 20 are the list of instruction for this IC. The instruction is able to be input by changing the CS "H" to "L". Input the instructi on in the MSB first. Each instruction code is or ganized with 1-byte as shown below. If this IC receives any invalid instruction code, this IC goes in the non-select status. 1. S-25A010A/020A Table 19 Instruction Set Instruction Operation Instruction Code Address Data SCK Input Clock 1 to 8 SCK Input Clock 9 to 16 SCK Input Clock 17 to 24 WREN Write enable 0000 X110 － － WRDI Write disable 0000 X100 － － RDSR Read the status register 0000 X101 b7 to b0 output*1 － WRSR Write in the status r egister 0000 X001 b7 to b0 input － READ Read memory data 0000 X011 A7*2 to A0 D7 to D0 output *3 WRITE Write memory data 0000 X010 A7*2 to A0 D7 to D0 input *1. Sequential data reading is possible. *2. In the S-25A010A, A7 = Don’t care because the address range is A6 to A0. *3. After outputting data in the specified addr ess, data in the following address is output. Remark X = Don't care. 2. S-25A040A Table 20 Instruction Set Instruction Operation Instruction Code Address Data SCK Input Clock 1 to 8 SCK Input Clock 9 to 16 SCK Input Clock 17 to 24 WREN Write enable 0000 X110 － － WRDI Write disable 0000 X100 － － RDSR Read the status register 0000 X101 b7 to b0 output*1 － WRSR Write in the status r egister 0000 X001 b7 to b0 input － READ Read memory data 0000 [A8*2]011 A7 to A0 D7 to D0 output*3 WRITE Write memory data 0000 [A8*2]010 A7 to A0 D7 to D0 input *1. Sequential data reading is possible. *2. In the S-25A040A, assign bit A8 in the addre ss into the fifth bit in an instruction code. *3. After outputting data in the specified addr ess, data in the following address is output. Remark X = Don't care.

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_00 Seiko Instruments Inc. 14  Operation 1. Status register The status register's organization is below. The status register can write and read by a specific instruction. b7 b6 BP1 BP0 WEL WIP Block Protect Write Enable Latch Write In Progress Figure 10 Organization of Status Register The status / control bits of the status register are as follows. 1. 1 BP1, BP0 (b3, b2) : Block Protect Bit BP1 and BP0 are composed of the nonvolatile memory. The area size of Software Protect with respect to WRITE instructions is defined by the BP1 and BP0 bits. Rewr iting these bits is possible by the WRSR instruction. To protect the memory area against the WRITE instruction, set either or both of bit BP1 and BP0 to "1". Rewriting bit BP1 and BP0 is possible unless they are in Hardware Protect mode. Refer to " Protect Operation" for details of Block Protect. 1. 2 WEL (b1) : Write Enable Latch Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL is "1", this is the status t hat Write Enable Latch is set. If bit WEL is "0", Write Enable Latch is in reset, so that this IC does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;

• The power supply voltage is dropping
• At power-on
• After performing WRDI
• After the completion of write operation by the WRSR instruction
• After the completion of write operation by the WRITE instruction
• After setting WP pin to "L"

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_00 Seiko Instruments Inc. 16 3. Write disable (WRDI) The WRDI instruction is one of ways to reset bit Write Enable Latch (WEL). After selecting th is IC by the chip select ( CS ), input the instruction code from serial data input (SI). To reset bit WEL, set this IC in the non-select status by CS at the 8th clock of the serial clock. To cancel the WRDI instruction, input the clock different from a specified value (n = 8 clock) while CS is in "L". Bit WEL is reset after the operations shown below.

• The power supply voltage is dropping
• At power-on
• After performing WRDI
• After the completion of write operation by the WRSR instruction
• After the completion of write operation by the WRITE instruction
• After setting WP pin to "L" SO SCK WP CS SI Instruction High-Z 12345678 High / Low X Remark X = Don't care. Figure 13 WRDI Operation

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM Rev.5.2_00 S-25A010A/020A/040A Seiko Instruments Inc. 17 4. Read the status register (RDSR) Reading data in the status regi ster is possible by the RDSR instruction. During the write operation, it is possible to confirm the progress by checking bit WIP. Set the chip select ( CS ) "L" first. After that, input the instruction code fr om serial data input (SI). The status of bit in the status register is output from serial data output (S O). Sequential read is available fo r the status register. To stop the read cycle, set CS to "H". It is possible to read the status register always. The bits in it are valid and can be r ead by RDSR even in the write cycle. The 2 bits WEL and WIP are updated during the write cycle. The updated nonvolatile bits BP1 and BP0 can be acquired by performing a new RDSR instruction after verifying the completion of the write cycle. b7, b6, b5, and b4 are "1" when they are read by the RDSR instruction. SO SCK WP CS SI Instruction High-Z 12345678 High / Low 9 1 01 11 21 31 41 51 6 Outputs Data in the Status Register b7 b6 b5 b7 b0 b1 b2 b3 b4 X Remark X = Don't care. Figure 14 RDSR Operation

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_00 Seiko Instruments Inc. 18 5. Write in the status register (WRSR) The values of status register (BP1, BP0) can be rewritten by inputting the WRSR instruction. But b7, b6, b5, b4, b1, b0 of status register cannot be rewritten. b7 to b4 are always "1" when reading the status register. Before inputting the WRSR instruction, set bit WEL by the WREN instruction. The operation of WRSR is shown below. Set the chip select ( CS ) "L" first. After that, input the instruction c ode and data from serial data input (SI). To start WRSR write (t PR), set the chip select ( CS ) to "H" after inputting data or befor e inputting a rising of the next serial clock. It is possible to confirm the operat ion status by reading the value of bit WIP during WRSR write. Bit WIP is "1" during write, "0" during any other status. Bit WEL is reset when write is completed. With the WRSR instruction, the val ues of BP1 and BP0; which determine the area size the users can handle as the read only memory; can be changed. When WP pin is "L", however, the WRSR instruction is not be performed (Refer to " Protect Operation"). Bits BP1 and BP0 keep the value which is the one prior to the WRSR instruction during the WRSR instruction. The newly updated value is changed when the WRSR instruction has completed. To cancel the WRSR instruction, input the clock different from a specified value (n = 16 clock) while CS is in "L". SO SCK WP CS SI Instruction High-Z 12345678 High 9 1 01 11 21 31 41 51 6 Inputs Data in the Status Register b7 b6 b5 b0 b1 b2 b3 b4X Remark X = Don't care. Figure 15 WRSR Operation 6. Read memory data (READ) The READ operation is shown below. I nput the instruction code and the address from serial data input (SI) after inputting "L" to the chip select ( CS ). The input address is loaded to the internal address counter, and data in the address is output from the serial data output (SO). Next, by inputting the serial clo ck (SCK) keeping the chip select ( CS ) in "L", the address is automatically incremented so that data in the following address is sequentially output. The address counter rolls over to the first address by increment in the last address. To finish the read cycle, set CS to "H". It is possible to raise the chip select always during the cycle. During write, the READ instruction code is not be accepted or operated.

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM Rev.5.2_00 S-25A010A/020A/040A Seiko Instruments Inc. 23  Protect Operation Table 21 shows the block settings of write protect. Setting value in Protect Bits (BP1, BP0) in t he status register protect data in the area of all / 50% / 25% of the memory address. Setting WP pin to “L” provides the following settings.

• Write protect for the WRITE, WRSR instructions
• Reset bit WEL The timing during the cycle write to the status register is showed in " Figure 8 Valid Timing in Write Protect " and "Figure 9 Invalid Timing in Write Protect ". Table 21 Block Settings of Write Protect Status Register Area of Write Protect Address of Write Protect Block BP1 BP0 S-25A010A S-25A020A S-25A040A 0 0 0% None None None 0 1 25% 60h to 7Fh C0h to FFh 180h to 1FFh 1 0 50% 40h to 7Fh 80h to FFh 100h to 1FFh 1 1 100% 00h to 7Fh 00h to FFh 000h to 1FFh  Hold Operation The hold operation is used to pause serial communications wit hout setting this IC in the non- select status. In the hold status, the serial data output goes in "High-Z", and both of the serial data input and the serial clock go in "Don't care". Be sure to set the chip select ( CS ) to "L" to set this IC in the select status during the hold status. Generally, during the hold status, this IC hol ds the select status. But if setting this IC in the non-select status, the users can finish the operation even in progress. Figure 22 shows the hold operation. These are two statuses when the serial clock (SCK) is set to "L".
• If setting hold ( HOLD ) to "L", hold (HOLD ) is switched at the same time the hold status starts.
• If setting hold ( HOLD ) to "H", hold (HOLD ) is switched at the same time the hold status ends. These are two statuses when the serial clock (SCK) is set to "H".
• If setting hold ( HOLD ) to "L", the hold status starts when the serial clock goes in "L" after hold (HOLD ) is switched.
• If setting hold ( HOLD ) to "H", the hold status ends when the serial clock goes in "L" after hold (HOLD ) is switched. SCK HOLD Hold status Hold status Figure 22 Hold Operation

/X4E/X6F/X2E/X20/X46/X4A/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X32/X2E/X31 /X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54 /X6D/X6D /X53/X4F/X50/X38/X4A/X2D/X44/X2D/X50/X4B/X47/X20/X44/X69/X6D/X65/X6E/X73/X69/X6F/X6E/X73 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /X46/X4A/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X32/X2E/X31 /X30/X2E/X34/XB1/X30/X2E/X30/X35/X31/X2E/X32/X37 /X30/X2E/X32/X30/XB1/X30/X2E/X30/X35 /X35/X2E/X30/X32/XB1/X30/X2E/X32 /X31 /X34 /X38/X35

/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54 /X6D/X6D /X35 /X38/X31 /X34 /XF8/X32/X2E/X30/XB1/X30/X2E/X30/X35 /XF8/X31/X2E/X35/X35/XB1/X30/X2E/X30/X35 /X30/X2E/X33/XB1/X30/X2E/X30/X35 /X32/X2E/X31/XB1/X30/X2E/X31/X38/X2E/X30/XB1/X30/X2E/X31 /X35/XB0/X6D/X61/X78/X2E /X36/X2E/X37/XB1/X30/X2E/X31 /X32/X2E/X30/XB1/X30/X2E/X30/X35 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /X46/X65/X65/X64/X20/X64/X69/X72/X65/X63/X74/X69/X6F/X6E /X34/X2E/X30/XB1/X30/X2E/X31/X28/X31/X30/X20/X70/X69/X74/X63/X68/X65/X73/X3A/X34/X30/X2E/X30/XB1/X30/X2E/X32/X29 /X53/X4F/X50/X38/X4A/X2D/X44/X2D/X43/X61/X72/X72/X69/X65/X72/X20/X54/X61/X70/X65 /X4E/X6F/X2E/X20/X46/X4A/X30/X30/X38/X2D/X44/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X31 /X46/X4A/X30/X30/X38/X2D/X44/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X31

/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54/X6D/X6D /X51/X54/X59/X2E/X32/X2C/X30/X30/X30 /X32/XB1/X30/X2E/X35 /X31/X33/X2E/X35/XB1/X30/X2E/X35 /X36/X30/XB0 /X32/XB1/X30/X2E/X35 /XF8/X31/X33/XB1/X30/X2E/X32 /XF8/X32/X31/XB1/X30/X2E/X38 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /X45/X6E/X6C/X61/X72/X67/X65/X64/X20/X64/X72/X61/X77/X69/X6E/X67/X20/X69/X6E/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X72/X61/X6C/X20/X70/X61/X72/X74 /X53/X4F/X50/X38/X4A/X2D/X44/X2D/X52/X65/X65/X6C /X4E/X6F/X2E/X20/X46/X4A/X30/X30/X38/X2D/X44/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X31 /X46/X4A/X30/X30/X38/X2D/X44/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X31

/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /X54/X53/X53/X4F/X50/X38/X2D/X45/X2D/X50/X4B/X47/X20/X44/X69/X6D/X65/X6E/X73/X69/X6F/X6E/X73 /X4E/X6F/X2E/X20/X46/X54/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X31/X2E/X31 /X46/X54/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X31/X2E/X31 /X30/X2E/X31/X37/XB1/X30/X2E/X30/X35 /X33/X2E/X30/X30/X2B/X30/X2E/X33 /X20/X2D/X30/X2E/X32 /X30/X2E/X36/X35 /X30/X2E/X32/XB1/X30/X2E/X31 /X31 /X34 /X35/X38 /X6D/X6D

/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /XF8/X31/X2E/X35/X35/XB1/X30/X2E/X30/X35 /X32/X2E/X30/XB1/X30/X2E/X30/X35 /X38/X2E/X30/XB1/X30/X2E/X31/XF8/X31/X2E/X35/X35/X2B/X30/X2E/X31 /X20/X2D/X30/X2E/X30/X35 /X28/X34/X2E/X34/X29 /X30/X2E/X33/XB1/X30/X2E/X30/X35 /X31 /X34 /X35 /X38 /X34/X2E/X30/XB1/X30/X2E/X31 /X46/X65/X65/X64/X20/X64/X69/X72/X65/X63/X74/X69/X6F/X6E /X54/X53/X53/X4F/X50/X38/X2D/X45/X2D/X43/X61/X72/X72/X69/X65/X72/X20/X54/X61/X70/X65 /X4E/X6F/X2E/X20/X46/X54/X30/X30/X38/X2D/X45/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X30 /X46/X54/X30/X30/X38/X2D/X45/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X30 /X2B/X30/X2E/X34 /X20/X2D/X30/X2E/X32/X36/X2E/X36 /X6D/X6D

/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /X45/X6E/X6C/X61/X72/X67/X65/X64/X20/X64/X72/X61/X77/X69/X6E/X67/X20/X69/X6E/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X72/X61/X6C/X20/X70/X61/X72/X74 /X4E/X6F/X2E/X20/X46/X54/X30/X30/X38/X2D/X45/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X30 /X32/XB1/X30/X2E/X35 /XF8/X31/X33/XB1/X30/X2E/X35 /XF8/X32/X31/XB1/X30/X2E/X38 /X31/X33/X2E/X34/XB1/X31/X2E/X30 /X31/X37/X2E/X35/XB1/X31/X2E/X30 /X33/X2C/X30/X30/X30/X51/X54/X59/X2E /X54/X53/X53/X4F/X50/X38/X2D/X45/X2D/X52/X65/X65/X6C /X46/X54/X30/X30/X38/X2D/X45/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X30 /X6D/X6D

/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /X32/X2E/X39/X30/XB1/X30/X2E/X32 /X38/X35 /X30/X2E/X32/XB1/X30/X2E/X31 /X30/X2E/X36/X35/XB1/X30/X2E/X31 /X30/X2E/X31/X33/XB1/X30/X2E/X31 /X31/X34 /X54/X4D/X53/X4F/X50/X38/X2D/X41/X2D/X50/X4B/X47/X20/X44/X69/X6D/X65/X6E/X73/X69/X6F/X6E/X73 /X4E/X6F/X2E/X20/X46/X4D/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X31/X2E/X31 /X46/X4D/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X31/X2E/X31 /X6D/X6D

/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /X30/X2E/X33/X30/XB1/X30/X2E/X30/X35 /X31/X2E/X30/X30/XB1/X30/X2E/X31 /X31/X2E/X30/X35/XB1/X30/X2E/X30/X35 /X31/X2E/X35 /X32/X2E/X30/X30/XB1/X30/X2E/X30/X35 /X34/X2E/X30/X30/XB1/X30/X2E/X31 /X33/X2E/X32/X35/XB1/X30/X2E/X30/X35 /X34/X2E/X30/X30/XB1/X30/X2E/X31 /X31/X34 /X35/X38 /X54/X4D/X53/X4F/X50/X38/X2D/X41/X2D/X43/X61/X72/X72/X69/X65/X72/X20/X54/X61/X70/X65 /X46/X65/X65/X64/X20/X64/X69/X72/X65/X63/X74/X69/X6F/X6E /X4E/X6F/X2E/X20/X46/X4D/X30/X30/X38/X2D/X41/X2D/X43/X2D/X53/X44/X2D/X32/X2E/X30 /X46/X4D/X30/X30/X38/X2D/X41/X2D/X43/X2D/X53/X44/X2D/X32/X2E/X30 /X2B/X30/X2E/X31 /X20/X2D/X30 /X6D/X6D

/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X53/X43/X41/X4C/X45 /X55/X4E/X49/X54 /X53/X65/X69/X6B/X6F/X20/X49/X6E/X73/X74/X72/X75/X6D/X65/X6E/X74/X73/X20/X49/X6E/X63/X2E /X31/X36/X2E/X35/X6D/X61/X78/X2E /X31/X33/X2E/X30/XB1/X30/X2E/X33 /X51/X54/X59/X2E /X34/X2C/X30/X30/X30 /X28/X36/X30/XB0/X29/X28/X36/X30/XB0/X29 /X31/X33/XB1/X30/X2E/X32 /X45/X6E/X6C/X61/X72/X67/X65/X64/X20/X64/X72/X61/X77/X69/X6E/X67/X20/X69/X6E/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X72/X61/X6C/X20/X70/X61/X72/X74 /X54/X4D/X53/X4F/X50/X38/X2D/X41/X2D/X52/X65/X65/X6C /X4E/X6F/X2E/X20/X46/X4D/X30/X30/X38/X2D/X41/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X30 /X46/X4D/X30/X30/X38/X2D/X41/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X30 /X6D/X6D

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