S24C512C

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www.sii-ic.com 2-WIRE SERIAL E2PROM © SII Semiconductor Corporation, 2010-2013 Rev.2.0_02_S The S-24C512C is a 2-wire, low current c onsumption and wide range operation serial E 2PROM. The S-24C512C has the capacity of 512 K-bit, and the organization is 65536 words × 8-bit. Page write and sequential read are available.  Features

• Operating voltage range Read: 1.6 V to 5.5 V Write: 1.7 V to 5.5 V
• Page write: 128 bytes / page
• Sequential read
• Operation frequency: 1.0 MHz (V CC = 2.5 V to 5.5 V) 400 kHz (V CC = 1.6 V to 2.5 V)
• Write time: 5.0 ms max.
• Noise suppression: Schmitt trigger and noi se filter on input pins (SCL, SDA)
• Write protect function during the low power supply voltage
• Endurance: 10 6 cycles / unit*1 (Ta = +25°C)
• Data retention: 100 years (Ta = +25°C)
• Memory capacity: 512 K-bit
• Write protect: 100%
• Initial shipment data: FFh
• Lead-free (Sn 100%), halogen-free*2 *1. For each unit (unit: the 4 bytes with the same address of W15 to W2) *2. Refer to “ Product Name Structure” for details.  Packages
• 8-Pin SOP (JEDEC)
• 8-Pin TSSOP Caution This product is intended to use in general electronic devices su ch as consumer electronics, office equipment, and communications devices. Before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to SII Semiconductor Corporation is indispensable.

S-24C512C Rev.2.0_02_S  Pin Configurations 1. 8-Pin SOP (JEDEC) 8-Pin SOP (JEDEC) Top view Table 1 Figure 1 S-24C512CI-J8T1U4 Pin No Symbol Description

1 A0 Slave address input

2 A1 Slave address input

3 A2 Slave address input

4 GND Ground

5 SDA*1 Serial data I/O

6 SCL*1 Serial clock input

Connected to VCC: Protection valid Open or connected to GND: Protection invalid

8 VCC Power supply

*1. Do not use it in high impedance. 2. 8-Pin TSSOP 8-Pin TSSOP Top view Table 2 Figure 2 S-24C512CI-T8T1U4 Pin No Symbol Description Connected to VCC: Protection valid Open or connected to GND: Protection invalid *1. Do not use it in high impedance. Remark Refer to the “Package drawings” for the details.

Rev.2.0_02_S S-24C512C  Block Diagram VCC GND SCL SDA DIN DOUT R / W LOAD INC COMP LOAD WP Start / Stop Detector Serial Clock Controller High-Voltage Generator Voltage Detector Device Address Comparator Address Counter Y Decoder Data Register Memory Cell ArrayX Decoder Selector Data Output ACK Output Controller Figure 3

S-24C512C Rev.2.0_02_S  Absolute Maximum Ratings Table 3 Item Symbol Absolute Maximum Ratings Unit Power supply voltage V CC −0.3 to +6.5 V Input voltage V IN −0.3 to +6.5 V Output voltage V OUT −0.3 to +6.5 V Operation ambient temperature T opr −40 to +85 °C Storage temperature T stg −65 to +150 °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions.  Recommended Operating Conditions Table 4 Item Symbol Condition Ta = −40°C to +85°C Unit Min. Max. Power supply voltage VCC Read Operation 1.6 5.5 V Write Operation 1.7 5.5 V High level input voltage VIH VCC = 1.8 V to 5.5 V 0.7 × VCC 5.5 V VCC = 1.6 V to 1.8 V 0.8 × VCC 5.5 V Low level input voltage VIL VCC = 1.8 V to 5.5 V −0.3 0.3 × VCC V VCC = 1.6 V to 1.8 V −0.3 0.2 × VCC V  Pin Capacitance Table 5 (Ta = +25°C, f = 1.0 MHz, VCC = 5.0 V) Item Symbol Condition Min. Max. Unit Input capacitance C IN VIN = 0 V (SCL, A0, A1, A2, WP) − 10 pF I/O capacitance C I / O VI / O = 0 V (SDA) − 10 pF  Endurance Table 6 Item Symbol Operation Ambient Temperature Min. Max. Unit Endurance N W Ta = +25°C 10 6 − cycles / unit*1 *1. For each unit (unit: the 4 bytes with the same address of W15 to W2)  Data Retention Table 7 Item Symbol Operation Ambient Temperature Min. Max. Unit Data retention − Ta = +25°C 100 − year

Rev.2.0_02_S S-24C512C  DC Electrical Characteristics Table 8 Item Symbol Condition Ta = −40°C to +85°C Unit VCC = 2.5 V to 5.5 V fSCL = 1.0 MHz VCC = 1.6 V to 2.5 V fSCL = 400 kHz Min. Max. Min. Max. Current consumption (READ) I CC1 − − 2.0 − 1.5 mA Table 9 Item Symbol Condition Ta = −40°C to +85°C Unit VCC = 2.5 V to 5.5 V fSCL = 1.0 MHz VCC = 1.7 V to 2.5 V fSCL = 400 kHz Min. Max. Min. Max. Current consumption (WRITE) I CC2 − − 4.0 − 4.0 mA Table 10 Item Symbol Condition Ta = −40°C to +85°C Unit VCC = 2.5 V to 5.5 V V CC = 1.6 V to 2.5 V Min. Max. Min. Max. Standby current consumption I SB V IN = VCC or GND − 8.0 − 4.0 μA Input leakage current 1 I LI1 SCL, SDA, VIN = GND to VCC − 1.0 − 1.0 μA Input leakage current 2 I LI2 A0, A1, A2 VIN > 0.7 × VCC At standby mode − 1.0 − 1.0 μA Output leakage current I LO SDA VOUT = GND to VCC − 1.0 − 1.0 μA Input current 1 I IL WP VIN < 0.3 × VCC − 50.0 − 50.0 μA Input current 2 I IH WP VIN > 0.7 × VCC − 2.0 − 2.0 μA Input Impedance 1 Z IL WP VIN = 0.3 × VCC 30 − 30 − k Ω Input Impedance 2 Z IH WP VIN = 0.7 × VCC 500 − 500 − k Ω Low level output voltage V OL IOL = 3.2 mA − 0.4 − − V IOL = 1.5 mA − 0.3 − 0.3 V IOL = 0.7 mA − 0.2 − 0.2 V

Rev.2.0_02_S S-24C512C Table 13 Item Symbol Ta = −40°C to +85°C Unit VCC = 1.7 V to 5.5 V Min. Max. Write time t WR − 5.0 ms SCL SDA D0 Write data Acknowledgment Signal Stop Condition Start ConditiontWR Start Condition WP (valid) WP (invalid) tWS1 tWH1 tWS2 tWH2 Figure 6 Write Cycle Timing

S-24C512C Rev.2.0_02_S  Pin Functions 1. A0, A1 and A2 (Slave address input) pins In the S-24C512C, to set the slave address, connect each pin of A0, A1, A2 to GND or V CC. Therefore the users can set 8 types of slave address by a combination of A0, A1, A2 pins. Comparing the slave address transmitted from the master device and one that you set, makes possible to select the S-24C512C from other devices connected onto the bus. Each A0, A1 and A2 pin has a pull-down resistor. In open, these pins have the status when they are connected to GND. 2. SDA (Serial data input / output) pin The SDA pin is used for the bi-directional transmission of se rial data. This pin is a signal input pin, and an Nch open drain output pin. In use, generally, connect the SDA line to any other devic e which has the open-drain or open-collector output with Wired-OR connection by pulling up to VCC by a resistor (Figure 7 shows the relation with an output load). 3. SCL (Serial clock input) pin The SCL pin is used for the serial clock input. Since the signals are processed at a ri sing or falling edge of the SCL clock, pay attention to the rising and falling time and comply with the specification. 4. WP (Write protect input) pin The write protect is enabled by connecting the WP pin to V CC. When not using the write protect, connect this pin to GND or set in open. Maximum value of pull-up resistor [kΩ] 100 200 fSCL= 400 kHz fSCL= 1000 kHz Value of load capacity [pF] Figure 7 Output Load  Initial Shipment Data Initial shipment data of all addresses is “FFh”.

Rev.2.0_02_S S-24C512C  ECC Function (Error correction function) S-24C512C Series adds 6 ECC bits for error correction to each 4 bytes with the same address of W15 to W2. The ECC function can make correction and output correct data even if wrong data of 1 bit is in the 4 bytes when reading. In addition, the S-24C512C Series rewrites the 4 bytes used as the rewriting minimum unit and 6 ECC bits if only 1 byte data is input. Therefore, it is recommended to rewrite data of each 4 bytes with the same address of W15 to W2 in order to get the maximum endurance in the application in which the data is rewrote frequently.  Operation 1. Start condition Start is identified by a high to low transition of the SDA line while the SCL line is stable at high. Every operation begins from a start condition. 2. Stop condition Stop is identified by a low to high transition of the SDA line while the SCL line is stable at high. When a device receives a stop condition during a read s equence, the read operation is interrupted, and the device enters standby mode. When a device receives a stop condition during a write sequence, the reception of the write data is halted, and the S- 24C512C initiates a write cycle. tSU.STA tHD.STA tSU.STO Start Condition Stop Condition SCL SDA Figure 8 Start / Stop Conditions

Rev.2.0_02_S S-24C512C 5. Device addressing To start communication, the master device on the system generates a start condition to the bus line. Next, the master device sends 7-bit device address and a 1-bit read / write instruction code on to the SDA bus. The upper 4 bits of the device address are the “Device Code”, and are fixed to “1010”. In the S-24C512C, successive 3 bits are the “Slave Addr ess”. These 3 bits are used to identify a device on the system bus and is compared with the predetermined value whic h is defined by the address input pins (A2, A1, A0). When the comparison result matches, the slave device responds with an acknowlede during the 9th clock cycle. Slave AddressDevice Code MSB LSB 1 0 1 0 A2 A1 A0 R / W Figure 11 Device Address

S-24C512C Rev.2.0_02_S 6. Write 6. 1 Byte write When the master sends a 7-bit device address and a 1-bit read / write instruction code set to “0”, following a start condition, the S-24C512C acknowledges it. The S-24C 512C then receives a upper 8-bit word address and responds with an acknowledge. And the S-24C512C receiv es a lower 8-bit word address and responds with an acknowledge. After the S-24C512C receives 8-bit write data and responds with an acknowledge, it receives a stop condition and that initiates the write cycle at the addressed memory. During the write cycle all operations are forbidden and no acknowledge is generated. A2 A1 A0 S T A R T 1 0 1 0 W R I T E DEVICE ADDRESS UPPER WORD ADDRESS R W M S B SDA LINE A C K L S B LOWER WORD ADDRESS S T O PDATA W15 W7 W6 W5 W4 W3 W2 W1 W0 D7 D6 D5 D4 D3 D2 D1 D0W12 W11 W10 W9 W8 A C K A C K W13 A C K W14 Figure 12 Byte Write

Rev.2.0_02_S S-24C512C 6. 2 Page write The page write mode allows up to 128 bytes to be written in a single write operation in the S-24C512C. Its basic process to transmit data is as same as byte write, but it operates page write by sequentially receiving 8-bit write data as much data as the page size has. When the S-24C512C receives a 7-bit device address and a 1-bit read / write instruction code set to “0”, following a start condition, it generates an acknowledge. And t he S-24C512C receives a upper 8-bit word address, and responds with an acknowledge. Then the S-24C512C receiv es a lower 8-bit word address, and responds with an acknowledge. After the S-24C512C receives 8-bit write dat a and responds with an acknowledge, it receives 8-bit write data corresponding to the next word address, and generates an acknowledge. The S-24C512C repeats reception of 8-bit write data and generation of acknowl edge in succession. The S-24C512C can receive as many write data as the maximum page size. Receiving a stop condition initiates a write cycle of the area starting from the designated memory address and having the page size equal to the received write data. A2 A1 A0 S T A R T 1 0 1 0 W R I T E DEVICE ADDRESS UPPER WORD ADDRESS (n) R W M S B SDA LINE A C K L S B LOWER WORD ADDRESS (n)

0 W15 W7 W6 W5 W4 W3 W2 W1 W0

DATA (n) D7 D0 S T O P W12 W11 W10 W9 W8 A C K W13 A C K DATA (n+x) D7 D0W14 Figure 13 Page Write In the S-24C512C, the lower 7 bits of the word address are automatically incremented every time when the S-24C512C receives 8-bit write data. If the size of the wr ite data exceeds 128 bytes, the upper 9 bits of the word address remain unchanged, and the lower 7 bits are rolled over and the last 128-byte data that the S-24C512C received will be overwritten.

Rev.2.0_02_S S-24C512C 6. 4 Acknowledge polling Acknowledge polling is used to know the completion of the write cycle in the S-24C512C. After the S-24C512C receives a stop condition and once starts the write cycle, all operations are inhibited and no response is made to the signal transmitted by the master device. Accordingly the master device can recognize the completion of the write cycle in the S-24C512C by detecting a response from the slave device after transmitting the start condition, the device address and the read / write instruction code to the S-24C512C (slave device). That is, if the S-24C512C does not generate an acknowledgm ent signal, the write cycle is in progress and if the S-24C512C generates an acknowledgment signal, the write cycle has been completed. It is recommended to use the read instruction “1” as the read / write instruction code transmitted by the master device. S T A R T A C K N A C K Remark Users are able to input word address and data afte r ACK output in acknowledge polling during write. Users are able to read data after ACK output in acknowledge polling during read. However, after that users input the write instruction, a start condition may not be input during data output. Input a stop condition and the next instruction after data output and ACK output. SDA LINE DEVICE ADDRESS DATA D2 D1 D0 S T O P tWR S T A R T S T A R T A C K SDA LINE DATA D2 D1 D0 S T O P tWR S T A R T N A C K S T O P DATA NO ACK from Master Device R E A D R W W R I T E R W

0 DEVICE

W R I T E R W 0DEVICE ADDRESS DEVICE ADDRESS R E A D R W Acknowledge polling during write Acknowledge polling during read A C K S T A R T DEVICE ADDRESS R W A C K WORD ADDRESS Figure 15 Usage Example of Acknowledge Polling

S-24C512C Rev.2.0_02_S 7. Read 7. 1 Current address read Either in writing or in reading the S-24C512C holds t he last accessed memory address. The memory address is maintained as long as the power voltage does not decrease less than the operating voltage. The master device can read the data at the memory addre ss of the current address pointer without assigning the word address as a result, when it recognizes the position of the address pointer in the S-24C512C. This is called “Current Address Read”. In the following the address counter in the S-24C512C is assumed to be “n”. When the S-24C512C receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following a start condition, it responds with an acknowledge. Next, an 8-bit data at the address “n” is sent from the S-24C512C synchronous to the SCL clock. The address counter is incremented and the content of the address counter becomes n +1. The master device outputs stop condition not an acknowledge, the reading of S-24C512C is ended. S T A R T 1 0 1 0 R E A D S T O P DEVICE ADDRESS R W M S B SDA LINE A2 A1 A0 D7 D6 D5 D4 D3 D2 D1D0 A C K L S B DATA NO ACK from Master Device Figure 16 Current Address Read Attention should be paid to the following point on the recognition of the address pointer in the S-24C512C. In Read, the memory address counter in the S-24C512C is automatically incremented after output of the 8th bit of the data. In Write, on the other hand, the upper bits of the memory address (the upper bits of the word address*1) are left unchanged and are not incremented. ∗1. The upper 9 bits of the word address

Rev.2.0_02_S S-24C512C 7. 2 Random read Random read is used to read the data at an arbitrary memory address. A dummy write is performed to load the memory address into the address counter. When the S-24C512C receives a 7-bit device address and a 1-bit read / write instruction code set to “0” following a start condition, it responds with an acknowledge. The S-24C512C then receives a upper 8-bit word address and responds with an acknowledge. And the S-24C512C receives a lower 8-bit word address and re sponds with an acknowledge. The memory address is loaded to the address counter in the S-24C512C by these operations. Reception of write data does not follow in a dummy write whereas reception of write data follows in byte write and in page write. Since the memory address is loaded into the memory addr ess counter by dummy write, the master device can read the data starting from the arbitrary memory address by transmitting a new start condition and performing the same operation in the current address read. That is, when the S-24C512C receives a 7-bit device address and a 1-bit read / write instruction code set to “1”, following a start condition signal, it responds with an ack nowledge. Next, 8-bit data is transmitted from the S-24C512C in synchronous to the SCL clock. The mast er device outputs stop condition not an acknowledge, the reading of S-24C512C is ended. SDA LINE S T A R T 1 0 1 0 W R I T E DEVICE ADDRESS LOWER WORD ADDRESS R W M S B A2 A1 A0 A C K L S B W7 W6 W5 W4 W3 W2 W1 A C K DUMMY WRITE S T O P S T A R T 1 0 1 0 R E A D DEVICE ADDRESS R W M S B A2 A1 A0 A C K L S B 1 下図へ続く NO ACK from Master Device DATA UPPER WORD ADDRESS X W9W8W15 D7 D6 D5D4D3D2D1D0 A C K W12 W11 W10 W0W13 W14 Figure 17 Random Read

S-24C512C Rev.2.0_02_S 7. 3 Sequential read When the S-24C512C receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following a start condition both in current address read and random read, it responds with an acknowledge. When an 8-bit data is output from the S-24C512C sync hronous to the SCL clock, the address counter is automatically incremented. When the master device responds with an acknowledge, the data at the next memory address is transmitted. Response with an acknowledge by the master device has the memory address counter in the S-24C512C incremented and makes it possible to read data in succession. This is called “Sequential Read”. The master device outputs stop condition not an acknowledge, the reading of S-24C512C is ended. Data can be read in succession in the sequential read mode. When the memory address counter reaches the last word address, it rolls over to the first word address. R E A D S T O P DEVICE ADDRESS R W A C K A C K A C K A C K SDA LINE DATA (n) D7 D0 D7 D0D7 D0 D7 D0 DATA (n+1) DATA (n+2) DATA (n+x) NO ACK from Master Device Figure 18 Sequential Read

Rev.2.0_02_S S-24C512C  Write Protect Function during the Low Power Supply Voltage The S-24C512C has a built-in detection circuit which operates with the low power supply voltage, cancels Write when the power supply voltage drops and power-on. Its detection and release voltages are 1.50 V typ. (Refer to Figure 19). The S-24C512C cancels Write by detecting a low power supply voltage when it receives a stop condition. In the data trasmission and the Write operation, data in the address written during the low power supply voltage is not assurable. Release Voltage (+VDET) 1.50 V typ. Power Supply Voltage Detection Voltage (−VDET) 1.50 V typ. Write Instruction cancel Figure 19 Operation during Low Power Supply Voltage

S-24C512C Rev.2.0_02_S 3. Phase adjustment during S-24C512C access The S-24C512C does not have a pin to reset (the internal circui t). The users cannot forcibly reset it externally. If the communication to the S-24C512C interrupted, the users need to handle it as you do for software. In the S-24C512C, users are able to reset the internal circuit by inputting a start condition and a stop condition. Although the reset signal is input to the master device, t he S-24C512C’s internal circuit does not go in reset, but it does by inputting a stop condition to the S-24C512C. The S-24C512C keeps the same status thus cannot do the next operation. Especially, this case corresponds to that only the master device is reset when the power supply voltage drops. If the power supply voltage restored in this status, input t he instruction after resetting (adjusting the phase with the master device) the S-24C512C. How to reset is shown below. [How to reset S-24C512C] The S-24C512C is able to be reset by a start and stop inst ructions. When the S-24C512C is reading data “0” or is outputting the acknowledgment signal, outputs “0” to the SDA line. In this status, the master device cannot output an instruction to the SDA line. In this case, terminat e the acknowledgment output operation or the Read operation, and then input a start instruction. Figure 24 shows this procedure. First, input a start condition. Then transmit 9 clocks (dummy clock) of SCL. During this time, the master device sets the SDA line to “H”. By this operation, the S-24C512C interrupts the acknowledgment output operation or data output, so input a start condition *1. When a start condition is input, the S-24C512C is reset. To make doubly sure, input the stop condition to the S-24C512C. The normal operation is then possible. 1 2 8 9 SCL SDA Start Condition Stop Condition Start ConditionDummy Clock Figure 24 Resetting S-24C512C *1. After 9 clocks (dummy clock), if the SCL clock conti nues to being output without inputting a start condition, S-24C512C may go in the write operation when it receiv es a stop condition. To prevent this, input a start condition after 9 clocks (dummy clock). Remark Regarding this reset procedure with dummy clock, it is recommended to perform at the system initialization after applying the power supply voltage.

Rev.2.0_02_S S-24C512C 4. Acknowledge check The I2C-bus protocol includes an acknowledge check function as a handshake f unction to prevent a communication error. This function allows detection of a communication failure during data communication between the master device and S-24C512C. This function is effective to prev ent malfunction, so it is recommended to perform an acknowledge check with the master device. 5. Built-in power-on-clear circuit The S-24C512C has a built-in power-on-clear circuit that in itializes itself at the same time during power-on. Unsuccessful initialization may cause a malfunction. To operate the power-on-clear circuit normally, the following conditions must be satisfied to raise the power supply voltage. 5. 1 Raising power supply voltage Shown in Figure 25, raise the power supply voltage from 0.2 V max., within the time defined as t RISE which is the time required to reach the power supply voltage to be set. For example, if the power supply voltage is 5.0 V, t RISE = 200 ms seen in Figure 26. The power supply voltage must be raised within 200 ms. 0.2 V VINIT max. tINIT *2 max. tRISE max. Power Supply Voltage (V CC)

0 V*1

*1. 0 V means there is no difference in potential between the VCC pin and the GND pin of the S-24C512C. *2. tINIT is the time required to initialize the S-24C512C. No instructions are accepted during this time. Figure 25 Raising Power Supply Voltage

S-24C512C Rev.2.0_02_S Power Supply Voltage Rise Time (t RISE) max. [ms] Power Supply Voltage (V CC) [V] 5.0 4.0 3.0 2.0 100 150 200 For example: If the power supply voltage = 5.0 V, raise the power supply voltage to 5.0 V within 200 ms. Figure 26 Power Supply Voltage Rise Time When initialization is successfully completed by the power-on-clear circuit, the S-24C512C enters the standby status. If the power-on-clear circuit does not operate; The S-24C512C has not completed initializ ation, an instruction prev iously input is still valid or an instruction may be inappropriately recognized. In this case, S-24C512C may perform the Write operation. The voltage drops due to power off while the S-24C512C is being accessed. Even if the master device is reset due to the low power voltage, the S-24C512C may malfunc tion unless the power-on-clear operation conditions of S-24C512C are satisfied. When not keeping to the power supply voltage rise time seen in Figure 26, adjust the phase (reset) to reset the internal circuit in the S-24C512C normally.

Rev.2.0_02_S S-24C512C 8. Operation when input stop condition during input write data The S-24C512C does the write operation only when it receives data of 1 byte or more and receives a stop condition immediately after ACK output. Refer to Figure 30 regarding details. R W S T A R T 1 0 1 0 W R I T E S T O PDEVICE ADDRESS DATA (n) LOWER WORD ADDRESS (n) M S B SDA LINE A2 A1 A0 A C K L S B A C K A C K

0 W7 W0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D0

A C K A C K DATA (n+1) DATA (n+x) Write Inhibition by stop condition Write Inhibition by stop condition UPPER WORD ADDRESS (n) A C K W15 W8 Write Inhibition by stop condition Write Enable by stop condition Write Enable by stop condition Figure 30 Write Operation by Inputting Stop Condition during Write 9. Command cancel by start condition By a start condition, users are able to cancel command wh ich is being input. However, adjust the phase while the S-24C512C is outputting “L” because users are not able to input a start condition. When users cancel the command, there may be a case that the address will not be identified. Us e random read for the read operation, not current address read. 10. Precaution for use Do not operate these ICs in excess of the absolute maxi mum ratings. Attention should be paid to the power supply voltage, especially. The surge voltage which exceeds the maximum absolute ratings can cause latch-up and malfunction. Perform operations after confirming the detailed operation condition in the data sheet. Operations with moisture on the S-24C512C pins may occu r malfunction by short-circuit between pins. Especially, in occasions like picking the S-24C512C up from low temperature tank during the evaluation. Be sure that not remain frost on the S-24C512C’s pins to prevent malfunction by short-circuit. Also attention should be paid in using on environment, which is easy to dew for the same reason.

S-24C512C Rev.2.0_02_S  Precautions

• Set a by-pass capacitor of about 0.1 μF between the VCC and GND pin for stabilization.
• Do not apply an electrostatic discharge to this IC that ex ceeds the performance ratings of the built-in electrostatic protection circuit.
• SII Semiconductor Corporation claims no responsibility for any and all disputes arising out of or in connection with any infringement of the products including this IC upon patents owned by a third party.  Product Name Structure 1. Product name S-24C512C I − xxxx U 4 Environmental code U: Lead-free (Sn 100%), halogen-free Product name S-24C512C : 512 K-bit Fixed Package name (abbreviation) and IC packing specification J8T1: 8-Pin SOP (JEDEC), Tape T8T1: 8-Pin TSSOP, Tape 2. Packages Package name Drawing code Package Tape Reel 8-Pin SOP (JEDEC) FJ008-Z-P-SD FJ008-Z-C-SD FJ008-Z-R-SD 8-Pin TSSOP FT008-Z-P-SD FT008-Z-C-SD FT008-Z-R-SD

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