S24C01A

S24C01A SII | Alldatasheet

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Rev. 2.2_30 Seiko Instruments Inc. 1 The S-24C0XA is a series of 2-wired, low power 1K/2K/4K-bit EEPROMs with a wide operating range. They are organized as 128-word × 8-bit, 256-word × 8-bit, and 512-word × 8-bit, respectively. Each is capable of page write, and sequential read. The time for byte write and page write is the same, i. e., 1 msec. (max.) during operation at 5 V ± 10%. „ Package y 8-pin DIP (PKG drawing code : DP008-A,DP008-C) y 8-pin SOP (PKG drawing code : FJ008-D,FJ008-E) „ Pin Assignment Figure 1 „ Pin Functions Pin NumberName DIP SOP Function A0 11 Address input (no connection in the S-24C04A*) A1 22 Address input A2 33 Address input GND 44 Ground SDA 55 Serial data input/output SCL 66 Serial clock input TEST/WP 77 TEST pin (S-24C01A): Connected to GND. WP (Write Protection) pin (S-24C02A, S-24C04A): * Connected to Vcc: Protection valid * Connected to GND: Protection invalid VCC 88 Power supply CMOS 2-WIRE SERIAL EEPROM S-24C01A/02A/04A

• Endurance: 10 6 cycles/word
• Data retention: 10 years
• Write protection: S-24C02A, S-24C04A
• S-24C01A: 1 kbits
• S-24C02A: 2 kbits
• S-24C04A: 4 kbits „ Features
• Low power consumption Standby: 1.0 µA Max. (V CC=5.5 V) Operating: 0.4 mA Max. (V CC=5.5 V) 0.3 mA Max. (V CC=3.3 V)
• Wide operating voltage range Write: 2.5 to 5.5 V Read: 1.8 to 5.5 V
• Page write 8 bytes (S-24C01A, S-24C02A) 16 bytes (S-24C04A) 8-pin DIP Top view VCC GND SCL SDA A0 1 4 5 TEST/WP 8-pin SOP Top view GND TEST/WP VCC SCL SDA S-24C01ADPx-uu S-24C02ADPx-uu S-24C04ADPx-uu S-24C01AFJA-zz-uuw S-24C02AFJA-zz-uuw S-24C04AFJA-zz-uuw * Lower-case letters x, uu, zz and w differ depending on the packing form. See „ Ordering Information and „ Dimensions. * When in use, connect to GND or Vcc. Table 1

S-24C01A/02A/04A Rev. 2.2 _30 2 Seiko Instruments Inc. „ Block Diagram „ Absolute Maximum Ratings Parameter Symbol Ratings Unit Power supply voltage V CC -0.3 to +7.0 V Input voltage V IN -0.3 to VCC+0.3 V Output voltage V OUT -0.3 to VCC V Storage temperature under bias T bias -50 to +95 °C Storage temperature T stg -65 to +150 °C Figure 2 VCC GND Serial Clock Controller Device Address Comparator Address Counter Y Decoder Data Output ACK Output Controller High-Voltage Generator Start/Stop Detector Data Register EEPROM X Decoder Selector SCL SDA DIN DOUT R / W LOAD INC COMP LOAD TEST/WP* * S-24C02A or S-24C04A Table 2

Rev. 2.2_30 S-24C01A/02A/04A Seiko Instruments Inc. 3 „ Recommended Operating Conditions Table 3 Parameter Symbol Conditions Min. Typ. Max. Unit Read Operation 1.8 — 5.5 V Power supply voltage V CC Write Operation 2.5 — 5.5 V VCC=2.5 to 5.5V 0.7 ×VCC —V CC V High level input voltage V IH VCC=1.8 to 2.5V 0.8 ×VCC —V CC V VCC=2.5 to 5.5V 0.0 — 0.3 ×VCC V Low level input voltage V IL VCC=1.8 to 2.5V 0.0 — 0.2 ×VCC V Operating temperature T opr — -40 — +85 °C „ Pin Capacitance Table 4 (Ta=25°C, f=1.0 MHz, VCC=5 V) Parameter Symbol Conditions Min. Typ. Max. Unit Input capacitance C IN VIN=0 V (SCL, A0, A1, A2, WP) — — 10 pF Input/output capacitance C I / O VI / O=0 V (SDA) — — 10 pF „ Endurance Table 5 Parameter Symbol Min. Typ. Max. Unit Endurance N W 106 — — cycles/word

CMOS 2-WIRED SERIAL EEPROM S-24C01A/02A/04A Rev. 2.2 _30 4 Seiko Instruments Inc. „ DC Electrical Characteristics Table 6 Parameter Symbol Conditions Unit Current consumption (READ) ICC1 f=100 kHz —— 0.4 —— 0.3 —— 0.2 mA Current consumption (PROGRAM) ICC2 f=100 kHz —— 2.0 —— 1.5 ——— mA Table 7 Unit Standby current consumption ISB VIN=VCC or GND —— 1.0 —— 0.6 —— 0.4 µA Input leakage Output leakage Low level output voltage VOL Current address

CMOS 2-WIRED SERIAL EEPROM S-24C01A/02A/04A Rev. 2.2 _30 6 Seiko Instruments Inc. Table 10 VCC=4.5 to 5.5V V CC=2.5 to 4.5V Item Symbol Unit Write time t WR — 0.8 1.0 — 4.0 5.0 ms „ Pin Functions 1. Address Input Pins (A0, A1, and A2) Connect pins A0, A1, and A2 to the GND or the VCC, respectively, to assign slave addresses. There are 8 different ways to assign slave addresses in the S-24C01A and S-24C02A through a combination of pins A0, A1, and A2, and 4 ways to assign them in the S-24C04A through a combination of pins A1 and A2. When the input slave address coincides with the slave address transmitted from the master device, 1 device can be selected from among multiple devices connected to the bus. Always connect the address input pin to GND or V CC and leave it unchanged. 2. SDA (Serial Data Input/Output) Pin The SDA pin is used for bilateral transmission of serial data. It consists of a signal input pin and an Nch open-drain transistor output pin. Usually pull up the SDA line via resistance to the V CC, and use it with other open-drain or open-collector output devices connected in a wired OR configuration. 3. SCL (Serial Clock Input) Pin The SCL pin is used for serial clock input. It is capable of processing signals at the rising and falling edges of the SCL clock input signal. Make sure the rising time and falling time conform to the specifications. 4. TEST/WP Pin The S-24C01A does not have a write protection (WP) function. The pin serves as a TEST pin and shoud always be connect to the GND. In the S-24C02A and S-24C04A, this pin is used for write protection. When there is no need for write protection, connect the pin to the GND; when there is a need for write protection, connect the pin to the Vcc. Figure 5 Write Cycle SCL SDA D0 Write data Acknowledge Stop condition Start condition tWR

Rev. 2.2_30 S-24C01A/02A/04A Seiko Instruments Inc. 9 6. Write

6.1 Byte Write

When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code "0," following the start condition signal, it outputs the acknowledgment signal. Next, when the EEPROM receives an 8-bit length word address, it outputs the acknowledgment signal. After the EEPROM receives 8-bit write data and outputs the acknowledgment signal, it receives the stop condition signal. Next, the EEPROM at the specified memory address starts to rewrite. When the EEPROM is rewriting, all operations are prohibited and the acknowledgment signal is not output.

6.2 Page Write

Up to 8 bytes per page can be written in the S-24C01A and S-24C02A. Up to 16 bytes per page can be written in the S-24C04A. Basic data transmission procedures are the same as those in the "Byte Write." However, when the EEPROM receives 8-bit write data which corresponds to the page size, the page can be written. When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code "0," following the start condition signal, it outputs the acknowledgment signal. When the EEPROM receives an 8-bit length word address, it outputs the acknowledgment signal. After the EEPROM receives 8-bit write data and outputs the acknowledgment signal, it receives 8- bit write data corresponding to the next word address, and outputs the acknowledgment signal. The EEPROM repeats reception of 8-bit write data and output of the acknowledgment signal in succession. It is capable of receiving write data corresponding to the maximum page size. When the EEPROM receives the stop condition signal, it starts to rewrite, corresponding to the size of the page, on which write data, starting from the specified memory address, is received. Figure 10 Byte Write S T A R T 1 0 1 0 W R I T E S T O P DEVICE ADDRES WORD ADDRESS DATA R W M S B SDA ADR INC (ADDRESS INCREMENT) A2 A1 A0 W7W6W5W4W3W2W1W0 D7 D6 D5 D4 D3 D2 D1D0 A C K L S B A C K A C K W7 is optional in the S-24C01A. A0 is P0 in the S-24C04A.

CMOS 2-WIRED SERIAL EEPROM S-24C01A/02A/04A Rev. 2.2 _30 10 Seiko Instruments Inc. S T A R T 1 0 1 0 W R I T E S T O P DEVICE ADDRES WORD ADDRESS (n) DATA (n) R W M S B SDA LINE ADR INC A2A1A0 W7W6W5W4W3W2W1W0 D7D6 D5 D4 D3 D2 D1D0 A C K L S B A C K A C K

0 D7 D0 D7 D0

A C K ADR INC A C K DATA (n+1) DATA (n+x) W7 is optional in the S-24C01A. A0 is P0 in the S-24C04A. In the S-24C01A or S-24C02A, the lower 3 bits of the word address are automatically incremented each when the EEPROM receives 8-bit write data. Even if the write data exceeds 8 bytes, the upper 5 bits at the word address remain unchanged, the lower 3 bits are rolled over and overwritten. In the S-24C04A, the lower 4 bits at the word address are automatically incremented each when the EEPROM receives 8 bit write data. Even when the write data exceeds 16 bytes, the upper 4 bits of the word address and page address P0 remain unchanged, and the lower 4 bits are rolled over and overwritten.

6.3 Acknowledgment Polling

Acknowledgment polling is used to know when the rewriting of the EEPROM is finished. After the EEPROM receives the stop condition signal and once it starts to rewrite, all operations are prohibited. Also, the EEPROM cannot respond to the signal transmitted by the master device. Accordingly, the master device transmits the start condition signal and the device address read/write instruction code to the EEPROM (namely, the slave device) to detect the response of the slave device. This allows users to know when the rewriting of the EEPROM is finished. That is, if the slave device does not output the acknowledgment signal, it means that the EEPROM is rewriting; when the slave device outputs the acknowledgment signal, you can know that rewriting has been completed. It is recommended to use read instruction "1" for the read/write instruction code transmitted by the master device.

6.4 Write Protection

The S-24C02A and the S-24C04A are capable of protecting the memory. When the WP pin is connected to V CC, writing to 50% of the latter half of all memory area (080h to 0FFh in the S-24C02A; 100h to 1FFh in the S-24C04A) is prohibited. Even when writing is prohibited, since the controller inside the IC is operating, the response to the signal transmitted by the master device is not available during the time of writing (t WR). When the WP pin is connected to GND, the write protection becomes invalid, and writing in all memory area becomes available. However, when there is no need for using write protection, always connect the WP pin to GND. Figure 11 Page Write

Rev. 2.2_30 S-24C01A/02A/04A Seiko Instruments Inc. 11 7. Read

7.1 Current Address Read

The EEPROM is capable of storing the last accessed memory address during both writing and reading. The memory address is stored as long as the power voltage is more than the retention voltage V AH. Accordingly, when the master device recognizes the position of the address pointer inside the EEPROM, data can be read from the memory address of the current address pointer without assigning a word address. This is called "Current Address Read." "Current Address Read" is explained for when the address counter inside the EEPROM is an "n" address. When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code "1," following the start condition signal, it outputs the acknowledgment signal. However, in the S- 24C04A, page address P0 becomes invalid, and the memory address of the current address pointer becomes valid. Next, 8-bit length data at an "n" address is output from the EEPROM, in synchronization with the SCL clock. The address counter is incremented at the falling edge of the SCL clock by which the 8th bit of data is output, and the address counter goes to address n+1. The master device does not output the acknowledgment signal and transmits the stop condition signal to finish reading. For recognition of the address pointer inside the EEPROM, take into consideration the following: The memory address counter inside the EEPROM is automatically incremented for every falling edge of the SCL clock by which the 8th bit of data is output during the time of reading. During the time of writing, upper bits of the memory address (upper 5 bits of the word address in the S-24C01A and S-24C02A; upper 4 bits of the word address and page address P0 in the S-24C04A) are left unchanged and are not incremented. Figure 12 Current Address Read S T A R T 1 0 1 0 R E A D S T O P DEVICE ADDRESS R W M S B SDA LINE ADR INC A2 A1 A0 D7 D6 D5 D4 D3 D2 D1D0 A C K L S B DATA NO ACK from Master Device (A0 is P0 in the S-24C04A)

CMOS 2-WIRED SERIAL EEPROM S-24C01A/02A/04A Rev. 2.2 _30 12 Seiko Instruments Inc.

7.2 Random Read

Random read is a mode used when the data is read from arbitrary memory addresses. To load a memory address into the address counter inside the EEPROM, first perform a dummy write according to the following procedures: When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code "0," following the start condition signal, it outputs the acknowledgment signal. Next, the EEPROM receives an 8-bit length word address and outputs the acknowledgment signal. Last, the memory address is loaded into the address counter of the EEPROM. the EEPROM receives the write data during byte or page writing. However, data reception is not performed during dummy write. The memory address is loaded into the memory address counter inside the EEPROM during dummy write. After that, the master device can read the data starting from the arbitrary memory address by transmitting a new start condition signal and performing the same operation as that in the "Current Read." That is, when the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code "1," following the start condition signal, it outputs the acknowledgment signal. Next, 8-bit length data is output from the EEPROM, in synchronization with the SCL clock. The master device does not output an acknowledgment signal and transmits the stop condition signal to finish reading. S T A R T 1 0 1 0 W R I T E S T O P DEVICE ADDRESS WORD ADDRESS (n) R W M S B SDA LINE A2 A1 A0 W7W6W5W4W3W2W1W0 A C K L S B A C K A C K 0 1 0 1 0 A2 A1 A0 1 D7 D6 D5 D4 D3 D2 D1 D0 DATA (n) DUMMY WRITE DEVICE ADDRESS R E A D NO ACK from Master Device ADR INC S T A R T W7 is optional in the S-24C01A. A0 is P0 in the S-24C04A. Figure 13 Random Read

Rev. 2.2_30 S-24C01A/02A/04A Seiko Instruments Inc. 13

7.3 Sequential Read

When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code "1" in both current and random read operations, following the start condition signal, it outputs the acknowledgment signal When 8-bit length data is output from the EEPROM, in synchronization with the SCL clock, the memory address counter inside the EEPROM is automatically incremented at the falling edge of the SCL clock, by which the 8th data is output. When the master device transmits the acknowledgment signal, the next memory address data is output. When the master device transmits the acknowledgment signal, the memory address counter inside the EEPROM is incremented and read data in succession. This is called "Sequential Read." When the master device does not output an acknowledgement signal and transmits the stop condition signal, the read operation is finished. Data can be read in the "Sequential Read" mode in succession. When the memory address counter reaches the last word address, it rolls over to the first memory address. Figure 14 Sequential Read R E A D S T O P DEVICE ADDRES R W ADR INC D7 D0 A C K A C K A C K

1 D7 D0

A C K ADR INC SDA LINE DATA (n) D7 D0 D7 D0 DATA (n+1) DATA (n+2) DATA (n+x) NO ACK from Master Device ADR INC

CMOS 2-WIRED SERIAL EEPROM S-24C01A/02A/04A Rev. 2.2 _30 14 Seiko Instruments Inc. 8. Address Increment Timing The address increment timing is as follows. See Figures 15 and 16. During reading operation, the memory address counter is automatically incremented at the falling edge of the SCL clock (the 8th read data is output). During writing operation, the memory address counter is also automatically incremented at the falling edge of the SCL clock when the 8th bit write data is fetched.Figure 15 Address Increment Timing During Reading SCL SDA R / W=1 Address Increment 891 89 D7 Output D0 OutputACK Output Figure 16 Address Increment Timing During Writing SCL SDA R / W=0 891 89 D7 Input D0 InputACK Output ACK Output Address Increment Purchase of I2C components of Seiko Instruments Inc. conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Please note that any product or system incorporating this IC may infringe upon the Philips I2C Bus Patent Rights depending upon its configuration. In the event that such product or system incorporating the I 2C Bus infringes upon the Philips Patent Rights, Seiko Instruments Inc. shall not bear any responsibility for any matters with regard to and arising from such patent infringement.

Rev. 2.2_30 S-24C01A/02A/04A Seiko Instruments Inc. 15 „ Ordering Information S-24C0xA yyy - zz - uuw P code (Distincion for package process) None S Endurance code 11 : 10 6 cycles Taping specification None for DIP and SOP in magazine TB Package code DP : DIP DPA : DIP FJA : SOP Product name S-24C01A : 1k bits S-24C02A : 2k bits S-24C04A : 4k bits Ordering names for DIP Product name Package code Taping specification Endurance code P code Package/Tape/Reel drawings DP None None −1A DP008-C S-24C01A S-24C02A S-24C04A DPA None −11 None DP008-A Note The endurarance of S-24C0xADP-1A is 106 cycles, though the ordering name does not have the endurance code. Ordering names for SOP Product name Package code Taping specification Endurance code P code Package/Tape/Reel drawings S-24C01A FJA −TB (None for magazine) −11 None FJ008-D None FJ008-D S-24C02A FJA −TB (None for magazine) −11 S FJ008-D FJ008-E S-24C04A FJA −TB (None for magazine) −11 None FJ008-D Note 1) Package dimensions of SOPs whose package code is FJA are the same in the range of deviation. 2) Please contact an SII local office or a local representative for details.

CMOS 2-WIRED SERIAL EEPROM S-24C01A/02A/04A Rev. 2.2 _30 16 Seiko Instruments Inc. „ Characteristics 1. DC Characteristics

1.1 Current consumption (READ) I CC1 —

1.2 Current consumption (READ) I CC1 —

1.3 Current consumption (READ) I CC1 —

1.4 Current consumption (READ) I CC1 —

1.5 Current consumption (READ) I CC1 —

1.6 Current consumption (READ) I CC1 −

1.7 Current consumption (PROGRAM) I CC2 −

1.8 Current consumption (PROGRAM) I CC2 −

Ta (°C) 200 100 VCC=5.5 V fscl=100 KHz DATA=0101 0 -40 0 85 I CC1 (µA) Ta (°C) 200 100 VCC=3.3 V fscl=100 KHz DATA=0101 0 -40 0 85 I CC1 (µA) Ta (°C) VCC=1.8 V fscl=100 KHz DATA=0101 -40 0 85 ICC1 (µA) 100 2 3 45 67 Ta=25°C fscl=100 KHz DATA=0101 VCC (V) ICC1 (µA) 100 23456 7 Ta=25°C fscl=400 KHz DATA=0101 VCC (V) 100 ICC1 (µA) VCC=5.0 V Ta=25°C 100K 200K fscl(Hz) ICC1 (µA) 300K 400K Ta (°C) 1.0 0.5 VCC=5.5 V 0 -40 0 85 ICC2 (mA) Ta (°C) 1.0 0.5 VCC=3.3 V 0 -40 0 85 ICC2 (mA)

Rev. 2.2_30 S-24C01A/02A/04A Seiko Instruments Inc. 17

1.10 Current consumption (PROGRAM) I CC2 −

1.11 Standby current consumption I SB —

1.12 Input leakage current I LI −

1.13 Input leakage current I LI −

1.14 Output leakage current I LO −

1.15 Output leakage current I LO −

1.9 Current consumption (PROGRAM) I CC2 −

Ta (°C) 1.0 0.5 VCC=2.5 V 0 -40 0 85 ICC2 (mA) 1.0 0.5 0 23456 7 Ta=25°C VCC (V) ICC2 (mA) 10-6 10-7 10-8 10-9 10-10 VCC=5.5 V 10-11 Ta (°C) -40 0 85 Ta (°C) 1.0 0.5 VCC=5.5 V A0, A1, A2, SDA SCL,TEST/WP=0V -40 0 85 ILI (µA) ISB (A) Ta (°C) 1.0 0.5 VCC=5.5 V SDA=0V -40 0 85 ILO (µA) Ta (°C) 1.0 0.5 -40 0 85 VCC=5.5 V A0, A1, A2, SDA SCL, TEST/WP=5.5V ILI (µA) Ta (°C) 1.0 0.5 VCC=5.5 V SDA=5.5 V -40 0 85 ILO (µA)

CMOS 2-WIRED SERIAL EEPROM S-24C01A/02A/04A Rev. 2.2 _30 18 Seiko Instruments Inc.

1.20 High input inversion voltage VIH −

1.16 Low level output voltage V OL −

1.17 Low level output voltage V OL −

1.18 Low level output current I OL −

1.19 Low level output current I OL −

1.21 High input inversion voltage VIH −

1.22 Low input inversion voltage VIL −

1.23 Low input inversion voltage VIL −

Ta (°C) 0.3 0.2 VCC=4.5 V IOL=2.3 mA -40 0 85 VOL (V) 0.1 Ta (°C) 0.03 0.02 VCC=1.8 V IOL=100 µA -40 0 85 VOL (V) 0.01 Ta (°C) VCC=4.5 V VOL=0.45 V -40 0 85 IOL (mA) Ta (°C) 1.0 0.5 VCC=1.8 V VOL=0.1 V 0 -40 0 85 IOL (mA) Ta=25°C A0, A1, A2, SDA SCL, TEST/WP 1.0 2.0 3.0 VIH (V) 1 23 4567 VCC (V) VCC=5.0 V A0, A1, A2, SDA SCL, TEST/WP 1.0 2.0 3.0 VIH (V) Ta (°C) -40 08 5 Ta=25°C A0, A1, A2, SDA SCL, TEST/WP 1.0 2.0 3.0 VIL (V) 123 456 7 VCC (V) 1.0 2.0 3.0 VIL (V) Ta (°C) -40 08 5 Ta=5.0V A0, A1, A2, SDA SCL, TEST/WP

Rev. 2.2_30 S-24C01A/02A/04A Seiko Instruments Inc. 19 2. AC Characteristics

2.1 Maximum operating frequency fmax −

2.2 Write time t WR −

2.3 Write time t WR −

2.4 Write time t WR −

2.5 SDA output delay time t PD −

2.6 SDA output delay time t PD −

2.7 Data output delay time t PD −

Ta=25°C VCC (V) fmax (Hz) 23456 7 Ta=25°C VCC (V) tWR (ms) 100K Ta (°C) 1.5 1.0 VCC=4.5 V -40 0 85 0.5 tWR (ms) Ta (°C) VCC=2.5 V -40 0 85 tWR (ms) Ta (°C) 1.5 1.0 VCC=4.5 V -40 0 85 0.5 tPD (µs) Ta (°C) 1.5 1.0 VCC=2.7 V -40 0 85 0.5 tPD (µs) Ta (°C) 3.0 2.0 VCC=1.8 V -40 0 85 1.0 tPD (µs)

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