SI3226 SILABS | Alldatasheet

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Technical content

Features

Applications

Description

The Dual ProSLIC ® is a family of low-voltage CMOS devices that integrate both SLIC and CODEC functionality into a sing le IC. In combination with a linefeed IC (LFIC), they provide a complete tw o-channel analog telephone interface in accordance with all relevant LSSGR, IT U, and ETSI specifications. The Dual ProSLIC devices (Si3226/7) operate from a single 3.3 V supply and interface to standard PCM/SPI or GCI bus digital interfaces. The LFICs (Si3208/9) perform all high-voltage functions and operate from a 3.3 V supply as well as high-voltage battery supplies. The Si3208 is rated for –110 V, and the Si3209 is rated for – 135 V. The Dual ProSLIC devices are available in a 64-pin thin quad flat package (TQFP), and the LFICs are available in a 40-pin, quad flat no-lead package (QFN). Functional Block Diagram „ Performs all BORSCHT functions „ Ideal for short- or long-loop applications „ Internal balanced or unbalanced ringing „ Low power consumption „ Software-programmable parameters: z Ringing frequency, amplitude, cadence, and waveshape z Two-wire ac impedance z Transhybrid balance z DC current loop feed (10–45 mA) z Loop closure and ring trip thresholds z Ground key detect threshold „ Integrated dc-dc controller „ Wideband CODEC (Si3227) „ Low-power sleep mode „ On-hook transmission „ Loop or ground start operation „ Smooth polarity reversal „ DTMF generator/decoder „ A-Law/µ-Law companding, linear PCM „ PCM and SPI bus digital interfaces with programmable interrupts „ GCI/IOM-2 mode support „ 3.3 V operation „ GR-909 loop diagnostics „ Audio diagnostics with loopback „ Pb-free/RoHS-compliant packaging „ Customer Premises Equipment (CPE) „ Optical Network Terminals (ONT) „ Private Branch Exchange (PBX) „ Cable EMTAs, ATAs, VoIP Gateways Linefeed RING TIP RING TIP Linefeed SPI Control Interface PCM/ GCI Interface DSP DTMF & Tone Gen Programmable AC Impedance and Hybrid Caller ID Ringing Generator ADC DAC CODEC ADC DAC CODEC SLIC Linefeed Control Linefeed Monitor SLIC Linefeed Control Linefeed Monitor Channel 1 Channel 2 DC-DC Controller Line Diagnostics PLLPCLK FSYNC DRX DTX CS SDI SDO SCLK INT RST Si3226 Si3206 DC-DC BOMVDC VBAT Linefeed RING TIP RING TIP Linefeed SPI Control Interface PCM/ GCI Interface DSP DTMF & Tone Gen Programmable AC Impedance and Hybrid Caller ID Ringing Generator ADC DAC CODEC ADC DAC CODEC ADC DAC CODEC ADC DAC CODEC SLIC Linefeed Control Linefeed Monitor SLIC Linefeed Control Linefeed Monitor Channel 1 Channel 2 DC-DC Controllers Line Diagnostics PLLPCLK FSYNC DRX DTX CS SDI SDO SCLK INT RST Si3226/7 DC-DC BOMVDC VBAT Si3208/9 Patents pending

Ordering Information

See page 33.

2 Preliminary Rev. 0.33

Preliminary Rev. 0.33 3 TABLE OF C ONTENTS Section Page

  1. Electrical Specifications

Table 1. Absolute Maximum Ratings and Thermal Information1

  1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operational sections of this data sheet.

  1. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout

copper surface and a large internal/bottom copper plane.

  1. Operation of the Si3226 or Si3227 above 125 °C junction temperature may degrade device reliability.
  2. Si3208 and Si3209 are equipped with on-chip thermal limiting circuitry that shuts down the circuit when the junction

the Si3208/Si3209 above 150 °C junction temperature should be avoided.

  1. The dv/dt of the voltage applied to the VBAT pins must be limited to 10 V/µs.

Table 2. Recommended Operating Conditions *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. Table 3. 3.3 V Power Supply Characteristics1

  1. All specifications are for a single channel of Si3226/7 using Si3208/9 linefeed IC and based on measurements with all

channels in the same operating state.

  1. ILOOP is the dc current in the subscriber loop during the off-hook state.
  2. IAVE is the average of the full-wave rectified current in the subscriber loop during ringing (IAVE = IPEAK x 2/π).

Table 4. AC Characteristics

1014 Hz, Any gain setting

  1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should

be –10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.

  1. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
  2. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
  3. VDD1–VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors; RL = 600 Ω, ZS =6 0 0Ω synthesized using RS register
  4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.

200 Hz to 1 kHz 58 60 — dB

Table 4. AC Characteristics (Continued)

  1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should

be –10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.

  1. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
  2. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
  3. VDD1–VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors; RL = 600 Ω, ZS =6 0 0Ω synthesized using RS register
  4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.

Table 5. Linefeed Characteristics

20 V dc offset, ITH =1 3m A

48 V DC offset, Rloop = 1500 Ω

5 REN load, RLOOP =0 Ω,

*Note: Ringing amplitude is set for 93 V peak and measured at TIP-RING using no series protection resistance.

Table 6. Monitor ADC Characteristics Table 7. Si3208/Si3209 Characteristics Table 5. Linefeed Characteristics (Continued) *Note: Ringing amplitude is set for 93 V peak and measured at TIP-RING using no series protection resistance.

Table 8. DC Characteristics Table 9. Switching Characteristics—General Inputs 1

  1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are

VIH =V DD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.

  1. The minimum RESET pulse width assumes the SDITHRU pin is tied to ground via a pulldown resistor no greater than

Figure 1. SPI Timing Diagram Table 10. Switching Characteristics—SPI

Table 11. Switching Characteristics—PCM Highway Interface

  1. FSYNC source is assumed to be 8 kHz under all operating conditions.
  2. Spec applies to PCLK fall to DTX tristate when that mode is selected.

Figure 2. PCM Highway Interface Timing Diagram Table 12. Switching Characteristics—GCI Highway Serial Interface Rise and fall times are referenced to the 20% and 80% levels of the waveform.

  1. FSYNC source is assumed to be 8 kHz under all operating conditions.
  2. Specification applies to PCLK fall to DTX tristate when that mode is selected.
  1. Typical Application Circuits

Figure 7. Si3226/7 (2 Lines)

1) Component values and ratings are shown in the bill of materials. 2) Vin and Vout are defined in the bill of materials. Figure 8. DC-DC Converter (A)

1) Component values and ratings are shown in the bill of materials. 2) Vin and Vout are defined in the bill of materials. Figure 9. DC-DC Converter (B)

All Resistors are 1% unless otherwise noted. Figure 10. Linefeed (2 Lines)

Table 13. Bill of Materials for Si3226/7 (2 Lines)

1 L1* 10 µH 180 mA ±10% IND-NLC3225 TDK

4 R13, R15, R16, R19 10 k Ω 1/10 W ±5% RC0603 Venkel

2 R100, R200 825 k Ω 1/10 W, 100 V ±1% RC0805 Venkel

1 U1 Si3226 TQFP64 SiLabs

*Note: Denotes optional component.

Table 14. Bill of Materials for Linefeed and DC-DC Converters with |VOUT| < 90 V (2 Lines)

1 C120 10 µF 25 V ±20% X7R CC1210 Venkel

1 C220* 10 µF 25 V ±20% X7R CC1210 Venkel

4 C127, C128, C227, C228 470 pF 25 V ±10% X7R CC0402 Venkel

2 D122, D222 BAS21HT1 250 V,200 mA SOD-323 ON SEMI

2 L120, L220 15 µH CDR74 SUMIDA

2 Q120, Q220 FQT7N10 100 V, 2 W SOT-223 Fairchild

2 R122, R222 15 Ω 1/4 W ±5% RC1206 Venkel

2 R123, R223 220 Ω 1/16 W ±5% RC0402 Venkel

2 R124, R224 1 k Ω 1/16 W ±5% RC0402 Venkel

2 R125, R225 150 k Ω 1/16 W ±5% RC0402 Venkel

2 R126, R226 100 k Ω 1/16 W ±5% RC0402 Venkel

2 R127, R227 2 Ω 1/8 W ±5% RC0402 Venkel

*Note: Denotes optional component.

4 C101, C102, C201, C202 10 nF 100 V ±10% X7R CC0805 Venkel

4 C103, C104, C203, C204 10 nF 100 V ±10% X7R CC0805 Venkel

4 R101, R102, R201, R202 681 k Ω 1/10 W, 150 V ±1% RC0805 Venkel

4 R103, R104, R203, R204 301 k Ω 1/16 W, 75 V ±1% RC0603 Venkel

2 R105, R205 590 k Ω 1/10 W, 150 V ±1% RC0805 Venkel

1 U100 Si3208 or

Table 14. Bill of Materials for Linefeed and DC-DC Converters with |VOUT| < 90 V (2 Lines) (Continued) *Note: Denotes optional component.

Table 15. Bill of Materials for Linefeed and DC-DC Converters with |VOUT| < 135 V (2 Lines)

2 L120, L220 15 µH CDRH125 SUMIDA

*Note: Denotes optional component.

4 C101, C102, C201, C202 10 nF 200 V ±10% X7R CC0805 Venkel

1 U100 Si3209 QFN- 40 Silicon Laboratories

Table 15. Bill of Materials for Linefeed and DC-DC Converters with |VOUT| < 135 V (2 Lines) (Continued) *Note: Denotes optional component.

voltage IC and the Si3208/9 high-voltage linefeed IC. voltages up to 110 V, sufficient for most ringing signals. higher-voltage ringing applications. and to reduce external controller requirements. integrated, including ac impedance and hybrid gain. single hardware design to meet global requirements. bus. Control data is transferred using a standard SPI. in a 40-pin QFN or a 48-pin eTQFP. completely programmable dc feed characteristics. voltage region has a low resistance, typically 160 Ω. Figure 11. Dual ProSLIC DC Feed programmable operating states as listed in Table 16. is reflected in a Si3226/7 register bit.

automatic intervention are described below.

  1. LFIC total power exceeded.
  2. Power exceeded in one or more transistors of a LFIC

individual power consumption).

  1. Excessive foreign current or voltage on TIP and/or
  2. LFIC thermal shutdown event; this event is

a maskable interrupt bit is also provided. Table 16. Linefeed Operating States feed testing. A power fault condition may also force the device into the open state. TIP lead. Loop closure and ground key detect circuitry are active. lead is more positive than the TIP lead. detect circuitry are active. detect circuitry are active. Ringing Drives programmable ringing signal onto TI P and RING leads with or without dc offset. special diagnostic resources available.

Preliminary Rev. 0.33 27 Si3226/7 Si3208/9 4.8. Ground Key Detection The Dual ProSLIC provides a ground key detect mechanism using a programmable architecture similar to the loop closure scheme. The ground key detect scheme provides two unique thresholds to allow hysteresis and also includes a programmable debounce filter to eliminate false detection. A ground key detect status bit provides contin uous status, and a maskable interrupt bit is also provided. 4.9. Ringing Generation The Dual ProSLIC provides the ability to generate a programmable sinusoidal or trapezoidal ringing waveform, with or without dc offset. The ringing frequency, wave shape, cadence, and offset are all register-programmable. Using a balanced ringing scheme, the ringing signal is applied to both the TIP and RING leads using dual ringing waveforms that are 180° out of phase with each other. The resulting ringing signal seen across TIP-RING is twice the amplitude of the ringing waveform on either the TIP or RING lead, which allows the ringing ci rcuitry to be forced to withstand only half the total ringing amplitude seen across TIP-RING. 4.10. Polarity Reversal The Dual ProSLIC supports polarity reversal for message waiting and various other signaling modes. The ramp rate can be programmed for a smooth or abrupt transition to accommodate different application requirements. 4.11. Two-Wire Impedance Synthesis The ac two-wire impedance synthesis is generated on- chip using a DSP-based scheme to optimally match the output impedance of the Dual ProSLIC to the impedance of the subscriber loop and minimize the receive path signal reflected back onto the transmit path. Most real or complex two-wire impedances can be generated by using the coefficient generator software to simulate the desired line conditions and generate the required register coefficients. 4.12. Transhybrid Balance Filter The trans-hybrid balance function is implemented on- chip using a DSP-based scheme to effectively cancel the reflected receive path signal from the transmit path. The coefficient generator software is used to optimize the filter coefficients. 4.13. Tone Generators The Dual ProSLIC includes two digital tone generators that allow a wide variety of single- or dual-tone frequency and amplitude combinations. Each tone generator has its own set of registers that hold the desired frequency, amplitude, and cadence to allow generation of DTMF and call progress tones for different requirements. The tones can be directed to either receive or transmit paths. 4.14. DTMF Detection In DTMF, two tones generate a DTMF digit. One tone is chosen from the four possible row tones, and one tone is chosen from the four possible column tones. The sum of these tones constitutes one of 16 possible DTMF digits. The Dual ProSLIC performs DTMF detection using an algorithm to compute the DFT for each of the eight DTMF frequencies and their second harmonics. At the end of the DFT computation, the squared magnitudes of the DFT results for the 8 DTMF fundamental tones are computed. The row and column results are sorted to determine the strongest tones, and checks are made to determine if the strongest row and column tones constitute a DTMF digit. 4.15. DC-DC Controller The controller converts a single positive dc input voltage into an independent negative battery voltage for each channel. The controller operates a dc-dc converter circuit that converts a sing le positive dc input voltage into an independent negative battery voltage for each channel. In addition to eliminating external high-voltage power supplies, the dc-dc controller allows the Dual ProSLIC to dynamically control the battery voltage to the minimum required for any given operating state according to the programmed linefeed parameters. 4.16. Wideband Audio The Si3226 supports a narrowband (200 Hz–3.4 kHz) audio codec. The Si3227 supports a software- selectable wideband (50 Hz–7 kHz) and narrowband (200 Hz–3.4 kHz) audio codec. The Si3227 wideband mode provides an expanded audio band at a 16-bit, 16 kHz sample rate for enhanced audio quality while maintaining standard tele phony audio compatibility. Wideband audio samples are transmitted and received on the PCM interface using two consecutive 8 kHz frames.

28 Preliminary Rev. 0.33 4.17. SPI Control Interface The controller interface to the Dual ProSLIC is a 4-wire interface modeled after microcontroller and serial peripheral devices. The interface consists of a clock (SCLK), chip select (CS), serial data input (SDI), and serial data output (SDO). In addition, the Dual ProSLIC devices feature a serial data through output (SDITHRU) to support operation of up to eight devices (up to 16 channels) using a single ch ip select line. The device operates with both 8-bit and 16-bit SPI controllers. 4.18. PCM Interface and Companding The Dual ProSLIC contains a flexible, programmable interface for the transmission and reception of digital PCM samples. PCM data tran sfer is controlled by the PCM clock (PCLK) and frame sync (FSYNC) inputs as well as the PCM Mode Select, PCM Transmit Start, and PCM Receive Start settings. The interface can be configured to support from four to 128 8-bit time slots in each 125 µs frame, corresponding to a PCM clock (PCLK) frequency range of 256 kHz to 8.192 MHz. 1.544 MHz is also supported. The Dual ProSLIC supports both µ-255 Law (µ-Law) and A-law companding formats in addition to 16-bit linear data mode with no companding. 4.19. General Circuit Interface The Dual ProSLIC supports an alternative communication interface to the SPI and PCM control and data interface. The General Circuit Interface (GCI) is used for transmission and reception of both control and data information onto a GCI bus. The PCM and GCI interfaces are both 4-wire interfaces and share the same pins. In GCI mode, the four-wire SPI control interface is used as hard- wired channel selector pins. The selection between PCM and GCI modes is performed when coming out of reset using the SDITHRU pin. 4.20. Metallic Loop Testing The Dual ProSLIC includes the ability to detect multiple fault conditions within the line card as well as on the T/R pair. 1. Hazardous Potential Test—T his test checks for ac voltage >50 V rms or dc voltage >135 V on T-G or R- G. If a hazardous voltage is encountered, test access MUST release within two seconds of the time when it was initiated using a preset threshold. 2. Foreign ElectroMotive Force Test—Checks T-G or R-G for ac voltage >10 V rms, dc voltage >6 V. Uses same threshold as for hazardous voltage test. 3. Resistive Faults Test—Checks for dc resistance from T-R, T-G or R-G. Any measurement <150 kΩ is considered a resistive fault. 4. Receiver-Off-Hook Test—Distinguishes between a T-R resistive fault and an off-hook condition. 5. Ringers Test—Checks for the presence of REN across T-R. Result are >0.175REN and <5REN for a valid load. 6. AC Line Impedance (line length)—T-R, T-G, and R-G. Generate a tone at several specific frequencies (audio band) and measure the reflected signal amplitude (complex spectrum) that comes back (with transhybrid balance filter disabled). The reflected signal is then used to calculate the line impedance based on certain assumptions of wire gauge, etc. 7. Line Capacitance—T-R, T-G, R-G. Generate a linear ramp function with polarity reversal, and measure the time constant. 8. Ringer Capacitance—This test uses the same procedure as the ringer test above but also measures the V/I phase relationship of the received signal (dc path) and then subtracts the delay to calculate the ringer capacitance. 9. Ringing Voltage Verification—Uses current voltage sensing capability. 10.Test-In Diagnostics—The Dual ProSLIC can switch in a preset load impedance to test the SLIC/codec functionality using a known set of conditions.

  1. Pin Descriptions: Si3226/7

Table 17. Si3226/7 Pin Descriptions 1 SRINGDCa I RING DC Sense Input. 2 SRINGACa I RING AC Sense Input. 3 STIPACa I TIP AC Sense Input. 4 STIPDCa I TIP DC Sense Input. 5 CAPPa I/O Metallic Loop Filter Ca pacitor-Positive Terminal. 6 CAPMa I/O Metallic Loop Filter Ca pacitor-Negative Terminal. 7 SVBATa I Battery Sensing Input. 8 SVDC I DC-DC Input Power Rail Sensor. 9 GPIO3a / PWROa I/O General Purpose I/O / Power Offloading Output.

10 GPIO2a / SRINGCa /

11 GPIO1a / STIPCa / TRD1a I/O General Purpose I/O / TIP Course Sense Input / Test Relay

13 FSYNC I Frame Sync Clock Input. 14 SDI I Serial Port Data Input. 15 HVCLKa O Line-Driver IC Clock Output. 16 SCLK I Serial Port Bit Clock Input.

17 HVDATA O Line-Driver IC Data Output

18 SDITHRU O Serial Data Daisy Chain Output. 19 SDO O Serial Port Data Output. 20 DCFFa I/O DC-DC BJT Drive Monitor. 21 SDCHa I DC-DC Current Moni tor Input-High Terminal. 22 SDCLa I DC-DC Current Moni tor Input-Low Terminal. 23 DCDRVa I/O DC-DC Drive Output. 24 VDDC PWR DC-DC Switch Driver Power Supply. 25 DCDRVb O DC-DC Drive Output. 26 SDCLb I DC-DC Current Moni tor Input-Low Terminal. 27 SDCHb I DC-DC Current Moni tor Input-High Terminal. 28 DCFFb I/O DC-DC BJT Drive Monitor. 30 VDDD PWR Digital Supply Voltage. 31 PCLK I PCM Bus Clock Input. 32 HVCLKb O Line-Driver IC Clock Output.

33 DTXEN O Transmit PCM Enable Output. 34 DTX O Transmit PCM Data Output. 35 DRX I Receive PCM Data Input.

36 INT

38 VDDREG I/O Regulated Core Power Supply.

39 GPIO1b / STIPCb / TRD1b I/O General Purpose I/O / TIP Course Sense Input / Test Relay

40 GPIO2b / SRINGCb /

41 GPIO3b / PWROb I/O General Purpose I/O / Power Offloading Output. 42 SVBATb I Battery Sensing Input. 43 CAPMb I/O Differential Loop Filt er Capacitor-Negative Term. 44 CAPPb I/O Differential Loop Filt er Capacitor-Positive Term. 45 STIPDCb I TIP DC Sense Input. 46 STIPACb I TIP AC Sense Input. 47 SRINGACb I RING AC Sense Input. 48 SRINGDCb I RING DC Sense Input. 49 DRINGb O RING Pull-Down Current Driver Output. 50 URINGb O RING Pull-Up Cu rrent Driver Output. 51 DTIPb O TIP Pull-Down Cu rrent Driver Output. 52 UTIPb O TIP Pull-Up Current Driver Output. 53 IBIASb O Line Driver IC Bias Current Output. 54 CAPLB O Longitudinal Balanc e Calibration Capacitor. 55 IREF I Current Reference Input. 56 QGND I Quiet Ground Reference Input. 58 VDDA PWR Analog Supply Voltage. 59 ISNS I/O Line Current Sense Input. 60 IBIASa O Line Driver IC Bias Current Output. 61 UTIPa O TIP Pull-Up Current Driver Output. 62 DTIPa O TIP Pull-Down Cu rrent Driver Output. 63 URINGa O RING Pull-Up Cu rrent Driver Output. 64 DRINGa O RING Pull-Down Current Driver Output. Table 17. Si3226/7 Pin Descriptions (Continued)

  1. Pin Descriptions: Si3208/9

Table 18. Si3208/9 Pin Descriptions 1 IC Internal connection; leave to float. 3 RING_1 I/O Ring Channel 1 Input/Output. 5 TIP_1 I/O Tip Channel 1 Input/Output. 7 IC Internal connection; leave to float. 8 IRINGN_1 I Negative Ring Current Control Channel 1 Input. 9 IRINGP_1 I Positive Ring Curr ent Control Channel 1 Input. 10 ITIPN_1 I Negative Tip Current Control Channel 1 Input. 11 ITIPP_1 I Positive Tip Current Control Channel 1 Input. 12 IBIAS_1 I Current Bias Channel 1 Input. 13 ISNS O Current Sense Output. 14 VDD I IC Supply Voltage Input. 15 HVCLK_1 I High-Voltage IC Clock Channel 1 Input. 16 HVDATA I/O High-Voltage IC Data Input/Output. 17 HVCLK_2 I High-Voltage IC Clock Channel 2 Input. 19 IBIAS_2 I Current Bias Channel 2 Input. 20 ITIPP_2 I Positive Tip Current Control Channel 1 Input. 21 ITIPN_2 I Negative Tip Current Control Channel 2 Input. 22 IRINGP_2 I Positive Ring Curr ent Control Channel 2 Input. 23 IRINGN_2 I Negative Ring Current Control Channel 2 Input. 24 IC Internal connection; leave to float. 26 TIP_2 I/O Tip Channel 2 Input/Output. 28 RING_2 I/O Ring Channel 2 Input/Output. 30 IC Internal connection; leave to float. 31 IC Internal connection; leave to float. 32 VBAT_2 I Operating Battery Voltage Channel 2 Input. 34 IC Internal connection; leave to float.

37 IC Internal connection; leave to float. 38 IC Internal connection; leave to float. 39 VBAT_1 I Operating Battery Voltage Channel 1 Input. 40 IC Internal connection; leave to float. epad Exposed Die Attach Paddle. Table 18. Si3208/9 Pin Descriptions (Continued)

Preliminary Rev. 0.33 33 7. Ordering Guide Device Description Wideband Audio Package Temp Range Si3226-X-FQ Dual ProSLIC No TQFP-64 0 to 70 °C Si3226-X-GQ Dual ProSLIC No TQFP-64 –40 to 85 °C Si3227-X-FQ Dual ProSLIC Yes TQFP-64 0 to 70 °C Si3227-X-GQ Dual ProSLIC Yes TQFP-64 –40 to 85 °C Si3208-X-FM 110 V Dual LFIC — QFN-40 0 to 70 °C Si3208-X-GM 110 V Dual LFIC — QFN-40 –40 to 85 °C Si3209-X-FM 135 V Dual LFIC — QFN-40 0 to 70 °C Si3209-X-GM 135 V Dual LFIC — QFN-40 –40 to 85 °C Notes: 1. All devices are lead-free and RoHS compliant. 2. “X” denotes product revision (A, B, C, etc.). 3. Add an R at the end of the device to denote tape and reel options.

Table 19. 64-Pin TQFP Package Dimensions

  1. All dimensions shown are in millimeters (mm) unless otherwise noted.
  2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
  3. This package outline conforms to JEDEC MS-026, variant ACD.
  4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C

specification for small body components.

Preliminary Rev. 0.33 37 Si3226/7 Si3208/9 DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.32 „ Added Si3208 and Si3209. „ Removed Si3203, Si3205, and Si3206. „ Added pin-outs and package drawings for Si3208 and Si3209. „ Updated pin-out for Si3226. „ Updated bill of materials. „ Updated “2. Typical Application Circuits” and added dc-dc converter schematics. „ Updated tables. Revision 0.32 to Revision 0.33 „ Changed package type for Si3208. „ Deleted QFN-32 drawing. „ Updated dc-dc converter schematic. „ Updated bills of materials. „ Updated max VBAT values. „ Updated thermal shutdown thresholds. „ Updated Si3208/9 pin descriptions.

38 Preliminary Rev. 0.33 CONTACT INFORMATION Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ProSLICinfo@silabs.com Internet: www.silabs.com Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.