R2600 RDC | Alldatasheet

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RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 1 of 6 REV 1.0 Jul. 18 2005 RR22660000 BBrriieeff SShheeeett FFAASSTT EETTHHEERRNNEETT RRIISSCC PPRROOCCEESSSSOORR

RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 2 of 6 REV 1.0 Jul. 18 2005 1. Features l CPU Core - RDC’s proprietary RISC architecture - Five-stage pipeline architecture - Operation frequency: 100MHz - Supports a 8K-byte uniform cache l ROM/RAM/SDRAM Controller and Addressing Space - Supports 16-bit data bus width - Flash ROM/SRAM control interface - SDRAM control interface - 16M addressing space - 64K-byte I/O space l Two Independent DMA Controllers - Supports high-speed DMA transfers l Interrupt Controller - Provides 8 maskable external interrupt channels l Counter/Timers - Three independent programmable 16-bit timers - One programmable watchdog timer which can generate NMI or reset. l High Performance UART Ports - Supports 2 high performance UARTs with send/receive 16-byte FIFOs - Programmable baud rate generator - The data rates are programmable from 50 to 460.8K baud (max. to 1Mbps) - The character options are programmable for 1 start bit; 1, 1.5 or 2 stop bits; even, odd or no parity, 5~8 data bits l RDC Debug Tool Support - RDC debug tool with a JTAG-like interface l General Programmable I/O - 48 programmable I/O ports mixed with other functions - 8 dedicated GPIOs for WLAN block - Pins individually configurable to input or output mode l Two 10/100M Fast Ethernet MAC Ports - IEEE 802.3u MII interface - IEEE 802.3x flow control in full-duplex mode - Internal loop-back self-test circuit support - Descriptor architecture for packet TX/RX l PCI Control Interface Support - Supports up to 3 PCI masters - Speed up to 33MHz l Two Card Bus Interface Support l IEEE 802.11b/g WLAN Support - Security: 64/128 WEP, WPA, AES - Advanced power saving algorithm for dynamic network traffic environment - On-chip A/D and D/A Converters for I/Q data, TSSI and AGCs. - Supports 6, 9, 12, 18, 24, 36, 48, 54 Mbps for OFDM; 5.5, 11Mbps for CCK; and 1,2 Mbps for barker

RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 3 of 6 REV 1.0 Jul. 18 2005 modulation. - Supports short preamble and antenna diversity - Proprietary robust demodulator with patent protection - Mitigates multipath delay spread up to 100ns at 54Mbps - 2 configurable LEDs to release CPU from LED routine loading l A Lead-free Product

RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 4 of 6 REV 1.0 Jul. 18 2005 2. Block Diagram

RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 5 of 6 REV 1.0 Jul. 18 2005 3. Package Information

RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 6 of 6 REV 1.0 Jul. 18 2005