R1620

R1620 RDC | Alldatasheet

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RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 1 of 5 REV 1.0 Sep. 20 2006 RR11662200 BBrriieeff SShheeeett FFAASSTT EETTHHEERRNNEETT RRIISSCC PPRROOCCEESSSSOORR

RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 2 of 5 REV 1.0 Sep. 20 2006 1. Features l Five-stage pipeline l RISC architecture l Bus interface - Multiplexed address and Data bus - Supports non-multiplexed address bus A[19:0] - 8-bit or 16-bit external bus dynamic access - 1M-byte memory address space - 64K-byte I/O space - Supports an independent bus for slower I/O device l Software is compatible with the 80C186 microprocessor l Supports two 16550 UART serial channel with 16 bytes FIFO. l Supports CPU ID l Supports 32 PIO pins l SDRAM control Interface l Three independent 16-bit timers and one independent programmable watchdog timer l The Interrupt controller with six maskable external interrupts and two non-maskable external interrupt l Two independent DMA channels l Programmable chip-select logic for Memory or I/O bus cycle decoder l Programmable wait-state generator l With 8-bit or 16-bit Boot ROM bus size l 2-Port Fast Ethernet MAC with MII interface l With 25MHz input frequency and up to 4x25MHz maximum internal frequency. l Compatible with 3.3V I/O. l Package Types include 160-pin PQFP and 160-pin LQFP.

RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 3 of 5 REV 1.0 Sep. 20 2006 2. Block Diagram DMA Unit Chip Select Unit Refresh Control Unit SDRAM/Bus Interface Unit PIO Unit Timer Control Unit Interrupt Control Unit Clock and Power Management

16550 UART

Queue (64bits) Instruction Decoder Register File General, Segment, Eflag Register ALU (Special, Logic, Adder, BSF) Micro ROM EA / LA Address Control Signal Execution Unit X1 X2 CLKOUTA INT[6:5] INT0 TMRIN0 TMROUT0 TMRIN1 TMROUT1 DRQ0 DRQ1 SOUT0 SIN0 A[19:0] AD[15:0] ALE RD_n VCC GND LCS_n/ONCE0_n UCS_n/ONCE1_n PCS5_n PCS6_n ARDY SRDY DT/R_n DEN_n HOLD HLDA WHB_n INT1/SELECT_n INT3/INTA1_n/IRQ INT2/INTA0_n NMI RST_n MAC0 MAC1 MII 1 MII 0 SD_CLK CKE CS_n WE_n CAS_n RAS_n BA DCD0_n DTR0_n DSR0_n RTS0_n CTS0_n RI0_n SOUT1 SIN1 DCD1_n DTR1_n DSR1_n RTS1_n CTS1_n RI1_n WLB_n/ADEN_n WR_n/BWSEL

RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 4 of 5 REV 1.0 Sep. 20 2006 3. Package Information PQFP 160 pins 121 160 81120 A = 4.07mm (max.) A2 A1 = 0.25mm (min.) PIN 1 IDENTIFIER 31.2 ± 0.25mm 28.0 ± 0.1mm 15° REF 10° REF A2 = 3.22 ± 0.07mm 28 ± 0.1mm 31.2 ± 0.25mm 0.18 ± 0.05mm 0.30 ± 0.05mm0.65mm BSC RDC R1620 XXXX-B-QF XX-XXXXX

RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 5 of 5 REV 1.0 Sep. 20 2006 LQFP 160 pins 121 160 81120 A = 1.6mm (max.) A2 PIN 1 IDENTIFIER 26mm BSC 24mm BSC A2 = 1.4 ± 0.05mm 24mm BSC 26mm BSC 12 ± 1° REF A1 = 0.1 ± 0.05mm 12 ± 1° REF 0.5mm BSC 0.22 ± 0.05mm 0.145 ± 0.055mm RDC R1620 XXXX-B-LQ XX-XXXXX