R2880

R2880 RDC | Alldatasheet

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Technical content

RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 1 of 5 REV 1.0 Jun. 12 2007 RR22888800 BBrriieeff SShheeeett FFAASSTT EETTHHEERRNNEETT RRIISSCC PPRROOCCEESSSSOORR

RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 2 of 5 REV 1.0 Jun. 12 2007 1. Features l CPU Core - RDC’s proprietary RISC architecture - Five-stage pipeline architecture - Operation frequency: 100MHz - Supports an 8K-byte uniform cache l ROM/RAM/SDRAM Controller and Addressing Space - Supports 16-bit data bus width - Flash ROM/SRAM control interface - SDRAM control interface - 16M addressing space - 64K-byte I/O space l Two Independent DMA Controllers l Interrupt Controller - Provides 8 maskable external interrupt channels l Counter/ Timers - Three independent 16-bit timers - Timer 1 can be programmed as a watchdog timer l High Performance UART Ports - Supports 2 high performance UARTs with send/receive 16-byte FIFOs - Programmable baud rate generators - The data rates are programmable from 50 to 460.8K baud (max. to 1Mbps) - The character options are programmable for 1 start bit; 1, 1.5 or 2 stop bits; even, odd or no parity, 5~8 data bits l RDC Debug Tool Support - RDC debug tool with a JTAG-like interface l General Programmable I/O - 48 programmable I/O ports - Pins individually configurable to input or output mode l Two 10/100M Fast Ethernet MAC Ports - IEEE 802.3u MII interface - IEEE 802.3x flow control in full-duplex mode - Internal loop-back self-test circuit support - Descriptor architecture for packet TX/RX l PCI Control Interface Support - Supports up to 5 PCI masters - Speed up to 33MHz l Two Card Bus Interface Support l A Green Product l Package Type - 208-pin PQFP - 225-ball LFBGA l Operating Temperature : 0 ~ 70 ℃

RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 3 of 5 REV 1.0 Jun. 12 2007 2. Block Diagram 8K-Byte Cache RDC RISC CPU MAC 0 MAC 1 PIO Unit

16550 UART

Clock & Power Management Uuit CLKOUTA SD_CLK PCICLK X1 X2 INTB_n INTA_n INT3 INT2 INT1 INT0 VCC Reset Unit Chip Select Unit Refresh Control Unit SDRAM/Bus Interface Unit GND RST_n PCIRST_n UCS_n MCS_n PCS0_n PCS1_n PCS2_n PCS3_n PCS5_n PCS6_n RAS_n CAS_n WE_n BA[1:0] DQMH DQML A[22:0] D[15:0] RD_n WR_n IOR_n IOW_n ARDY UART 0 PCI Bus PCI Bus Interface PCI Arbiter PCI Master PCI Target PCI Configuration Register

RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 4 of 5 REV 1.0 Jun. 12 2007 3. Package Information PQFP 208 pins be A2A 0.5mm (BSC) 0.17~0.27mm 31.20mm 28.00mm 0.11~0.23mm A2 = 3.20~3.60mm A1 = 0.25mm (Min.) A = 4.10mm (Max.) 1.60mm (REF) PIN 1 IDENTIFIER 1.60mm 0.25mm DETAIL A DETAIL A 4.10mm (Max.) 3.20~3.60mm 0.88 ± 0.15mm

RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 5 of 5 REV 1.0 Jun. 12 2007 LFBGA 225 balls