R1610 RDC | Alldatasheet
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RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 1 of 4 REV 1.0 Nov. 25 2005 RR11661100 BBrriieeff SShheeeett FFAASSTT EETTHHEERRNNEETT RRIISSCC PPRROOCCEESSSSOORR
RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 2 of 4 REV 1.0 Nov. 25 2005 1. Features l Five-stage pipeline l RISC architecture l Bus interface - Multiplexed address and data bus - Supports non-multiplexed address bus A[19:0] - 8-bit or 16-bit external bus dynamic access - 1M-byte memory address space - 64K-byte I/O space - Supports an independent bus for the slower I/O device l Software is compatible with the 80C186 microprocessor l Supports two 16550 UART serial channels with 16-byte FIFO l Supports CPU ID l Supports 18 PIO pins l SDRAM control Interface l Three independent 16-bit timers and one independent programmable watchdog timer l The Interrupt controller with five maskable external interrupts and one non-maskable external interrupt l Two independent DMA channels l Programmable chip-select logic for memory or I/O bus cycle decoder l Programmable wait-state generators l With 8-bit or 16-bit boot ROM bus size l 1-port Fast Ethernet MAC with MII interface l With 25MHz input frequency and up to 4x25MHz maximum internal frequency l Compatible with 3.3V I/O l With 128-pin PQFP package type
RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 3 of 4 REV 1.0 Nov. 25 2005 2. Block Diagram DMA Unit Chip Select Unit Refresh Control Unit SDRAM/Bus Interface Unit PIO Unit Timer Control Unit Interrupt Control Unit Clock and Power Managemen t
16550 UART
Queue (64bits) Instruction Decoder Register File General, Segment, Eflag Register ALU (Special, Logic, Adder, BSF) Micro ROM EA / LA Address Control Signal Execution Unit X1 X2 CLKOUTA INT[6:5] INT0 TMRIN0 TMROUT0 TMRIN1 TMROUT1 DRQ0 DRQ1 SOUT0 SIN0 A[19:0] AD[15:0] ALE RD_n VCC GND UCS_n PCS5_n ARDY INT1/SELECT_n INT2/INTA0_n NMI RST_n MAC MII SD_CLK WE_n CAS_n RAS_n DCD0_n DTR0_n DSR0_n RTS0_n CTS0_n RI0_n SOUT1 SIN1 DCD1_n DTR1_n DSR1_n RTS1_n CTS1_n WR_n/BWSEL PCS[3:0]_n
RRIISSCC DDSSPP CCoommmmuunniiccaattiioonn FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 4 of 4 REV 1.0 Nov. 25 2005 3. Package Information PQFP 128 pins Seating Plane 1 38 128 103 65102 20.0 ± 0.1mm 14.0 ± 0.1mm 17.2 ± 0.2mm 23.2 ± 0.2mm Pin 1 Identifier 3.40mm (Max.) 2.85 ± 0.12mm 0.25mm (Min.) 0.145 ± 0.055mm 0.22 ± 0.05mm 0.5mm BSC RDC R1610 XXXX-B-QF XX-XXXXX