PUMA68S4000X-010 MOSAIC | Alldatasheet

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Technical content

Features

 Access times of 10, 12, 15 and 17ns.  5V + 10%.  Commercial and Industrial temperature grades  JEDEC Standard 68 PLCC footprint.  Industry standard pinout.  User configurable as 8 / 16 / 32 bits wide.  Operating Power (10ns-32 Bit) 3.96W (max)  Low power standby. (TTL) 1.16W (max)  Completely Static Operation. PUMA68S4000X - 010/012/015/017 Issue 5.1 April 2001

Description

The PUMA68 range of devices provide a high density surface mount industry standard memory solution which may accommodate various memory technologies including SRAM, EEPROM and Flash. The devices are designed to offer a defined upgrade path and may be user configured as 8, 16 or 32 bits wide. The PUMA68S4000X is a 128Kx32 SRAM module housed in a 68 Jleaded package which complies with the JEDEC 68 PLCC standard. Access times of 10, 12, 15 and 17ns are available. The 5V device is available to commercial and industrial temperature grade.

Issue 5.1 April 2001PAGE 2 Pin Definition - PUMA68S4000X Pin Signal Pin Signal

1 V CC 35 V CC

2 NC 36 A13

7 NC 41 A8

8 NC 42 A7

9 D16 43 D0

10 D17 44 D1

11 D18 45 D2

12 D19 46 D3

13 V SS 47 V SS

14 D20 48 D4

15 D21 49 D5

16 D22 50 D6

17 D23 51 D7

18 V CC 52 V CC

19 D24 53 D8

20 D25 54 D9

21 D26 55 D10

22 D27 56 D11

23 V SS 57 V SS

24 D28 58 D12

25 D29 59 D13

26 D30 60 D14

27 D31 61 D15

28 A6 62 A14

29 A5 63 A15

30 A4 64 A16

31 A3 65 /WE

32 A2 66 /OE

33 A1 67 NC

34 A0 68 NC

Issue 5.1 April 2001PAGE 3 Absolute Maximum Ratings(1) Recommended Operating Conditions (VCC =5V +10%, TA=-40O C to 85O C) Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Notes (1) /CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode. (2) At f=fMAX address and data inputs are cycling at max frequency (3) All currents are specified for 10ns Parameter Symbol Min Typ Max Unit Supply Voltage VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 - V CC +0.3 V Input Low Voltage VIL (1) -0.3 - 0.8 V Operating Temperature (Commercial) T A 0 - 70 O C (Industrial) TAI -40 - 85 O C (I Suffix) Parameter Symbol Min Max Unit Voltage on any pin relative to VSS V T -0.3 to +7.0 V Power Dissipation P T 4.0 W Storage Temperature T STG -55 to +125 O C DC Output Current I OUT 20 mA Notes : (1) Pulse Width : -3.0V for less than 5ns. Parameter Symbol Test Condition Min Typ Max Unit Input Leakage Current ILI VIN=0V to VCC -20 - 20 µA Output Leakage Current ILO VI/O=0V to VCC -20 - 20 µA Operating Supply Current 32 Bit ICC32 CS (1) =V IL,II/O=0mA, f=fMAX - - 750 mA

16 Bit ICC16 CS

(1) =V IL,II/O=0mA, f=fMAX - - 490 mA

8 Bit ICC8 CS

(1) =V IL,II/O=0mA, f=fMAX - - 370 mA Standby Supply Current TTL ISB /CS (1) =V IH,f=fMAX ,VIN=V IL or VIH - - 250 mA Output Voltage Low VOL IOL =8.0mA, VCC = Min - - 0.4 V Output Voltage High VOH IOH =-4.0mA, VCC = Min 2.4 - - V

Issue 5.1 April 2001PAGE 4 /CS1 /CS2 /CS3 /CS4 /OE /WE Supply Current Mode L H H H X L I CC8 Write D0~D7 H L H H X L I CC8 Write D8~D15 H H L H X L I CC8 Write D16~D23 H H H L X L I CC8 Write D24~D31 L L H H X L I CC16 Write D0~D15 H H L L X L I CC16 Write D16~D31 L L L L X L I CC32 Write D0~D31 L H H H L H I CC8 Read D0~D7 H L H H L H I CC8 Read D8~D15 H H L H L H I CC8 Read D16~D23 H H H L L H I CC8 Read D24~D31 L L H H L H I CC16 Read D0~D15 H H L L L H I CC16 Read D16~D31 L L L L L H I CC32 Read D0~D31 X X X X H H I CC32 /ICC16 /ICC8 D0~D31 High-Z H H H H X X I SB ,ISB1 D0~D31 Standby 166Ω 30pF I/O Pin 1.76V Capacitance (VCC = 5.0V, TA = 25O C, F=1MHz.) Parameter Symbol Test Condition Min Typ Max Unit Input Capacitance, (Address, /OE, /WE) C IN1 V IN=0V - - 30 pF Output Capacitance, 8 bit mode (worst case) C I/O VI/O=0V - - 38 pF Test Conditions Output Load  Input pulse levels : 0V to 3.0V  Input rise and fall times : 3ns  Input and Output timing reference levels : 1.5V  Output Load : See Load Diagram.  VCC = 5V+10%  PUMA module tested in 32 bit mode. Note : These Parameters are calculated not measured. Operation Truth Table Notes : H=VIH : L=VIL : X=VIH or VIL

Issue 5.1 April 2001PAGE 5 Read Cycle Write Cycle 10 12 15 17 Parameter Symbol Min Max Min Max Min Max Min Max Units Read Cycle Time t RC 10 - 12 - 15 - 17 - ns Address Access Time t AA - 10 - 12 - 15 - 17 ns Chip Select Access Time t ACS - 10 - 12 - 15 - 17 ns Output Enable to Output Valid t OE - 5 - 6 - 7 - 8 ns Output Hold From Address Change tOH 2 - 3 - 3 - 3 - ns Chip Selection to Output in Low Z tCLZ 3 - 3 - 3 - 3 - ns Output Enable to Output in Low Z tOLZ 0 - 0 - 0 - 0 - ns Chip Deselection to Output in High Z tCHZ 0 5 0 6 0 8 0 9 ns Output Disable to Output in High Z tOHZ 0 4 0 5 0 7 0 8 ns 10 12 15 17 Parameter Symbol Min Max Min Max Min Max Min Max Units Write Cycle Time t WC 10 - 12 - 15 - 17 - ns Chip Selection to End of Write tCW 9 - 10 - 12 - 15 - ns Address Valid to End of Write tAW 9 - 10 - 12 - 15 - ns Address Setup Time t AS 0 - 0 - 0 - 0 - ns Write Pulse Width t WP 8 - 9 - 10 - 12 - ns Write Recovery Time t WR 0 - 0 - 0 - 0 - ns Data to Write Time Overlap t DW 6 - 7 - 9 - 12 - ns Output Active from End of Write tOW 0 - 0 - 0 - 0 - ns Data Hold time from Write Time tDH 0 - 0 - 0 - 0 - ns Write to Output in High Z t WHZ - 5 - 6 - 7 - 8 ns Under Development

Issue 5.1 April 2001PAGE 6 Read Cycle 1 3,6,7,9 (Address Controlled) Read Cycle 2 3,6,8,9 (/CS Controlled) Address D OUT tRC tAA tOH Data Valid /CS /OE D OUT Current Supply Data Valid 50% 50% tRC tOE tOLZ tPU tCLZ tPD tOHZ tCHZ ICC ISB Notes 1 During VCC power-up, a pull-up resistor to VCC on /CS is required to meet I SB specification. 2 This parameter is sampled and not 100% tested. 3 For test conditions, see AC Test Conditions, Figures A, B, C. 4 tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage. 5 This parameter is guaranteed but not tested. 6 /WE is HIGH for read cycle. 7 /CS and /OE are LOW for Read cycle. 8 Address valid prior to or coincident with CS transition LOW.

9 All read cycle timin

gs are referenced from the last valid address to the first transitioning address. 10 /CS or /WE must be HIGH during address transitions. 11 All write cycle timings are referenced from the last valid address to the first transitioning address.

Issue 5.1 April 2001PAGE 7 Write Cycle 1 10,11 (/WE Controlled) Data Valid Address /WE D IN D OUT tWC tAW tAH tAS tWP tDW tDH tOWtWZ Notes 1 During VCC power-up, a pull-up resistor to VCC on /CS is required to meet I SB specification. 2 This parameter is sampled and not 100% tested. 3 For test conditions, see AC Test Conditions, Figures A, B, C. 4 t CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage. 5 This parameter is guaranteed but not tested. 6 /WE is HIGH for read cycle. 7 /CS and /OE are LOW for Read cycle. 8 Address valid prior to or coincident with CS transition LOW. 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 /CS or /WE must be HIGH during address transitions. 11 All write cycle timings are referenced from the last valid address to the first transitioning address.

Issue 5.1 April 2001PAGE 8 Address /WE tWC tAW tAH tAS tCW Data Valid /CS D IN D OUT tWP tWZ tDW tDH Notes 1 During VCC power-up, a pull-up resistor to VCC on /CS is required to meet I SB specification. 2 This parameter is sampled and not 100% tested. 3 For test conditions, see AC Test Conditions, Figures A, B, C. 4 tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage. 5 This parameter is guaranteed but not tested. 6 /WE is HIGH for read cycle. 7 /CS and /OE are LOW for Read cycle. 8 Address valid prior to or coincident with CS transition LOW. gs are referenced from the last valid address to the first transitioning address. 10 /CS or /WE must be HIGH during address transitions. 11 All write cycle timings are referenced from the last valid address to the first transitioning address. Write Cycle 2 10,11 (/CS Controlled)

PAGE 9 Issue 5.0 August 1999 PUMA 68 pin JEDEC Surface Mounted PLCC 25.02 (0.985) 0.90 (0.035) typ 23.11 (0.910) 5.08 (0.200) max 24.13 (0.950) 25.27 (0.995) 1.27 (0.050) 0.46 (0.018) Pin 68Pin 1

Ordering Information

PAGE 10 Issue 5.1 April 2001http://www.mosaicsemi.com/ Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. /G50/G55/G4D/G41/G20/G36/G38/G53/G34/G30/G30/G30/G58/G4C/G49/G20/G2D/G20/G30/G31/G30 Speed 010 = 10ns 012 = 12ns 015 = 15ns 017 = 17ns Temp. Range/Screening Blank = Commercial I = Industrial Power Consumption Blank = Standard Pinout Configuration X = Industry Standard Pinout Memory Organisation 4000 = configurable as 128K x 8, 256K x 16 or 512K x 8 Technology S = SRAM Package PUMA 68 = 68 pin ‘J’ Leaded PLCC

PAGE 11 Issue 5.1 April 2001 Visual Inspection Standard All devices inspected to ANSI/J-STD-001B Class 2 standard Moisture Sensitivity Devices are moisture sensitive. Shelf Life in Sealed Bag 12 months at <40O C and <90% relative humidity (RH). After this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or equivalent processing (peak package body temp 220O C) must be : A : Mounted within 72 Hours at factory conditions of <30O C/60% RH OR B : Stored at <20% RH If these conditions are not met or indicator card is >20% when read at 23 O C +/-5% devices require baking as specified below. If baking is required, devices may be baked for :- A : 24 hours at 125O C +/-5% for high temperature device containers OR B : 192 hours at 40 O C +5O C/-0O C and <5% RH for low temperature device containers. Packaging Standard Devices packaged in dry nitrogen, JED-STD-020. Packaged in trays as standard. Tape and reel available for shipment quantities exceeding 200pcs upon request. Soldering Recomendations IR/Convection - Ramp Rate 6 O C/sec max. Temp. exceeding 183O C 150 secs. max. Peak Temperature 225 O C Time within 5O C of peak 20 secs max. Ramp down 6 O C/sec max. Vapour Phase - Ramp up rate 6 O C/sec max. Peak Temperature 215 - 219 O C Time within 5O C of peak 60 secs max. Ramp down 6 O C/sec max. The above conditions must not be exceeded. Note : The above recomendations are based on standard industry practice. Failiure to comply with the above recomendations invalidates product warranty.