MSM8512C-020

MSM8512C-020 MOSAIC | Alldatasheet

Document overview

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Technical content

Features

• Access times of 20 ns.  5V + 10%, (3.3V Under Development)  Commercial & Industrial temperature grades  Chip Size BGA.  48 pad, 1mm pad pitch, package.  Eutectic 63/67 solder ball attach.  Low Power Dissipation. Operating 1 W (max) Standby (CMOS) 66mW (max)  Completely Static Operation.  4 layer BT substrate with power and ground planes.  Pinout and footprint will remain the same in the event of a die shrink. MSM8512C - 020 Issue 5.2 April 2001

Description

The MSM8512C is a 512K x 8 SRAM monolithic device available in Chip Size BGA (Ball Grid Array) package, with access times of 20ns. The device is available to commercial and industrial temperature grades. The Chip Size BGA provides an ultra high density memory packaging solution. The Chip Size BGA occupies less than 50% of the board area of conventional SOP, SOJ and TSOP II packages.

Issue 5.2 April 2001PAGE 2 Pin Definition - MSM8512B Pinout (Top View) 1234 56 A B C D E F G H /CS A2 A0 A17 A15 NC NC VCC VSS NC NC A1 A16 NC NC NC A18 NC NC A12A10A8A6 VCC VSS D7A3 /OE NC D1 NC D6 A14 D2 NC NC A5 A13 /WE NC A7 A11 Note : Pinout shows top view, balls facing down. Pin A1 Ident.

Issue 5.2 April 2001PAGE 3 Parameter Symbol Min Typ Max Unit Supply Voltage V CC 4.5 5.0 5.5 V Input High Voltage V IH 2.2 - 6.0 V Input Low Voltage V IL -0.3 - 0.8 V Operating Temperature T A 0 - 70 O C T AI -40 - 85 O C (I Suffix) Absolute Maximum Ratings(1) Recommended Operating Conditions (VCC =5V +10%, TA= -40O C to 85O C) Parameter Symbol Min Max Unit Voltage on any pin relative to VSS V T -0.5 to +6.0 V Power Dissipation P T 1 W Storage Temperature T STG -55 to +150 O C Parameter Symbol Test Condition Min Typ Max Unit Input Leakage Current I LI VIN=V SS to VCC -2 - 2 µA Output Leakage Current I LO /CS=V IH or /OE=VIH or /WE=VIL, VOUT =V SS to VCC -2 - 2 µA Operating Supply Current ICC1 Min. Cycle, 100% Duty /CS=V IL, VIN=V IH or VIL, IOUT =0mA - - 180 mA Standby Supply Current I SB Min. Cycle, /CS=VIH - - 60 mA I SB1 f=0MHz, CS>VCC -0.2V, VIN>VCC -0.2V or VIN<0.2V - - 12 mA Output Voltage V OL IOL =8.0mA - - 0.4 V V OH IOH =-4.0mA 2.4 - - V Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability

Issue 5.2 April 2001PAGE 4 166Ω 30pF I/O Pin 1.76V Capacitance (VCC = 5.0V+10% TA = 0O C to 70O C) Parameter Symbol Test Condition Typ max Unit Input Capacitance C IN V IN=0V - 10 pF I/O Capacitance C I/O VI/O=0V - 10 pF Test Conditions Output Load  Input pulse levels : 0V to 3.0V  Input rise and fall times : 3ns  Input and Output timing reference levels : 1.5V  Output Load : See Load Diagram.  VCC = 5V+10% /CS /WE /OE Mode I/O Pin Supply Current H X X Not Select High-Z I SB ,ISB1 L H H Output Disable High-Z I CC L H L Read D OUT I CC L L X Write D IN I CC Functional Description Note : X = Don’t Care

Issue 5.2 April 2001PAGE 5 AC Operating ConditionsRead Cycle Write Cycle Parameter Symbol Min Max Units Read Cycle Time t RC 20 - ns Address Access Time t AA - 20 ns Chip Select to Output t CO - 20 ns Output Enable to Valid Output t OE - 9 ns Chip Enable to Low-Z Output t LZ 3 - ns Output Enable to Low-Z Output t OLZ 0 - ns Chip Disable to High-Z Output t HZ 0 9 ns Output Disable to High-Z Output tOHZ 0 9 ns Output Hold from Address Change t OH 3 - ns Parameter Symbol Min Max Units Write Cycle Time t WC 20 - ns Chip Select to End of Write t CW 14 - ns Address Set-up Time t AS 0 - ns Address Valid to End of Write tAW 14 - ns Write Pulse Width (/OE High) t WP 14 - ns Write Recovery Time t WR 0 - ns Write to Output High-Z t WHZ 0 9 ns Data to Write Time Overlap t DW 10 - ns Data Hold from Write Time t DH 0 - ns End Write to Output Low-Z t OW 3 - ns

Issue 5.2 April 2001PAGE 6 Read Cycle 1 (Address Controlled, /CS=/OE=VIL, /WE=VIH) Read Cycle 2 (/WE = VIH) Previous Data Valid Data Valid Address Data Out tRC tAAtOH Address Data Out Valid Data tRC tAA tCO tOLZ tLZ(4,5) tHZ(3,4,5) tOHZ tOH /CS /OE NOTES (READ CYCLE) 1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or V OL levels. 4. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CS=VIL. 7. Address valid prior to coincident with /CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. tOE

Issue 5.2 April 2001PAGE 7 Write Cycle 1 (/OE = Clock) Valid Data Address /OE /CS Data In Data Out tWC tAW tWR(5) tCW(3) tAS(4) tWP(2) tDW tDH tOHZ(6) High Z High Z(8) /WE NOTES (WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When /CS is low I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.

Issue 5.2 April 2001PAGE 8 Write Cycle 2 (/OE = Low Fixed) /CS Address Data In Data Out tWC tAW tWR(5) tCW(3) tAS(4) tWP(2) tWHZ(6) High Z High Z(8) /WE Valid Data tDW tDH tOW (10) (9) NOTES (WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When /CS is low I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.

Issue 5.2 April 2001PAGE 9 Write Cycle 3 (/CS = Controlled) /CS Address Data In Data Out tWC tAW tWR(5) tCW(3) tAS(4) tWP(2) tWHZ(6) High Z High Z(8) /WE Valid Data tDW tDH tLZ High Z High Z NOTES (WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.

Issue 5.2 April 2001PAGE 10 Package Details Chip Size BGA - 48 pad General Reliability Data High Temperature Operating Life 125 O C / 6V / 1000hrs High Temperature Storage Life 150 O C / 1000hrs Autoclave 121 O C / 100% RH / 168hrs Temperature Cycling -55 ~ 125 O C / 1000 cycles Moisture Sensitivity JEDEC Level 3 30 O C / 60% RH / 192hrs O JA Thermal Performance 30 ~ 45 O C/Watt 10.00 Max. 8.00 Max. 1.40 Max. Top View Pin A1 Ident. 1.00+0.07 C L 1.00+0.07 C L Bottom View

Ordering Information

PAGE 11 Issue 5.2 April 2001 Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. /G4D/G53/G4D/G38/G35/G31/G32/G43/G42/G20/G49/G20/G2D/G20/G30/G32/G30/G2F/G34/G38/G44 48D 48D = 48 Pad package, 1mm Pitch Speed 020 = 20ns Temp. Range/Screening Blank = Commercial I = Industrial Power Consumption Blank = Standard Power Package B = Chip Size BGA Die Revision C = ‘C ’ Rev die. Memory Organisation 8512 = 512K x 8 Family M = Monolithic Technology S = SRAM