MSM8128

MSM8128 MOSAIC | Alldatasheet

Document overview

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Technical content

Features

Access Times of 70/85/100/120 ns JEDEC standard Dual CS footprints. Operating Power 550 mW (max) Low Power Standby (-L) 2.2 mW (max) Low Voltage Data Retention. Completely Static Operation Directly TTL compatible. May be processed in accordance with MIL-STD-883

Description

The MSM8128 is a 1Mbit monolithic SRAM organised as 128K x 8. It is currently available in a VIL Package, with access times of 70, 85, 100, 120ns. It has a low power standby version and has 3.0V battery backup capability. It is directly TTL compatible and has common data inputs and outputs. Two pinout variants (single and dual CS) are available. All versions may be screened in accordance with MIL-STD-883. Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997 Pin Definition NC A12 A14 A16 GND VCC A11 OE A13 WE CS2 A15 A10 CS1 TOP VIEW S,V TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE

MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 /G32 Absolute Maximum Ratings Voltage on any pin relative to V SS VT -0.5V to +7.0 V Power Dissipation P T 1W Storage Temperature T STG -55 to +150 oC Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions min typ max Supply Voltage V CC 4.5 5.0 5.5 V Input High Voltage V IH 2.2 - 5.8 V Input Low Voltage V IL -0.3 - 0.8 V Operating Temperature T A 0- 7 0 oC TAI -40 - 85 oC (I suffix) TAM -55 - 125 oC (M , MB suffix) DC OPERATING CONDITIONS Capacitance (VCC=5V±10%,TA=25oC) Parameter Symbol Test Condition typ max Unit I/P Capacitance C IN VIN=0V - 9 pF I/O Capacitance C I/O VI/O=0V - 11 pF Note: This parameter is not 100% tested. Parameter Symbol Test Condition min typ max Unit Input Leakage Current I LI VIH=0V to Vcc -2 - 2 µA Output Leakage Current I l/O CS1=VIH, CS2 =VIL, VI/O=0V to Vcc ,OE=VIH -2 - 2 µA Average Supply Current I CC1 Min. Cycle, VIN=VIL or VIH - - 110 mA Standby Supply Current I SB1 CS1=VIH,CS2 = VIL , I/P's static -- 4 m A Output Voltage V OL IOL = 2.1 mA - - 0.4 V VOH IOH = -1.0 mA 2.4 - - V

MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 /G33 Operating Modes The table below shows the logic inputs required to control the MSM8128 SRAM. /G20Mode CS1 CS2 OE WE V CC Current I/O Pin Reference Cycle Not Selected 1 X X X I SB1,ISB2 High Z Power Down Not Selected X 0 X X I SB,ISB1 High Z Power Down Output Disable 0 1 1 1 I CC High Z Read 0 1 0 1 I CC DOUT Read Cycle Write 0 1 X 0 I CC DIN Write Cycle 1 = VIH,0 = V IL, X = Don't Care Low V cc Data Retention Characteristics - L Version Only (TA=-55°C to +125oC) Parameter Symbol Test Condition min typ max Unit VCC for Data Retention V DR CS1/G20≥≥≥≥≥/G20VCC-0.2V, CS2/G20≥≥≥≥≥/G20VCC-0.2V or Data Retention Current I CCDR VCC=3.0V,VIN ≥≥≥≥≥/G200V, CS1/G20/G20≥≥≥≥≥VCC-0.2V, Chip Deselect to Data Retention t CDR See Retention Waveform 0-- n s Operation Recovery Time t R See Retention Waveform 5-- m s Notes (1) CS2 controls address buffer, WE buffer, CS1 buffer and OE buffer. If CS2 controls data retention mode, Vin levels (WE,OE,CS1,I/O) can be in the high impedance state. If CS1 controls Data Retention mode, CS2 must be/G20≥≥≥≥≥/G20VCC - 0.2V or 0V ≤≤≤≤≤ CS2/G20≤≤≤≤≤ 0.2V. The other input levels (address, WE,OE,I/O) can be in the high impedance state. AC Test Conditions Output Load * Input pulse levels: 0V to 3.0V * Input rise and fall times: 5ns * Input and Output timing reference levels: 1.5V * Output load: See Load Diagram * V cc=5V±10% 166 30pF I/O Pin 1.76V Ω

MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 /G34 /G20AC OPERATING CONDITIONS Read Cycle 70 85 10 12 Parameter Symbol min max min max min max min max Unit Read Cycle Time tRC 70 - 85 - 100 - 120 - ns Address Access Time tAA - 70 - 85 - 100 - 120 ns Chip Select (CS1) Access Time(2) tACS1 - 70 - 85 - 100 - 120 ns Chip Select (CS2) Access Time(2) tACS2 - 70 - 85 - 100 - 120 ns Output Enable to Output Valid tOE -3 5-4 5-5 0-6 0 n s Output Hold from Address Change tOH 5-5- 1 0 - 1 0 - n s Chip Selection (CS1) to Output in Low Z tCLZ1 10 - 10 - 10 - 10 - ns Chip Selection (CS2) to Output in Low Z tCLZ2 10 - 10 - 10 - 10 - ns Output Enable to Output in Low Z tOLZ 5-5-5-5- n s Chip Disable (CS1) to Output in High Z(3) tCHZ1 03 503 503 504 5 n s Chip Disable (CS2) to Output in High Z(3) tCHZ2 03 503 503 504 5 n s Output Disable to Output in High Z(3) tOHZ 03 003 003 504 5 n s Write Cycle 70 85 10 12 Parameter Symbol min max min max min max min max Unit Write Cycle Time tWC 70 - 85 - 100 - 120 - ns Chip Selection to End of Write tCW 60 - 75 - 85 - 100 - ns Address Valid to End of Write tAW 60 - 75 - 85 - 100 - ns Address Setup Time tAS 0-0-0-0- n s Write Pulse Width tWP 50 - 60 - 70 - 70 - ns Write Recovery Time (WE, CS1) tWR1 5-5-5-5- n s (CS2) t WR2 5-5-5-5- n s Write to Output in High Z tWHZ 03 003 003 504 0 n s Data to Write Time Overlap tDW 30 - 35 - 40 - 45 - ns Data Hold from Write Time tDH 0-0-0-0- n s Output Active from End of Write tOW 5-5-5-5- n s

MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 /G35 Notes: (1) WE is High for Read Cycle. (2) Address valid prior to or coincident with CS1 transition low or CS2 high. (3) t CHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. At any given temperature and voltage condition, t CHZ max is less than tCLZ min both for a given device and from device to device. This parameter is sampled and not 100% tested. Read Cycle Timing Waveform (1,2 ) t t t t RC AA OE OH Address OE CS1 Data Valid ttACS2 (2) tCLZ2 OHZ (3) tCHZ2 (3) Dout tOLZ tACS1 (2) tCLZ1 tCHZ1 (3) CS2

MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 /G36 Write Cycle No.1 Timing Waveform t t t t WC AS (3) AW Address CS1 t t t WP(1) DW DH WE Din tWR1,2 (2) High - Z Data Valid OE (6) OHZ(3,9)t Dout CS2 (6) CW (4) tWR1,2 (2) CS1 tCW (4) t t t WP (1) DW DH WE Dout Din tAS (3) tAW tWC Address High - Z Data Valid (6) tWHZ(3,9) High - Z tOW tOH (7)(8) (6)CS2 Write Cycle No.2 Timing Waveform (5)

MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 /G37 Low V CC Data Retention Timing Waveform 1 (CS1 controlled) Low V CC Data Retention Timing Waveform 2 (CS2 controlled) tRtCDR 4.5V 2.2V 4.5V 2.2V DATA RETENTION MODEVcc CS1 V DR CS1 ≥Vcc-0.2V 4.5V 4.5V DATA RETENTION MODEVcc CS2 V DR2 0.4V tRtCDR CS2 ≤ 0.2V AC Characteristics Notes (1) A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 going low, CS2 going high and WE going low. A write ends at the earliest transition among CS1 going high, CS2 going low and WE going high. t WP is measured from the beginning of write to the end of write. (2) t WR is measured from the earlier of CS1 or WE going high or CS2 going high to the end of write cycle. (3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied. (4) If CS1 goes low simultaneously with WE going low or after WE going low, outputs remain in high impedance state. (5) OE is continuously low. (OE=V IL) (6) Dout is in the same phase as written data of this write cycle. (7) Dout is the read data of next address. (8) If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input signals out of phase must not be applied to I/O pins. (9) t WHZ is defined as the time at which the outputs achieve the open circuit conditions and is not referenced to output voltage levels. These parameters are sampled and not 100% tested.

MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 /G38 Package Details All dimensions in mm (inches). 0.51 (0.020) 2.54 (0.100) 3.18 (0.125) 0.41 (0.016) 11.43 (0.450) 10.41 (0.410) 2.67 (0.105) 41.02 (1.615) 40.26 (1.585) 2.67 (0.105) 4.00 (0.157) 3.00 (0.117) 1.54 (0.060) 32 pin 0.1" Vertical-in-Line (VILTM ) - 'V' Package

MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 /G39 Military Screening Procedure Component Screening Flow for high reliability product is in accordance with Mil-883 method 5004 Visual and Mechanical Internal visual 2010 Condition B or manufacturers equivalent 100% Temperature cycle 1010 Condition C (10 Cycles,-65 oC to +150oC) 100% Constant acceleration 2001 Condition E (Y, only) (30,000g) 100% Pre-Burn-in electrical Per applicable device specifications at T A=+25oC 100% Burn-in Method 1015,Condition D,T A=+125oC,160hrs min 100% Final Electrical Tests Per applicable Device Specification Static (dc) a) @ T A=+25oC and power supply extremes 100% b) @ temperature and power supply extremes 100% Functional a) @ T A=+25oC and power supply extremes 100% b) @ temperature and power supply extremes 100% Switching (ac) a) @ T A=+25oC and power supply extremes 100% b) @ temperature and power supply extremes 100% Percent Defective allowable (PDA) Calculated at post-burn-in at TA=+25oC 5 % Hermeticity 1014 Fine Condition A 100% Gross Condition C 100% External Visual 2009 Per vendor or customer specification 100% SCREEN TEST METHOD LEVEL MB COMPONENT SCREENING FLOW Alternate Pin Definition NC A12 A14 A16 GND VCC A11 OE A13 WE NC A15 A10 CS TOP VIEW VX,SX

MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 /G31/G30 Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subjected to a constant process of development. Data may be changed at any time without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. MSM8128VLMB - 70 Speed 70 = 70 ns 85 = 85 ns 10 = 100 ns 12 = 120 ns Temp. range/screening Blank = Commercial I = Industrial M = Military MB = Screened in accordance with MIL-STD-883. Power Consumption Blank = Standard Power L = Low Power Package V = 32 pin 0.1" VIL VX = 32 pin 0.6" VIL (Single CS Organisation 8128 = 128K x 8 SRAM

Ordering Information

THE ABOVE PARTS ARE NOT RECOMMENDED FOR NEW DESIGNS AND MAY BE MADE OBSOLETE WITHOUT NOTICE.