PUMA68S16000XBI-25

PUMA68S16000X-020 MOSAIC | Alldatasheet

Document overview

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Technical content

Features

• Access times of 20/25 ns.  5V + 10%.  Commercial and Industrial temperature grades  JEDEC standard 68 J Lead footprint.  Industry standard pinout.  May be organised as 512K x 32, 1M x 16, 2M X 8  Operating Power (32 Bit) 4.18W max)  Low power standby.(TTL) 1.32W (max) (CMOS) 220mW (max)  Completely Static Operation. PUMA 68S16000X - 020/025 Issue 5.2 April 2001

Description

The PUMA68 range of devices provide a high density surface mount industry standard memory solution which may accommodate various memory technologies including SRAM, EEPROM and Flash. The devices are designed to offer a defined upgrade path and may be user configured as 8, 16 or 32 bits wide. The PUMA68SV16000X is a 512Kx32 SRAM mod- ule housed in a 68 Jleaded package which complies with the JEDEC 68 PLCC standard. Access times of 20 or 25ns are available. The 5V low voltage device is available to commercial and industrial temperature grade. Package Details PUMA 68 - Plastic 68 ‘J’ Leaded Package Max. Dimensions (mm) - 25.27 x 25.27 x 5.08

Issue 5.2 April 2001PAGE 2 Pin Definition - PUMA68SV16000X Pin Signal Pin Signal

1 V CC 35 V CC

2 NC 36 A13

7 A17 41 A8

8 A18 42 A7

9 D16 43 D0

10 D17 44 D1

11 D18 45 D2

12 D19 46 D3

13 V SS 47 V SS

14 D20 48 D4

15 D21 49 D5

16 D22 50 D6

17 D23 51 D7

18 V CC 52 V CC

19 D24 53 D8

20 D25 54 D9

21 D26 55 D10

22 D27 56 D11

23 V SS 57 V SS

24 D28 58 D12

25 D29 59 D13

26 D30 60 D14

27 D31 61 D15

28 A6 62 A14

29 A5 63 A15

30 A4 64 A16

31 A3 65 /WE

32 A2 66 /OE

33 A1 67 NC

34 A0 68 NC

Issue 5.2 April 2001PAGE 3 Parameter Symbol Min Typ Max Unit Supply Voltage V CC 4.5 5.0 5.5 V Input High Voltage V IH 2.2 - V CC +0.5 V Input Low Voltage V IL (1) -0.3 - 0.8 V Operating Temperature T A 0 - 70 O C T AI -40 - 85 O C (I Suffix) Absolute Maximum Ratings(1) Recommended Operating Conditions (VCC =5V +10%, TA=-40O C to +85O C) Parameter Symbol Min Max Unit Voltage on any pin relative to VSS V T -0.3 to +6 V Power Dissipation P T 4.0 W Storage Temperature T STG -55 to +125 O C Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Notes : (1) Pulse Width : -2.0V for less than 10ns. Notes (1) /CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode. (2) At f=fMAX address and data inputs are cycling at max frequency. Parameter Symbol Test Condition Min Typ Max Unit Input Leakage Current I LI V IN=0V to VCC -8 - 8 µA Output Leakage Current I LO V I/O=0V to VCC -8 - 8 µA Average Supply Current (2)

32 Bit I CC32 /CS

(1) =V IL, II/O=0mA,f=fmax - - 760 mA 16 Bit I CC16 As Above. - - 490 mA 8 Bit I CC8 As Above. - - 370 mA Standby Supply Current TTL I SB /CS (1) =V IH ,Min Cycle - - 240 mA CMOS I SB1 /CS>VCC -0.2V, 0.2V >VIN>VCC -0.2V, f=0 - - 40 mA Output Voltage Low V OL I OL =8.0mA, VCC =Min - - 0.4 V Output Voltage High V OH I OH =-4.0mA, VCC =Min 2.4 - - V

Issue 5.2 April 2001PAGE 4 166Ω 30pF I/O Pin 1.76V Capacitance (VCC = 5V, TA = 25O C, F=1MHz.) Parameter Symbol Test Condition Min Typ Max Unit Input Capacitance, Address, /OE, /WE C IN1 V IN=0V - - 30 pF Output Capacitance, 8 bit mode (worst case) C I/O VI/O=0V - - 34 pF Test Conditions Output Load  Input pulse levels : 0V to 3.0V  Input rise and fall times : 3ns  Input and Output timing reference levels : 1.5V  Output Load : See Load Diagram.  VCC = 5V+10%  PUMA module tested in 32 bit mode. Note : These Parameters are calculated not measured. /CS1 /CS2 /CS3 /CS4 /OE /WE Supply Current Mode L H H H X L I CC8 Write D0~D7 H L H H X L I CC8 Write D8~D15 H H L H X L I CC8 Write D16~D23 H H H L X L I CC8 Write D24~D31 L L H H X L I CC16 Write D0~D15 H H L L X L I CC16 Write D16~D31 L L L L X L I CC32 Write D0~D31 L H H H L H I CC8 Read D0~D7 H L H H L H I CC8 Read D8~D15 H H L H L H I CC8 Read D16~D23 H H H L L H I CC8 Read D24~D31 L L H H L H I CC16 Read D0~D15 H H L L L H I CC16 Read D16~D31 L L L L L H I CC32 Read D0~D31 X X X X H H I CC32 /ICC16 /ICC8 D0~D31 Hi gh-Z H H H H X X I SB , ISB1 D0~D31 Standb y Operation Truth Table Notes : H=VIH : L=VIL : X=VIH or VIL

Issue 5.2 April 2001PAGE 5 Read Cycle Write Cycle 20 25 Parameter Symbol Min Max Min Max Units Read Cycle Time t RC 20 - 25 - ns Address Access Time t AA - 20 - 25 ns Chip Select Access Time t ACS - 20 - 25 ns Output Enable to Output Valid t OE - 9 - 12 ns Output Hold From Address Change t OH 3 - 3 - ns Chip Selection to Output in Low Z tCLZ 3 - 3 - ns Output Enable to Output in Low Z tOLZ 0 - 0 - ns Chip Deselection to Output in High Z t CHZ 0 9 0 10 ns Output Disable to Output in High Z t OHZ 0 9 0 10 ns 20 25 Parameter S ymbol Min Max Min Max Units Write Cycle Time t WC 20 - 25 - ns Chip Selection to End of Write t C W 15 - 20 - ns Address Valid to End of Write t AW 15 - 20 - ns Address Setup Time t A S 0 - 0 - ns Write Pulse Width (/OE High) t WP1 13 - 15 - ns Write Pulse Width (/OE Low ) t WP2 14 - 15 - ns Write Recovery Time t WR 0 - 0 - ns Write to Output in High Z t WHZ 0 9 0 10 ns Data to Write Time Overlap t DW 9 - 10 - ns Data Hold time from Write Time t DH 0 - 0 - ns Output Active from End of Write t OW 3 - 3 - ns

Issue 5.2 April 2001PAGE 6 Address Data Out Valid Data tRC tAA tACS tOLZ tCLZ(4,5) tCHZ(3,4,5) tOHZ tOH /CS /OE NOTES (READ CYCLE) 1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or V OL levels. 4. At any given temperature and voltage condition, tCHZ (Max.) is less than tCLZ (Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CS=VIL. 7. Address valid prior to coincident with /CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary durin g read and write cycle. 9. /CS=/CS1~4 tOE Previous Data Valid Data Valid Address Data Out tRC tAAtOH Read Cycle 1 (Address Controlled, /CS=/OE=VIL, /WE=VIH) Read Cycle 2 (/WE = VIH)

Issue 5.2 April 2001PAGE 7 Valid Data Address /OE /CS Data In Data Out tWC tAW tWR(5) tCW(3) tAS(4) tWP(2) tDW tDH tOHZ(6) High Z High Z(8) /WE NOTES (WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11 /CS=/CS1~4 Write Cycle 1 (/OE = Clock)

Issue 5.2 April 2001PAGE 8 Write Cycle 2 (/OE = Low Fixed) /CS Address Data In Data Out tWC tAW tWR(5) tCW(3) tAS(4) tWP(2) tWHZ(6) High Z High Z(8) /WE Valid Data tDW tDH tOW (10) (9) NOTES (WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11. /CS=/CS1~4

Issue 5.2 April 2001PAGE 9 Write Cycle 3 (/CS = Controlled) /CS Address Data In Data Out tWC tAW tWR(5) tCW(3) tAS(4) tWP(2) tWHZ(6) High Z High Z(8) /WE Valid Data tDW tDH tLZ High Z High Z NOTES (WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. t WP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11. /CS=/CS1~4 Note: /CS = /CS1~4

PAGE 10 Issue 5.2 April 2001 PUMA 68 Pin JEDEC Surface Mount PLCC Notes: 1. All dimensions in mm (inches). 25.02 (0.985) 0.90 (0.035) typ 23.11 (0.910) 5.08 (0.200) max 24.13 (0.950) 25.27 (0.995) XXXXXX-X 0.46 (0.018) 1.27 (0.050) Pin 68Pin 1

PAGE 11 Issue 5.2 April 2001 Ordering InformationOrdering Information Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. /G50/G55/G4D/G41/G20/G36/G38/G53/G31/G36/G30/G30/G30/G58/G42/G49/G20/G2D/G20/G32/G30 Speed 20 = 20ns 25 = 25ns Temp. Range/Screening Blank =Commercial I = Industrial Pinout Configuration XB = Chip Scale BGABased Design, Industry Standard Pinout Memory Organisation 16000 = 512K x 32 configurable as 1M x 16 and 2M x 8 Technology S = SRAM Package PUMA 68 = 68 pin ‘J’ Leaded PLCC

PAGE 12 Issue 5.2 April 2001 Visual Inspection Standard All devices inspected to ANSI/J-STD-001B Class 2 standard Moisture Sensitivity Devices are moisture sensitive. Shelf Life in Sealed Bag 12 months at <40O C and <90% relative humidity (RH). After this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or equivalent processing (peak package body temp 220O C) must be : A : Mounted within 72 Hours at factory conditions of <30O C/60% RH OR B : Stored at <20% RH If these conditions are not met or indicator card is >20% when read at 23 O C +/-5% devices require baking as specified below. If baking is required, devices may be baked for :- A : 24 hours at 125O C +/-5% for high temperature device containers OR B : 192 hours at 40 O C +5O C/-0O C and <5% RH for low temperature device containers. Packaging Standard Devices packaged in dry nitrogen, JED-STD-020. Packaged in trays as standard. Tape and reel available for shipment quantities exceeding 200pcs upon request. Soldering Recomendations IR/Convection - Ramp Rate 6 O C/sec max. Temp. exceeding 183O C 150 secs. max. Peak Temperature 225 O C Time within 5O C of peak 20 secs max. Ramp down 6 O C/sec max. Vapour Phase - Ramp up rate 6 O C/sec max. Peak Temperature 215 - 219 O C Time within 5O C of peak 60 secs max. Ramp down 6 O C/sec max. The above conditions must not be exceeded Note : The above recommendations are based on standard industry practice. Failure to comply with the above recommendations invalidates product warranty.