PLSI1032E-100LJ

1032E1111 LATTICE | Alldatasheet

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High-Density Programmable Logic Functional Block DiagramFeatures

• HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E 2CMOS ® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES — In-System Programmable (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity
• ispEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Output Routing Pool Output Routing Pool D7 D6 D5 D4 D3 D2 D1 D0 B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool Output Routing Pool CLK Global Routing Pool (GRP) 0139A(A1)-isp Logic Array DQ DQ DQ DQ GLB

Description

The ispLSI and pLSI 1032E are High Density Program- mable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedi- cated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032E features 5-Volt in-system programmability and in-system diagnostic ca- pabilities. The ispLSI 1032E device offers non-volatile reprogrammability of the logic, as well as the intercon- nects to provide truly reconfigurable systems. It is architecturally and parametrically compatible to the pLSI 1032E device, but multiplexes four input pins to control in-system programming. A functional superset of the ispLSI and pLSI 1032 architecture, the ispLSI and pLSI 1032E devices add two new global output enable pins. The basic unit of logic on the ispLSI and pLSI 1032E devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI and pLSI 1032E devices. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. 1032E_06 Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com

Specifications ispLSI and pLSI 1032E Absolute Maximum Ratings 1 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions TA = 0°C to + 70°C TA = -40°C to + 85°C SYMBOL Table 2-0005/1032E VCC VIH VIL PARAMETER Supply Voltage Input High Voltage Input Low Voltage MIN. MAX. UNITS 4.75 4.5 2.0 5.25 5.5 Vcc+1 0.8 V V V V Commercial Industrial Capacitance (TA =25oC, f=1.0 MHz) Data Retention Specifications Table 2-0008/1032E PARAMETER pLSI Erase/Reprogram Cycles 100 Data Retention MINIMUM MAXIMUM UNITS ispLSI Erase/Reprogram Cycles 10000 Cycles Years Cycles C SYMBOL Table 2-0006/1032E C PARAMETER Y0 Clock Capacitance 15 UNITSTYPICAL TEST CONDITIONS 8Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance (Commercial/Industrial) pf pf V = 5.0V, V = 2.0V V = 5.0V, V = 2.0VCC CC PIN PIN

Figure 2. Test Load *C L includes Test Fixture and Probe Capacitance.

1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems

by tester ground degradation. Characterized but not 100% tested.

1. Measured using eight 16-bit counters.
2. Typical values are at V = 5V and T = 25°C.
3. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption

Specifications ispLSI and pLSI 1032E tpd1 UNITSTEST COND. 1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Table 2-0030A/1032E tsu2 + tco1( ) -100 MIN. MAX.DESCRIPTION#2PARAMETER A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 ns tpd2 A 2 Data Propagation Delay, Worst Case Path – ns fmax (Int.) A 3 Clock Frequency with Internal Feedback 100 – MHz fmax (Ext.) – 4 Clock Frequency with External Feedback – MHz fmax (Tog.) – 5 Clock Frequency, Max. Toggle – MHz tsu1 – 6 GLB Reg. Setup Time before Clock,4 PT Bypass – ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – ns th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass – ns tsu2 – 9 GLB Reg. Setup Time before Clock – ns tco2 – 10 GLB Reg. Clock to Output Delay – ns th2 – 11 GLB Reg. Hold Time after Clock – ns tr1 A 12 Ext. Reset Pin to Output Delay – ns trw1 – 13 Ext. Reset Pulse Duration – ns tptoeen B 14 Input to Output Enable – ns tptoedis C 15 Input to Output Disable – ns twh – 18 External Synchronous Clock Pulse Duration, High 4.0 ns twl – 19 External Synchronous Clock Pulse Duration, Low 4.0 ns tsu3 – 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) – ns th3 – 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) – ns 71.0 125 7.0 0.0 8.0 0.0 6.5 3.5 0.0 12.5 6.0 7.0 13.5 15.0 15.0 ( ) twh + tw1 tgoeen B 16 Global OE Output Enable – ns 9.0 tgoedis C 17 Global OE Output Disable – ns 9.0 -125 MIN. MAX. – 7.5 125 – 3.0 3.0 91.0 167 5.0 0.0 6.0 0.0 5.0 3.0 0.0 10.0 5.0 6.0 10.0 12.0 12.0 – 7.0 – 7.0 External Timing Parameters Over Recommended Operating Conditions

Specifications ispLSI and pLSI 1032E USE 1032E-100 FOR NEW DESIGNS tpd1 UNITSTEST COND. 1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Table 2-0030B/1032E tsu2 + tco1( ) -70 MIN. MAX.DESCRIPTION#2PARAMETER A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 15.0 ns tpd2 A 2 Data Propagation Delay, Worst Case Path – ns fmax (Int.) A 3 Clock Frequency with Internal Feedback 70.0 – MHz fmax (Ext.) – 4 Clock Frequency with External Feedback – MHz fmax (Tog.) – 5 Clock Frequency, Max. Toggle – MHz tsu1 – 6 GLB Reg. Setup Time before Clock,4 PT Bypass – ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – ns th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass – ns tsu2 – 9 GLB Reg. Setup Time before Clock – ns tco2 – 10 GLB Reg. Clock to Output Delay – ns th2 – 11 GLB Reg. Hold Time after Clock – ns tr1 A 12 Ext. Reset Pin to Output Delay – ns trw1 – 13 Ext. Reset Pulse Duration – ns tptoeen B 14 Input to Output Enable – ns tptoedis C 15 Input to Output Disable – ns twh – 18 External Synchronous Clock Pulse Duration, High 5.0 ns twl – 19 External Synchronous Clock Pulse Duration, Low 5.0 ns tsu3 – 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) – ns th3 – 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) – ns 56.0 100 9.0 0.0 11.0 0.0 10.0 4.0 0.0 17.5 7.0 8.0 15.0 18.0 18.0 ( ) twh + tw1 tgoeen B 16 Global OE Output Enable – ns 12.0 tgoedis C 17 Global OE Output Disable – ns -90 MIN. MAX. – 10.0 90.0 – 0.0 8.5 0.0 6.5 4.0 4.0 3.5 – 0.0 – 69.0 125 7.5 6.0 7.0 13.5 15.0 15.0 12.5 – 9.0 – 9.0 12.0 -80 MIN. MAX. – 12.0 80.0 – 4.5 4.5 61.0 111 8.5 0.0 10.0 0.0 8.0 3.5 0.0 15.0 6.5 7.5 14.0 16.5 16.5 – 10.0 – 10.0 External Timing Parameters Over Recommended Operating Conditions

Specifications ispLSI and pLSI 1032E GRP Delay, 32 GLB Loads tiobp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2-0036A/1032E Inputs UNITS -100

22 I/O Register Bypass ns

tiolat 23 I/O Latch Delay ns tgrp32 33 ns GLB t1ptxor 36 1 Prod.Term/XOR Path Delay ns t20ptxor 37 20 Prod. Term/XOR Path Delay ns txoradj 38 XOR Adjacent Path Delay ns tgbp 39 GLB Register Bypass Delay ns tgsu 40 GLB Register Setup Time before Clock ns tgh 41 GLB Register Hold Time after Clock ns tgco 42 GLB Register Clock to Output Delay ns tgro 43 GLB Register Reset to Output Delay ns tptre 44 GLB Prod.Term Reset to Register Delay ns tptoe 45 GLB Prod. Term Output Enable to I/O Cell Delay ns tptck 46 GLB Prod. Term Clock Delay ns ORP GRP t4ptbpc 34 4 Prod.Term Bypass Path Delay (Combinatorial) ns t4ptbpr 35 4 Prod. Term Bypass Path Delay (Registered) ns torp 47 ORP Delay ns torpbp 48 ORP Bypass Delay ns tiosu 24 I/O Register Setup Time before Clock ns tioh 25 I/O Register Hold Time after Clock ns tioco 26 I/O Register Clock to Out Delay ns tior 27 I/O Register Reset to Out Delay ns tdin 28 Dedicated Input Delay ns tgrp16 32 GRP Delay, 16 GLB Loads ns tgrp8 31 GRP Delay, 8 GLB Loads ns tgrp4 30 GRP Delay, 4 GLB Loads ns tgrp1 29 GRP Delay, 1 GLB Load ns 0.0 -125 0.1 4.5 2.9 3.0 0.0 0.3 1.9 3.8 3.6 5.0 5.0 0.4 2.3 4.9 3.9 5.4 3.9 4.0 4.0 1.0 0.0 4.6 4.6 2.3 2.8 2.3 2.0 1.8 0.5 5.8 3.5 3.5 0.0 0.3 2.3 4.2 4.6 5.8 6.3 1.0 2.5 6.2 4.5 7.2 5.3 5.3 4.7 1.0 5.0 5.0 2.7 3.0 2.4 2.4 1.9 Internal Timing Parameters1

Specifications ispLSI and pLSI 1032E Internal Timing Parameters1 USE 1032E-100 FOR NEW DESIGNS GRP Delay, 32 GLB Loads tiobp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2-0036B/1032E Inputs UNITS -80 MIN. -70 MIN.MAX. MAX.DESCRIPTION# 2PARAM.

22 I/O Register Bypass – ns

tiolat 23 I/O Latch Delay – ns tgrp32 33 –n s GLB t1ptxor 36 1 Prod.Term/XOR Path Delay – ns t20ptxor 37 20 Prod. Term/XOR Path Delay – ns txoradj 38 XOR Adjacent Path Delay – ns tgbp 39 GLB Register Bypass Delay –n s tgsu 40 GLB Register Setup Time before Clock ns tgh 41 GLB Register Hold Time after Clock ns tgco 42 GLB Register Clock to Output Delay – ns tgro 43 GLB Register Reset to Output Delay – ns tptre 44 GLB Prod.Term Reset to Register Delay – ns tptoe 45 GLB Prod. Term Output Enable to I/O Cell Delay – ns tptck 46 GLB Prod. Term Clock Delay ns ORP GRP MIN. MAX. t4ptbpc 34 4 Prod.Term Bypass Path Delay (Combinatorial) – ns t4ptbpr 35 4 Prod. Term Bypass Path Delay (Registered) – ns 0.5 7.9 4.5 torp 47 ORP Delay – ns torpbp 48 ORP Bypass Delay – 0.0 ns tiosu 24 I/O Register Setup Time before Clock 3.5 ns tioh 25 I/O Register Hold Time after Clock 0.0 ns tioco 26 I/O Register Clock to Out Delay – ns tior 27 I/O Register Reset to Out Delay – ns tdin 28 Dedicated Input Delay – ns tgrp16 32 GRP Delay, 16 GLB Loads – ns tgrp8 31 GRP Delay, 8 GLB Loads – ns tgrp4 30 GRP Delay, 4 GLB Loads – ns tgrp1 29 GRP Delay, 1 GLB Load – ns 0.3 2.7 4.8 6.6 7.8 8.2 1.3 2.9 6.4 5.5 8.0 7.1 6.7 5.8 1.0 0.0 5.4 5.4 2.8 3.5 2.8 2.5 2.2 0.5 8.8 4.8 4.0 0.0 0.3 3.3 5.6 8.3 8.7 9.2 1.6 2.9 6.8 5.8 9.0 8.8 7.2 6.2 1.0 6.1 6.0 2.8 4.0 3.2 2.5 2.5 -90 0.2 6.8 4.1 3.5 0.0 0.3 2.3 4.4 5.6 6.8 7.1 0.4 2.9 6.3 5.1 7.1 5.7 6.1 5.3 1.0 0.0 5.0 5.0 2.6 3.2 2.6 2.3 2.1

Specifications ispLSI and pLSI 1032E Internal Timing Parameters1 tob 1. Internal Timing Parameters are not tested and are for reference only. Table 2-0037A/1032E Outputs UNITS -100

49 Output Buffer Delay ns

toen 51 I/O Cell OE to Output Enabled ns tgy0 54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk) ns Global Reset Clocks tgr 59 Global Reset to GLB and I/O Registers ns todis 52 I/O Cell OE to Output Disabled ns tgy1/2 55 Clk Delay, Y1 or Y2 to Global GLB Clk Line ns tgcp 56 Clk Delay, Clock GLB to Global GLB Clk Line ns tioy2/3 57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line ns tiocp 58 Clk Delay, Clk GLB to I/O Cell Global Clk Line ns tgoe 53 Global OE ns tsl 50 Output Buffer Delay, Slew Limited Adder ns -125 1.5 1.5 0.8 0.0 0.8 2.0 5.1 1.5 4.3 5.1 1.5 1.8 0.0 1.8 3.9 10.0 1.4 1.4 0.8 0.0 0.8 1.3 4.3 1.4 2.8 4.3 1.4 1.8 0.0 1.8 2.7 9.9

Specifications ispLSI and pLSI 1032E USE 1032E-100 FOR NEW DESIGNS Internal Timing Parameters1 tob 1. Internal Timing Parameters are not tested and are for reference only. Table 2-0037B/1032E Outputs UNITS -80 MIN. -70 MIN.MAX. MAX.DESCRIPTION#PARAM.

49 Output Buffer Delay – ns

toen 51 I/O Cell OE to Output Enabled – ns tgy0 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.5 ns Global Reset Clocks tgr 59 Global Reset to GLB and I/O Registers – ns todis 52 I/O Cell OE to Output Disabled – ns tgy1/2 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.6 ns tgcp 56 Clock Delay, Clock GLB to Global GLB Clock Line 0.8 ns tioy2/3 57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 0.0 ns tiocp 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line 0.8 ns tgoe 53 Global OE – ns MIN. MAX. tsl 50 Output Buffer Delay, Slew Limited Adder – ns 2.1 5.7 1.5 4.5 5.7 3.1 1.8 0.0 1.8 4.3 10.0 1.5 1.5 0.8 0.0 0.8 2.6 6.2 1.5 4.6 6.2 1.5 1.8 0.0 1.8 5.8 10.0 -90 1.4 2.4 0.8 0.0 0.8 1.7 5.3 1.4 4.5 5.3 2.9 1.8 0.0 1.8 3.7 10.0

Specifications ispLSI and pLSI 1032E ispLSI and pLSI 1032E Timing Model GLB Reg Delay I/O Pin (Output) ORP Delay 0491 Feedback Reg 4 PT Bypass 20 PT XOR Delays Control PTs Input Register Clock Distribution I/O Pin (Input) Y1,2,3 D Q GRP4 GLB Reg Bypass ORP Bypass DQ RST RE OE CK I/O Reg Bypass I/O CellORPGLBGRPI/O Cell #23 - 27 #30 #35 #34 Comb 4 PT Bypass #36 - 38 #55 - 58 #44 - 46 #54 #53 #47 #48 Reset Ded. In GOE 0,1 #28 #22 RST #59 #59 #39 #40 - 43 #51, 52 #49, 50 GRP Loading Delay #29, 31 - 33 Derivations of tsu, th and tco from the Product Term Clock1 tsu 2.2 ns Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min)) th Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor) tco Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) Table 2-0042a/1032E Derivations of tsu, th and tco from the Clock GLB1 tsu Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min)) th Clock (max) + Reg h - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor) tco Clock (max) + Reg co + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) 3.5 ns 10.9 ns 2.9 ns 2.7 ns 5.5 ns 1. Calculations are based upon timing specifications for the ispLSI and pLSI 1032E-125.

Figure 3. Typical Device Power Consumption vs fmax conditions and the program in the device, the actual I should be verified.

Specifications ispLSI and pLSI 1032E Pin Description Input - This pin performs two functions. When ispEN is logic low, it functions as pin to control the operation of the isp state machine. It is a dedicated input pin when ispEN is logic high. This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Input/Output Pins - These are the general purpose I/O pins used by the logic array. NAME Table 2-0002A/1032E PLCC PIN NUMBERS DESCRIPTION 26, 30, 34, 38, 45, 49, 53, 57, 68, 72, 76, 80, 11, 15, 27, 31, 35, 39, 46, 50, 54, 58, 69, 73, 77, 81, 12, 16, 28, 32, 36, 40, 47, 51, 55, 59, 70, 74, 78, 82, 13, 17, I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 I/O 48 - I/O 51 I/O 52 - I/O 55 I/O 56 - I/O 59 I/O 60 - I/O 63 29, 33, 37, 41, 48, 52, 56, 60, 71, 75, 79, 83, 10, 14, 66Y1 20Y0 42MODE/IN 12 Ground (GND)GND VccVCC 21, 65 NC 1 GOE 0/IN 43 Dedicated input pins to the device.IN 6, IN 7 GOE 1/IN 53 Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. 23ispEN/NC 1,2 Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 is also used as one of the two control pins for the isp state machine. It is a dedicated input pin when ispEN is logic high. 25SDI/IN 0 44SDO/IN 22 Output/Input - This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. It is a dedicated input pin when ispEN is logic high. 61SCLK/IN 3 2 Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. It is a dedicated input pin when ispEN is logic high. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. 24RESET Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. 63Y2 Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. 62Y3 1, 22, 43, 64 12, 26, 51, 76, 2, 24, 25, No connect. 27, 49, 50, 52, 74, 75, 77, 99, 100 1. NC pins are not to be connected to any ative signals, Vcc or GND. 2. Pins have dual function capability for ispLSI 1032E only. 3. Pins have dual function capability which is software selectable. TQFP PIN NUMBERS 17, 21, 29, 33, 40, 44, 48, 56, 67, 71, 79, 83, 90, 94, 98, 18, 22, 30, 34, 41, 45, 53, 57, 68, 72, 80, 84, 91, 95, 19, 23, 31, 35, 42, 46, 54, 58, 69, 73, 81, 85, 92, 96, 20, 28, 32, 36, 43, 47, 55, 59, 70, 78, 82, 86, 93, 97, 89, 13, 38, 63, 88

Specifications ispLSI and pLSI 1032E ispLSI and pLSI 1032E 84-Pin PLCC Pinout Diagram I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 GOE 0/IN 4 VCC GND SCLK/IN 3 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 IN 7 VCC GND 1,2ispEN/NC RESET 2SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 GND GOE 1/IN 5 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 2MODE/IN 1 GND 2SDO/IN 2 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 ispLSI 1032E pLSI 1032E Top View 0123-32-isp 1. NC pins are not to be connected to any active signals, Vcc or GND. 2. Pins have dual function capability for ispLSI 1032E only (except pin 23, which is ispEN only). 3. Pins have dual function capability which is software selectable. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 1 1 1 0 987654321 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 Pin Configurations

Specifications ispLSI and pLSI 1032E NC NC I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 IN 7 VCC GND ispEN RESET 1SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 NC NC NC NC I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 GOE 0/IN 4 VCC GND SCLK/IN 3 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 NC NC NC NC I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 GND GOE 1/IN 5 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 NC NC NC NC I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 1MODE/IN1 GND 1SDO/IN 2 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 NC NC 100 ispLSI 1032E Top View 1. Pins have dual function capability. 2. Pins have dual function capability which is software selectable. 0766A-32E-isp ispLSI 1032E 100-Pin TQFP Pinout Diagram Pin Configurations

Specifications ispLSI and pLSI 1032E Note: Use ispLSI for all new designs. Part Number Description Device Number Grade Blank = Commercial I = Industrial 1032E XXX X X X Speed 125 = 125 MHz fmax 100 = 100 MHz fmax 90 = 90 MHz fmax 80 = 80 MHz fmax 70 = 70 MHz fmax Power L = Low Package J = PLCC T = TQFP Device Family 0212/1032E (is)pLSI ispLSI and pLSI 1032E Ordering Information 100 100 84-Pin PLCC10 ispLSI 1032E-100LJ 100-Pin TQFPispLSI 1032E-100LT pLSI Table 2-0041A/1032E 84-Pin PLCC10 ispLSI 1032E-90LJ* 100-Pin TQFPispLSI 1032E-90LT* 80 12 84-Pin PLCCispLSI 1032E-80LJ* FAMILY fmax (MHz) 125 ORDERING NUMBER PACKAGEtpd (ns) 7.5 ispLSI 84-Pin PLCCispLSI 1032E-125LJ 100-Pin TQFP 84-Pin PLCC ispLSI 1032E-80LT* ispLSI 1032E-70LJ 100-Pin TQFPispLSI 1032E-70LT 125 100-Pin TQFP7.5 ispLSI 1032E-125LT 84-Pin PLCC12 pLSI 1032E-80LJ* 84-Pin PLCCpLSI 1032E-70LJ 125 100 84-Pin PLCC7.5 pLSI 1032E-125LJ 84-Pin PLCCpLSI 1032E-100LJ 90 84-Pin PLCC10 pLSI 1032E-90LJ* COMMERCIAL *Use ispLSI 1032E-100 for all new designs. Table 2-0041B/1032E FAMILY fmax (MHz) ORDERING NUMBER PACKAGE 84-Pin PLCC 100-Pin TQFP tpd (ns) ispLSI ispLSI 1032E-70LJI ispLSI 1032E-70LTI INDUSTRIAL