GAL16V8D-10LJ

GAL16V8_98 LATTICE | Alldatasheet

Document overview

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Technical content

Features

• HIGH PERFORMANCE E 2CMOS ® TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 3.0 ns Maximum from Clock Input to Data Output — UltraMOS ® Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR — 75mA Typ Icc on Low Power Device — 45mA Typ Icc on Quarter Power Device
• ACTIVE PULL-UPS ON ALL PINS

2 CELL TECHNOLOGY

— Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity — Also Emulates 20-pin PAL ® Devices with Full Function/Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability
• APPLICATIONS INCLUDE: — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Description

The GAL16V8, at 3.5 ns maximum propagation delay time, com- bines a high performance CMOS process with Electrically Eras- able (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and ef- ficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configura- tions possible with the GAL16V8 are the PAL architectures listed in the table of the macrocell description section. GAL16V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and function- ality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Functional Block Diagram Pin Configuration

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010 17 55P Q01-D8V61LAGP IDcitsalPniP-02 55J Q01-D8V61LAGC CLPdaeL-02 511 8V61LAG0 1-DP L PIDcitsalPniP-02 511 8V61LAG0 1-DJ L CCLPdaeL-02 512 10 15 5P Q51-D8V61LAGP IDcitsalPniP-02 55J Q51-D8V61LAGC CLPdaeL-02 09P L51-D8V61LAGP IDcitsalPniP-02 09J L51-D8V61LAGC CLPdaeL-02 525 12 15 5P Q52-D8V61LAGP IDcitsalPniP-02 55J Q52-D8V61LAGC CLPdaeL-02 09P L52-D8V61LAGP IDcitsalPniP-02 09J L52-D8V61LAGC CLPdaeL-02 )sn(dpT) sn(usT) sn(ocT) Am(ccI# gniredrOe gakcaP 5.77 5 0 31 8V61LAG7 -DI PL PIDcitsalPniP-02 031 8V61LAG7 -DI JL CCLPdaeL-02 010 17 0 31 8V61LAG0 1-DI PL PIDcitsalPniP-02 031 8V61LAG0 1-DI JL CCLPdaeL-02 512 10 10 31I PL51-D8V61LAGP IDcitsalPniP-02 031I JL51-D8V61LAGC CLPdaeL-02 023 11 15 6I PQ02-D8V61LAGP IDcitsalPniP-02 56I JQ02-D8V61LAGC CLPdaeL-02 525 12 15 6I PQ52-D8V61LAGP IDcitsalPniP-02 56I JQ52-D8V61LAGC CLPdaeL-02 031I PL52-D8V61LAGP IDcitsalPniP-02 031I JL52-D8V61LAGC CLPdaeL-02 Industrial Grade Specifications Commercial Grade Specifications Part Number Description

The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accom- plished by development software/hardware and is completely trans- parent to the user. There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes are illustrated in the following pages. Two global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individ- ual architecture bits define all possible configurations in a GAL16V8 . The information given on these architecture bits is only to give a better understanding of the device. Compiler software will trans- parently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. The following is a list of the PAL architectures that the GAL16V8 can emulate. It also shows the OLMC mode under which the GAL16V8 emulates the PAL architecture. PAL Architectures GAL16V8 Emulated by GAL16V8 Global OLMC Mode 16R8 Registered 16R6 Registered 16R4 Registered 16RP8 Registered 16RP6 Registered 16RP4 Registered 16L8 Complex 16H8 Complex 16P8 Complex 10L8 Simple 12L6 Simple 14L4 Simple 16L2 Simple 10H8 Simple 12H6 Simple 14H4 Simple 16H2 Simple 10P8 Simple 12P6 Simple 14P4 Simple 16P2 Simple Software compilers support the three different global OLMC modes as different device types. These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the soft- ware to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types listed in the table can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1 and pin 11 are permanently configured as clock and output enable, respectively. These pins cannot be con- figured as dedicated inputs in the registered mode. In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins ( pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated combinatorial output. Registered Complex Simple Auto Mode Select ABEL P16V8R P16V8C P16V8AS P16V8 CUPL G16V8MS G16V8MA G16V8AS G16V8 LOG/iC GAL16V8_R GAL16V8_C7 GAL16V8_C8 GAL16V8 OrCAD-PLD "Registered" 1 "Complex"1 "Simple"1 GAL16V8A PLDesigner P16V8R 2 P16V8C 2 P16V8C 2 P16V8A TANGO-PLD G16V8R G16V8C G16V8AS 3 G16V8 1) Used with Configuration keyword. 2) Prior to Version 2.0 support. 3) Supported on Version 1.20 or later. Output Logic Macrocell (OLMC) Compiler Support for OLMC

In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Architecture configurations available in this mode are similar to the common 16R8 and 16RP4 devices with various permutations of polarity, I/O and register placement. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or I/ O. Up to eight registers or up to eight I/O's are possible in this mode. Dedicated input or output functions can be implemented as sub- sets of the I/O function. Registered outputs have eight product terms per output. I/O's have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page. Registered Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this output configuration. - Pin 1 controls common CLK for the registered outputs. - Pin 11 controls common OE for the registered outputs. - Pin 1 & Pin 11 are permanently configured as CLK & OE for registered output configuration. Combinatorial Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this output configuration. - Pin 1 & Pin 11 are permanently configured as CLK & OE for registered output configuration. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. DQ Q CLK OE XOR XOR Registered Mode

DIP & PLCC Package Pinouts 0000 0224 0256 0480 0512 0736 0768 0992 1024 1248 1280 1504 1536 1760 1792 2016 XOR-2048 AC1-2120 XOR-2049 AC1-2121 XOR-2050 AC1-2122 XOR-2051 AC1-2123 XOR-2052 AC1-2124 XOR-2053 AC1-2125 XOR-2054 AC1-2126 XOR-2055 AC1-2127

2824201612840 PTD

Registered Mode Logic Diagram

In the Complex mode, macrocells are configured as output only or I/O functions. Architecture configurations available in this mode are similar to the common 16L8 and 16P8 devices with programmable polarity in each macrocell. Up to six I/O's are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The two outer most macrocells (pins 12 & 19) do not have input capa- bility. Designs requiring eight I/O's can be implemented in the Registered mode. All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 1 and 11 are always available as data inputs into the AND array. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Combinatorial I/O Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1. - Pin 13 through Pin 18 are configured to this function. Combinatorial Output Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1. - Pin 12 and Pin 19 are configured to this function. XOR XOR Complex Mode

DIP & PLCC Package Pinouts 0000 0224 0256 0480 0512 0736 0768 0992 1024 1248 1280 1504 1536 1760 1792 2016 PTD 2128 2191 OLMC OLMC OLMC OLMC OLMC OLMC SYN-2192 AC0-2193 XOR-2055 AC1-2127 XOR-2054 AC1-2126 XOR-2053 AC1-2125 XOR-2052 AC1-2124 XOR-2051 AC1-2123 XOR-2050 AC1-2122 XOR-2049 AC1-2121 XOR-2048 AC1-2120 OLMC OLMC 2824201612840 Complex Mode Logic Diagram

In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common 10L8 and 12P6 devices with many permutations of ge- neric output polarity or input choices. All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has pro- grammable polarity. Pins 1 and 11 are always available as data inputs into the AND array. The center two macrocells (pins 15 & 16) cannot be used as input or I/O pins, and are only available as dedicated outputs. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram. Combinatorial Output with Feedback Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - All OLMC except pins 15 & 16 can be configured to this function. Combinatorial Output Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - Pins 15 & 16 are permanently configured to this function. Dedicated Input Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this configuration. - All OLMC except pins 15 & 16 can be configured to this function. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Vcc XOR Vcc XOR Simple Mode

DIP & PLCC Package Pinouts 0000 0224 0256 0480 0512 0736 0768 0992 1024 1248 1280 1504 1536 1760 1792 2016 PTD 2128 2191 XOR-2048 AC1-2120 OLMC XOR-2049 AC1-2121 XOR-2050 AC1-2122 XOR-2051 AC1-2123 XOR-2052 AC1-2124 XOR-2053 AC1-2125 XOR-2054 AC1-2126 XOR-2055 AC1-2127 OLMC OLMC OLMC OLMC OLMC OLMC OLMC SYN-2192 AC0-2193 2824201612840 Simple Mode Logic Diagram

VIL Input Low Voltage Vss – 0.5 — 0.8 V VIH Input High Voltage 2.0 — Vcc+1 V IIL1 Input or I/O Low Leakage Current 0V £ VIN £ VIL (MAX.) — — –100 mA IIH Input or I/O High Leakage Current 3.5 V £ VIN £ VCC ——1 0 mA VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V IOL Low Level Output Current L-3/-5 & -7 (Ind. PLCC) — — 16 mA L-7 (Except Ind. PLCC)/-10/-15/-25 — — 24 mA Q-10/-15/-20/-25 IOH High Level Output Current — — –3.2 mA IOS 2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25°C –30 — –150 mA Recommended Operating Conditions Commercial Devices: Supply voltage (VCC ) Industrial Devices: Supply voltage (VCC ) Absolute Maximum Ratings(1) Ambient Temperature with 1.Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. TYP . 3 MAX. UNITS COMMERCIAL ICC Operating Power VIL = 0.5V VIH = 3.0V L -3/-5/-7/-10 — 75 115 mA Supply Current ftoggle = 15MHz Outputs Open L-15/-25 — 75 90 mA INDUSTRIAL ICC Operating Power VIL = 0.5V VIH = 3.0V L -7/-10/-15/-25 — 75 130 mA Supply Current ftoggle = 15MHz Outputs Open Q -20/-25 — 45 65 mA 1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T A = 25 °C

tpd A Input or I/O to Comb. Output 1 3.5 1 5 1 7.5 ns tco A Clock to Output Delay 1 3 1 4 1 5 ns tcf2 — Clock to Feedback Delay — 2.5 — 3 — 3 ns tsu — Setup Time, Input or Feedback before Clock › 2.5 — 3 — 7 — ns th — Hold Time, Input or Feedback after Clock › 0— 0 —0— n s A Maximum Clock Frequency with 182 — 142.8 — 83.3 — MHz External Feedback, 1/(tsu + tco) A Maximum Clock Frequency with 200 — 166 — 100 — MHz Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with 250 — 166 — 100 — MHz No Feedback twh — Clock Pulse Duration, High 2 4 —3 4 —5—n s twl — Clock Pulse Duration, Low 2 4 —3 4 —5—n s ten B Input or I/O to Output Enabled — 4.5 — 6 — 9 ns B OE to Output Enabled — 4.5 — 6 — 6 ns tdis C Input or I/O to Output Disabled — 4.5 — 5 — 9 ns C OE to Output Disabled — 4.5 — 5 — 6 ns MIN. MAX. SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS C I Input Capacitance 8 pF V CC = 5.0V, VI = 2.0V C I/O I/O Capacitance 8 pF V CC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. AC Switching Characteristics Over Recommended Operating Conditions MIN. MAX. UNITSPARAMETER TEST COND 1. DESCRIPTION COM / INDCOM 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. Characterized but not 100% tested. 4) Characterized but not 100% tested. fmax 3 MIN. MAX. COM Capacitance (TA = 25°C, f = 1.0 MHz)

tpd A Input or I/O to Comb. Output 3 10 3 15 3 20 3 25 ns tco A Clock to Output Delay 2 7 2 10 2 11 2 12 ns tcf2 — Clock to Feedback Delay — 6 — 8 — 9 — 10 ns tsu — Setup Time, Input or Fdbk before Clk › 10 — 12 — 13 — 15 — ns th — Hold Time, Input or Fdbk after Clk › 0— 0— 0— 0— n s A Maximum Clock Frequency with 58.8 — 45.5 — 41.6 — 37 — MHz External Feedback, 1/(tsu + tco) fmax 3 A Maximum Clock Frequency with 62.5 — 50 — 45.4 — 40 — MHz Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with 62.5 — 62.5 — 50 — 41.6 — MHz No Feedback twh — Clock Pulse Duration, High 8 — 8 — 10 — 12 — ns twl — Clock Pulse Duration, Low 8 — 8 — 10 — 12 — ns ten B Input or I/O to Output Enabled — 10 — 15 — 18 — 20 ns t B OE to Output Enabled — 10 — 15 — 18 — 20 ns tdis C Input or I/O to Output Disabled — 10 — 15 — 18 — 20 ns t C OE to Output Disabled — 10 — 15 — 18 — 20 ns AC Switching Characteristics Over Recommended Operating Conditions UNITS -25 MIN. MAX. -20 MIN. MAX. -15 MIN. MAX. -10 MIN. MAX. PARAM. DESCRIPTIONTEST COND 1. COM / IND COM / IND IND COM / IND SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS C I Input Capacitance 8 pF V CC = 5.0V, VI = 2.0V C I/O I/O Capacitance 8 pF V CC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. Characterized but not 100% tested. Specifications GAL16V8D Capacitance (TA = 25°C, f = 1.0 MHz)

Registered OutputCombinatorial Output OEOEOEOEOE to Output Enable/DisableInput or I/O to Output Enable/Disable fmax with Feedback Clock Width COMBINATIONAL OUTPUT VALID INPUTINPUT or I/O FEEDBACK tpd COMBINATIONAL OUTPUT INPUT or I/O FEEDBACK tentdis CLK (w/o fb) 1/fmax twltwh OE REGISTERED OUTPUT tentdis CLK REGISTERED FEEDBACK tcf tsu 1/fmax (internal fdbk) INPUT or I/O FEEDBACK REGISTERED OUTPUT CLK VALID INPUT (external fdbk) tsu tco th 1/fmax Switching Waveforms

fmax with Internal Feedback 1/(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. REGISTERLOGIC ARRAY CLK tsu + th REGISTERLOGIC ARRAY tcotsu CLK Test Condition R 1 R 2 C L A 200 W 390W 50pF B Active High ¥ 390W 50pF Active Low 200 W 390W 50pF C Active High ¥ 390W 5pF Active Low 200 W 390W 5pF CLK REGISTER LOGIC ARRAY tcf tpd TEST POINT C *L FROM OUTPUT (O/Q) UNDER TEST +5V *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE R 2 R 1 Input Pulse Levels Table 2-0003/16V8 Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 1.5V 1.5V See figure at right 3-state levels are measured 0.5V from steady-state active level. 2 – 3ns 10% – 90% 1.5ns 10% – 90% GAL16V8D-10 (and slower) GAL16V8D-3/-5/-7 GAL16V8D (except -3) Output Load Conditions (see figure above) fmax Descriptions Switching Test Conditions

*CL includes test fixture and probe capacitance. Electronic Signature An electronic signature is provided in every GAL16V8 device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calcula- tions. Changing the electronic signature will alter the checksum. Security Cell A security cell is provided in the GAL16V8 devices to prevent un- authorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is pro- grammed. The Electronic Signature is always available to the user, regardless of the state of this control cell. Latch-Up Protection GAL16V8 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential of latch-up caused by negative input undershoots. Ad- ditionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups in order to eliminate latch-up due to output overshoots. Device Programming GAL devices are programmed using a Lattice Semiconductor- approved Logic Programmer, available from a number of manu- facturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. -60 -20 -40 Input Voltage (Volts) Input Current (uA) TEST POINT Z0 = 50Ω , CL = 35pF*FROM OUTPUT (O/Q) UNDER TEST +1.45V R 1 GAL16V8D-3 Output Load Conditions (see figure at right) Test Condition R 1 CL A5 0 W 35pF B High Z to Active High at 1.9V 50W 35pF High Z to Active Low at 1.0V 50W 35pF C Active High to High Z at 1.9V 50W 35pF Active Low to High Z at 1.0V 50W 35pF Switching Test Conditions (Continued) Output Register Preload When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. GAL16V8 devices include circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing text vectors perform output register preload automatically. Input Buffers GAL16V8 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The GAL16V8 input and I/O pins have built-in active pull-ups. As a result, unused inputs and I/O's will float to a TTL "high" (logical "1"). Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to another active input, V CC , or Ground. Doing this will tend to improve noise immunity and re- duce I CC for the device. Typical Input Pull-up Characteristic

Typ. Vref = 3.2V Typical Output Typ. Vref = 3.2V Typical Input INPUT/OUTPUT EQUIVALENT SCHEMATICS Circuitry within the GAL16V8 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1ms MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Be- cause of the asynchronous nature of system power-up, some Vcc PIN Vcc Vref Active Pull-up Circuit ESD Protection Circuit ESD Protection Circuit Vcc PIN Vcc PIN VrefTri-State Control Active Pull-up Circuit Feedback (To Input Buffer) PIN Feedback Data Output Vcc CLK INTERNAL REGISTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Vcc (min.) tpr Internal Register Reset to Logic "0" Device Pin Reset to Logic "1" twl tsu conditions must be met to provide a valid power-up reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Power-Up Reset Input/Output Equivalent Schematics

0.8 0.9 1.2 Supply Voltage (V) Normalized Tpd Normalized Tco vs Vcc 0.8 0.9 1.1 1.2 Supply Voltage (V) Normalized Tco Normalized Tsu vs Vcc 0.8 0.9 1.1 1.2 Supply Voltage (V) Normalized Tsu Normalized Tpd vs Temp 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Tpd Normalized Tco vs Temp 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Tco Normalized Tsu vs Temp 0.7 0.9 1.1 - 5 5 - 2 5 0 2 55 07 5 1 0 0 1 2 5 Temperature (deg. C) Normalized Tsu PT H->L PT L->H PT H->L PT L->H1.1 PTH->L PT L->H 1.3 1.2 0.8 RISE FALL PT H->L PT L->H RISE FALL Delta Tpd vs # of Outputs Switching -0.4 -0.3 -0.2 -0.1 12345678 Number of Outputs Switching Delta Tpd (ns) Delta Tco vs # of Outputs Switching -0.4 -0.3 -0.2 -0.1 12345678 Number of Outputs Switching Delta Tco (ns) Delta Tpd vs Output Loading 0 50 100 150 200 250 300 Output Loading (pF) Delta Tpd (ns) Delta Tco vs Output Loading 0 50 100 150 200 250 300 Output Loading (pF) Delta Tco (ns) RISE FALL RISE FALL RISE FALL RISE FALL GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams

0.25 0.5 0.75 0 1 02 03 04 0 Iol (mA) Vol (V) Voh vs Ioh 0 1 02 03 04 05 0 Ioh (mA) Voh (V) Voh vs Ioh 2.5 2.75 3.25 01234 Ioh (mA) Voh (V) Normalized Icc vs Vcc 0.8 0.9 1.1 1.2 Supply Voltage (V) Normalized Icc Normalized Icc vs Temp 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Icc Normalized Icc vs Freq. 0.9 0.95 1.05 1.1 1.15 1.2 02 5 5 0 7 5 1 0 0 Frequency (MHz) Normalized Icc Delta Icc vs Vin (1 input) 00 . 511 . 522 . 533 . 54 Vin (V) Delta Icc (mA) Input Clamp (Vik) -2 -1.5 -1 -0.5 0 Vik (V) Iik (mA) GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams

0.9 0.95 1.05 1.1 1.15 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Tpd RISE FALL Normalized Tco vs Vcc 0.9 0.95 1.05 1.1 1.15 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Tco RISE FALL Normalized Tsu vs Vcc 0.8 0.9 1.1 1.2 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Tsu RISE FALL Normalized Tpd vs Temp 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Tpd RISE FALL Normalized Tsu vs Temp 0.8 0.9 1.1 1.2 1.3 - 5 5 - 2 5 0 2 55 07 5 1 0 0 1 2 5 Temperature (deg. C) Normalized Tsu RISE FALL Normalized Tco vs Temp 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Tco RISE FALL Delta Tpd vs # of Outputs Switching -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 12345678 Number of Outputs Switching Delta Tpd (ns) RISE FALL Delta Tco vs # of Outputs Switching -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 12345678 Number of Outputs Switching Delta Tco (ns) RISE FALL Delta Tpd vs Output Loading 0 50 100 150 200 250 300 Output Loading (pF) Delta Tpd (ns) RISE FALL Delta Tco vs Output Loading 0 50 100 150 200 250 300 Output Loading (pF) Delta Tco (ns) RISE FALL GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams

0.1 0.2 0.3 0.4 0.5 1 6 11 16 21 26 Iol (mA) Vol (V) Voh vs Ioh 0 5 10 15 20 25 Ioh (mA) Voh (V) Voh vs Ioh 2.5 3.5 Ioh (mA) Voh (V) Normalized Icc vs Vcc 0.8 0.9 1.1 3 3.15 3.3 3.45 3.6 Supply Voltage (V) Normalized Icc Normalized Icc vs Temp 0.8 0.9 1.1 1.2 - 5 5 - 2 5 0 2 55 08 8 1 0 0 1 2 5 Temperature (deg. C) Normalized Icc Normalized Icc vs Freq 0.95 1.05 1.1 1.15 11 5 2 5 5 0 7 5 1 0 0 Frequency (MHz) Normalized Icc Input Clamp (Vik) Vik (V) Iik (mA) Delta Icc vs Vin (1 input) Vin (V) Delta Icc (mA) GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams

0.8 0.9 1.1 1.2 Supply Voltage (V) Normalized Tpd PT H->L PT L->H Normalized Tco vs Vcc 0.8 0.9 1.1 1.2 Supply Voltage (V) Normalized Tco RISE FALL Normalized Tsu vs Vcc 0.8 0.9 1.1 1.2 Supply Voltage (V) Normalized Tsu PT H->L PT L->H Normalized Tpd vs Temp 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Tpd PT H->L PT L->H Normalized Tco vs Temp 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Tco RISE FALL Normalized Tsu vs Temp 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Tsu PT H->L PT L->H Delta Tpd vs # of Outputs Switching -1.2 -0.8 -0.6 -0.4 -0.2 12345678 Number of Outputs Switching Delta Tpd (ns) RISE FALL Delta Tco vs # of Outputs Switching -1.2 -0.8 -0.6 -0.4 -0.2 12345678 Number of Outputs Switching Delta Tco (ns) RISE FALL Delta Tpd vs Output Loading 0 50 100 150 200 250 300 Output Loading (pF) Delta Tpd (ns) RISE FALL Delta Tco vs Output Loading 0 50 100 150 200 250 300 Output Loading (pF) Delta Tco (ns) RISE FALL GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams

0.2 0.4 0.6 0 1 02 03 04 0 Iol (mA) Vol (V) Voh vs Ioh 0 1 02 03 04 05 0 Ioh (mA) Voh (V) Voh vs Ioh 3.2 3.4 3.6 3.8 01234 Ioh (mA) Voh (V) Normalized Icc vs Vcc 0.8 0.9 1.1 1.2 Supply Voltage (V) Normalized Icc Normalized Icc vs Temp 0.7 0.8 0.9 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 Temperature (deg. C) Normalized Icc Normalized Icc vs Freq. 0.8 0.9 1.1 1.2 1.3 1.4 0 25 50 75 100 Frequency (MHz) Normalized Icc Delta Icc vs Vin (1 input) 0 0.5 1 1.5 2 2.5 3 3.5 4 Vin (V) Delta Icc (mA) Input Clamp (Vik) -2 -1.5 -1 -0.5 0 Vik (V) Iik (mA) GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams