PALLV16V8-10JC

PLV16V8 LATTICE | Alldatasheet

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Publication# 17713 Rev: E Amendment/0 Issue Date: November 1998 COM’L:-10 IND:-20 PALLV16V8-10 and PALLV16V8Z-20 Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS N Low-voltage operation, 3.3 V JEDEC compatible CC = +3.0 V to +3.6 V N Pin and function compatible with all 20-pin PAL devices N Electrically-erasable CMOS technology provides reconfigurable logic and full testability N Direct plug-in replacement for the PAL16R8 series N Designed to interface with both 3.3-V and 5-V logic N Outputs programmable as registered or combinatorial in any combination N Programmable output polarity N Programmable enable/disable control N Preloadable output registers for testability N Automatic register reset on power up N Cost-effective 20-pin plastic DIP , PLCC, and SOIC packages N Extensive third-party software and programmer support N Fully tested for 100% programming and functional yields and high reliability GENERAL DESCRIPTION The PALLV16V8 is an advanced PAL device built with low-voltage, high-speed, electrically-erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALLV16V8 will directly replace the PAL16R8, with the exception of the PAL16C1. The PALLV16V8Z provides zero standby power and high speed. At 30- µ A maximum standby current, the PALLV16V8Z allows battery powered operation for an extended period. The PALLV16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floating-gate cells in the AND logic array that can be erased electrically. The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell.

2 PALLV16V8-10 and PALLV16V8Z-20 Families

The PALLV16V8 is a low-voltage, EE CMOS version of the PALCE16V8. The PALLV16V8Z is a low-voltage, EE CMOS version of the PALCE16V8. In addition, the PALLV16V8Z has zero standby power and an unused product term disable feature for reduced power consumption. The PALLV16V8 is a universal PAL device. It has eight independently configurable macrocells (MC -MC ). Each macrocell can be configured as registered output, combinatorial output, combinatorial I/O or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Pins 1 and 11 serve either as array inputs or as clock (CLK) and output enable (OE ), respectively, for all flip-flops. Unused input pins should be tied directly to V CC or GND. Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state and product terms with both true and complement of any input signal connected assume a logical LOW state. The programmable functions on the PALLV16V8 are automatically configured from the user’s design specification. The design specification is processed by development software to verify the design and create a programming file. This file, once downloaded to a programmer, configures the device according to the user’s desired function. Programmable AND Array 32 x 64 MACRO MC 0 MACRO MC 1 MACRO MC 2 MACRO MC 3 MACRO MC 4 MACRO MC 5 MACRO MC 6 MACRO MC 7 OE /I9 I/O0 I/O1 I/O2 I/O3 I/O4 I1 - I8 CLK/I0 17713D-1I/O5 I/O6 I/O7

will supply device codes for the standard PAL device architectures to be used with the PALLV16V8. user to use existing standard PAL device JEDEC files without making any changes to them. PALLV16V8 device code. This option allows full utilization of the macrocell. sets the output as either active low or active high for the individual macrocell. 17713D-004*In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer. Figure 1. PALLV16V8 Macrocell

4 PALLV16V8-10 and PALLV16V8Z-20 Families

SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being the adjacent pin for MC and OE the adjacent pin for MC Registered Output Configuration The control bit settings are SG0 = 0, SG1 = 1 and SL0 x =0. There is only one registered configuration. All eight product terms are available as inputs to the OR gate. Data polarity is determined by SL1 x The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The output buffer is enabled by OE. Combinatorial Configurations The PALLV16V8 has three combinatorial output configurations: dedicated output in a non- registered device, I/O in a non-registered device and I/O in a registered device. Dedicated Output In a Non-Registered Device The control bit settings are SG0 = 1, SG1 = 0 and SL0 x =0. All eight product terms are available to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the exception of MC and MC . MC and MC do not use feedback in this mode. Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin 1 will use the feedback path of MC and pin 11 will use the feedback path of MC Combinatorial I/O In a Non-Registered Device The control bit settings are SG0 = 1, SG1 = 1, and SL0 x =1. Only seven product terms are available to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as an input. Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as inputs. Pin 1 will use the feedback path of MC and pin 11 will use the feedback path of MC Combinatorial I/O in a Registered Device The control bit settings are SG0 = 0, SG1 = 1 and SL0 x =1. Only seven product terms are available to the OR gate. The eighth product term is used as the output enable. The feedback signal is the corresponding I/O signal. Dedicated Input Configuration The control bit settings are SG0 = 1, SG1 = 0 and SL0 x =1. The output buffer is disabled. Except for MC and MC , the feedback signal is an adjacent I/O. For MC and MC , the feedback signals are pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2.

in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts. Table 1. Macrocell Configuration

010 Registered

011 Combinatorial

111 Combinatorial

6 PALLV16V8-10 and PALLV16V8Z-20 Families

Figure 2. Macrocell Configurations

PALLV16V8-10 and PALLV16V8Z-20 Families 7 Benefits of Lower Operating Voltage The PALLV16V8 has an operating voltage range of 3.0V to 3.6 V. Low voltage allows for lower operating power consumption, longer battery life, and/or smaller batteries for notebook applications. The PALLV16V8 inputs accept up to 5.5 V, so they are safe for mixed voltage design. Because power is proportional to the square of the voltage, reduction of the supply voltage from 5.0 V to 3.3 V significantly reduces power consumption. This directly translates to longer battery life for portable applications. Lower power consumption can also be used to reduce the size and weight of the battery. Thus, 3.3-V designs facilitate a reduction in the form factor. A lower operating voltage results in a reduction of I/O voltage swings. This reduces noise generation and provides a less hostile environment for board design. A lower operating voltage also reduces electromagnetic radiation noise and makes obtaining FCC approval easier. Power-Up Reset All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALLV16V8 will depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial is selected, the output will be a function of the logic. Register Preload The register on the PALLV16V8 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. The preload function is not disabled by the security bit. This allows functional testing after the security bit is programmed. Security Bit A security bit is provided on the PALLV16V8 as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. However, programming and verification are also defeated by the security bit. The bit can only be erased in conjunction with the array during an erase cycle. Electronic Signature Word An electronic signature word is provided in the PALLV16V8 device. It consists of 64 bits of programmable memory that can contain user-defined data. The signature data is always available to the user independent of the security bit. Programming and Erasing The PALLV16V8 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its unprogrammed state. Erasure is automatically performed by the programming hardware. No special erase operation is required.

8 PALLV16V8-10 and PALLV16V8Z-20 Families

The PALLV16V8 offers a very high level of built-in quality. The erasability if the device provides a direct means of verifying performance of all the AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to yield the highest programming yields and post-programming function yields in the industry. Technology The high-speed PALLV16V8Z is fabricated with Vantis’ advanced electrically-erasable (EE) CMOS process. The array connections are formed with proven EE cells. This technology provides strong input-clamp diodes and a grounded substrate for clean switching. Zero-Standby Power Mode The PALLV16V8 features a zero-standby power mode. When none of the inputs switch for an extended period (typically 50 ns), the PALLV16V8Z will go into standby mode, shutting down most of its internal circuitry. The current will go to almost zero (I CC < 30 µ A). The outputs will maintain the states held before the device went into the standby mode. There is no speed penalty associated with coming out of standby mode. When any input switches, the internal circuitry is fully enabled, and power consumption returns to normal. This feature results in considerable power savings for operation at low to medium frequencies. This saving is illustrated in the I CC vs. frequency graph. The PALLV16V8Z-20 has the free-running-clock feature. This means that if one or more registers are used, switching only the CLK will not wake up the logic array or any macrocell. The device will not be in standby mode because the CLK buffer will draw some current, but dynamic I CC will typically be less than 2 mA. Product-Term Disable On a programmed PALLV16V8Z, any product terms that are not used are disabled. Power is cut off from these product terms so that they do not draw current. As shown in the I CC vs. frequency graph, product-term disabling results in considerable power savings. This saving is greater at the higher frequencies. Further hints on minimizing power consumption can be found in a separate document entitled, Minimizing Power Consumption with Zero-Power PLDs

PALLV16V8-10 and PALLV16V8Z-20 Families 9 LOGIC DIAGRAM 03 47 8 1 1 1 2 1 5 1 6 1 9 2 0 2 3 2 4 2 7 2 8 3 1 03 47 8 1 1 1 2 1 5 1 6 1 9 2 0 2 4 2 7 2 8 3 123 CLK/I0 1 I3 4 CLK OE 1 1 0 X 1 0 SG1 SL0 7 1 1 0 X 1 0 SG1 SL0 5 1 1 0 X 1 0 SG1 SL0 4 SG1 1 1 0 X 1 0DQ Q 1 0 1 1 1 1 1 0 0 0 0 1 VCC SL0 5 0 X SG1 1 1 0 X 1 0DQ Q 1 0 1 1 1 1 1 0 0 0 0 1 VCC SL0 4 0 X 1 1 0 X 1 0 SG1 SL0 6 SG1 1 1 0 X 1 0DQ Q 1 0 1 1 1 1 1 0 0 0 0 1 VCC SL0 6 0 X SG0 1 1 0 X 1 0DQ Q 1 0 1 1 0 X 1 1 1 0 0 0 0 1 VCC I/O416 I/O5 I/O6 I/O719 SL1 7 SL16 SL1 5 SL1 4

20 VCC

10 PALLV16V8-10 and PALLV16V8Z-20 Families

LOGIC DIAGRAM (CONTINUED) 03 47 8 1 1 1 2 1 5 1 6 1 9 2 0 2 3 2 4 2 7 2 8 3 1 0 3 4 7 8 1 11 2 1 51 6 1 92 0 2 32 4 2 72 8 3 1 CLK OE 1 1 0 X 1 0 SG1 SL0 3 1 1 0 X 1 0 SG1 SL0 1 1 1 0 X 1 0 SG1 SL0 0 1 1 0 X 1 0 SG1 SL0 2 OE/I 1 1 0 X 1 0DQ Q 1 0 1 1 0 X 1 1 1 0 0 0 0 1 SG0 VCC SG1 1 1 0 X 1 0DQ Q 1 0 1 1 1 1 1 0 0 0 0 1 VCC SL0 1 0 X 1 1 0 X 1 0DQ Q 1 0 1 1 1 1 1 0 0 0 0 1 VCC 0 X SG1 1 1 0 X 1 0DQ Q 1 0 1 1 1 1 1 0 0 0 0 1 VCC SL0 2 0 X SG1 SL0 3 I/O315 I/O214 I/O113 I/O012 SL1 3 SL1 2 SL1 1 SL1 0 SL00 GND 10 17713D-18

PALLV16V8-10 (Com’l) 11 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage with DC Output or I/O Latch-up Current Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Supply Voltage (VCC) Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of I IL and IOZL (or IIL and IOZL). 3. Not more than one output should be shortened at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is guaranteed worst case under test conditions. Refer to the I CC vs. frequency graph for typical measurements. Parameter Symbol Parameter Description Test Conditions Min Max Unit VOH Output HIGH Voltage VIN = VIH or VIL VCC = Min IOH = –2 mA 2.4 V IOH = –75 mA V CC - 0.2 V V VOL Output LOW Voltage VIN = VIH or VIL VCC = Min IOL = 2 mA 0.4 V IOL = 100 mA 0.2 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) 2.0 5.5 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current V IN = VCC, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage Current HIGH V OUT = VCC, VCC = Max, VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW V OUT = VCC, VCC = Max, VIN = VIH or VIL (Note 2) -100 µA ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 3) -50 -130 mA ICC Supply Current Outputs Open (I OUT = 0 mA), VCC = Max, f = 15 MHz (Note 4) 55 mA

12 PALLV16V8-10 (Com’l)

Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1 Notes: 1. See “Switching Test Circuit” for test conditions. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. t CF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. Parameter Symbol Parameter Description Test Condition Typ Unit CIN Input Capacitance V IN = 2.0 V VCC - 3.3 V, TA = 25°C, f = 1 MHz 5p F COUT Output Capacitance V OUT = 2.0 V 8 pF Parameter Symbol Parameter Description -10 UnitMin Max tPD Input or Feedback to Combinatorial Output (Note 2) 10 ns tS Setup Time from Input or Feedback to Clock 7 ns tH Hold Time 0 ns tCO Clock to Output 7n s tWL Clock Width LOW 6 ns tWH HIGH 6 ns fMAX Maximum Frequency (Notes 2 and 3) External Feedback 1/(t S + tCO) 71.4 MHz Internal Feedback (fCNT 1/(t S + tCF) 83.3 MHz No Feedback 1/(t S + tH) 83.3 MHz tPZX OE to Output Enable 10 ns tPXZ OE to Output Disable 10 ns tEA Input to Output Enable Using Product Term Control 12 ns tER Input to Output Disable Using Product Term Control 12 ns

PALLV16V8Z-20 (Ind) 13 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage with DC Output or I/O Latch-up Current Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. OPERATING RANGES Industrial (I) Devices Supply Voltage (VCC) with Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES Note: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of I IL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is guaranteed worst case under test conditions. Refer to the I CC vs. frequency graph for typical measurements. Parameter Symbol Parameter Description Test Conditions Min Max Unit VOH Output HIGH Voltage VIN = VIH or VIL VCC = Min IOH = –2 mA 2.4 V IOH = –75 µA V CC – 0.2 V V VOL Output LOW Voltage VIN = VIH or VIL VCC = Min IOL = 2 mA 0.4 V IOL = 100 µA 0.2 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) 2.0 5.5 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current V IN = VCC, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –10 µA IOZH Off-State Output Leakage Current HIGH V OUT = VCC, VCC = Max, VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW V OUT = VCC, VCC = Max, VIN = VIH or VIL (Note 2) -10 µA ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 3) -15 -75 mA ICC Supply Current Outputs Open (IOUT = 0 mA) VCC = Max, f = 15 MHz (Note 4) f = 0 MHz 30 µA f = 15 MHz 45 mA

14 PALLV16V8Z-20 (Ind)

Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES 1 Notes: 1. See “Switching Test Circuit” for test conditions. 2. This parameter is tested in Standby Mode. When the device is not in Standby Mode, the t PD will typically be about 2 ns faster. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. t CF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. Parameter Symbol Parameter Description Test Condition Typ Unit CIN Input Capacitance V IN = 2.0 V VCC = 5.0 V, TA = 25°C, f = 1 MHz 5p F COUT Output Capacitance V OUT = 2.0 V 8 pF Parameter Symbol Parameter Description -20 UnitMin Max tPD Input or Feedback to Combinatorial Output (Note 2) 20 ns tS Setup Time from Input or Feedback to Clock 15 ns tH Hold Time 0 ns tCO Clock to Output 10 ns tWL Clock Width LOW 8 ns tWH HIGH 8 ns fMAX Maximum Frequency (Notes 3 and 4) External Feedback 1/(t S + tCO) 40 MHz Internal Feedback (fCNT) 1/(t S + tCF) 50 MHz No Feedback 1/(t S + tH) 66.7 MHz tPZX OE to Output Enable 20 ns tPXZ OE to Output Disable 20 ns tEA Input to Output Enable Using Product Term Control 20 ns tER Input to Output Disable Using Product Term Control 20 ns

PALLV16V8-10 and PALLV16V8Z-20 Families 15 SWITCHING WAVEFORMS Notes: 1. V T = 1.5 V for input signals and VCC/2 for output signals. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns to 5 ns typical. tPD Input or Feedback Combinatorial Output VT VTO 17713D-7 a. Combinatorial output VT VTO Input Output d. Input to output disable/enable 17713D-10 tER tEA VTInput or Feedback Registered Output b. Registered output 17713D-8 tS tCO VTO tH VT Clock tWH Clock c. Clock width VT tWL 17713D-9 VT VTO OE Output e. OE to output disable/enable 17713D-11 tPZXtPXZ VOH - 0.5V VOL + 0.5V VOH - 0.5V VOL + 0.5V

16 PALLV16V8-10 and PALLV16V8Z-20 Families

Specification S 1 S2 CL R1 R2 Measured Output Value tPD, tCO Closed Closed 30 pF 1.6K 1.6K VCC/2 tPZX, tEA Z → H: Open Z → L: Closed Z → H: Closed Z → L: Open VCC/2 tPXZ, tER H → Z: Open L → Z: Closed H → Z: Closed L → Z: Open 5 pF H → Z: VOH – 0.5 V L → Z: VOL + 0.5 V KS000010-PAL Must be Steady May Change from H to L May Change from L to H Does Not Apply Don’t Care, Any Change Permitted Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is High- Impedance “Off” State WAVEFORM INPUTS OUTPUTS 17713D-12 C L Output R 1 R 2 Test Point VCC

PALLV16V8-10 and PALLV16V8Z-20 Families 17 TYPICAL ICC CHARACTERISTICS VCC = 3.3 V, TA = 25°C 150 125 100 01 0 2 0 3 0 4 0 5 0 Frequency (MHz) I CC (mA) 17713D-13 The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching. By utilizing 50% of the device, a midpoint is defined for I CC . From this midpoint, a designer may scale the ICC graphs up or down to estimate the ICC requirements for a particular design. ICC vs. Frequency PALLV16V8-10 PALLV16V8Z-20

18 PALLV16V8-10 and PALLV16V8Z-20 Families

The PALLV16V8 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, devices can be erased and reprogrammed—a feature which allows 100% testing at the factory. ROBUSTNESS FEATURES The PALLV16V8 has some unique features that make it extremely robust, especially when operating in high-speed design environments. Pull-up resistors on inputs and I/O pins cause unconnected pins to default to a known state. Input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special noise filter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns. INPUT/OUTPUT EQUIVALENT SCHEMATICS Symbol Parameter Test Conditions Value Unit tDR Min Pattern Data Retention Time Max Storage Temperature 10 Years Max Operating Temperature 20 Years N Max Reprogramming Cycles Normal Programming Conditions 100 Cycles 17713D-15 Typical Input Typical Output Preload Circuitry ESD Protection and Clamping Feedback Input VCC VCC > 50 kΩ VCC Programming Voltage Detection Positive Overshoot Filter Programming Circuitry Provides ESD Protection and Clamping Programming Pins only > 50 kΩ VCC 5-V Protection 17713D-14

simplifying state machine initialization. A timing diagram and parameter table are shown below. N The VCC rise must be monotonic. and feedback setup times are met. Figure 3. Power-Up Reset Waveform

20 PALLV16V8-10 and PALLV16V8Z-20 Families

TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heat- flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location ion the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the pack age. Furthermore, θjc tests on packages are performed in a constant temperature. Therefore, the measurements can only be used in a similar environment. Parameter Symbol Parameter Description Typ UnitPDIP PLCC θjc Thermal impedance, junction to case 20 19 °C/W θja Thermal impedance, junction to ambient 65 57 °C/W θjma Thermal impedance, junction to ambient with air flow 200 lfpm air 58 41 °C/W 400 lfpm air 51 37 °C/W 600 lfpm air 47 35 °C/W 800 lfpm air 44 33 °C/W

PALLV16V8-10 and PALLV16V8Z-20 Families 21 CONNECTION DIAGRAMS (TOP VIEW) 1 20 19 9 10 11 12 13 I I/O6 I/O5 I/O4 I/O3 I/O2 OE/I9 I/O0 I/O1 GND CLK/I0 VCC I/O7 VCCCLK/I I I I I I I I I GND I/O I/O I/O I/O I/O I/O I/O I/O OE/I 17713D-2 PLCCDIP/SOIC Note: Pin 1 is marked for orientation. 17713D-3 PIN DESIGNATIONS CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V CC = Supply Voltage

22 PALLV16V8-10 and PALLV16V8Z-20 Families

ORDERING INFORMATION

Commercial and Industrial Products Vantis programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: SPEED –10 = 10 ns t PD –20 = 20 ns t PD Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confirm availability of specific valid combinations and to check on newly released NUMBER OF ARRAY INPUTS OPERATING CONDITIONS C = Commercial (0 °C to +75°C) I = Industrial (–40 °C to 85°C) NUMBER OF OUTPUTS OUTPUT TYPE V = Versatile TECHNOLOGY LV = Low-Voltage FAMILY TYPE PAL = Programmable Array Logic PACKAGE TYPE P = 20-Pin Plastic DIP (PD 020) J = 20-Pin Plastic Leaded Chip Carrier (PL 020) S = 20-Pin Plastic Gull-Wing Small Outline Package (SO 020) Valid Combinations PALLV16V8-10 PC, JC, SC PALLV16V8Z-20 PI, JI Valid Combinations PAL LV 16 V 8 Z P C Z = Zero Power (30 µA ICC Standby) -10