PAC80

PAC80 LATTICE | Alldatasheet

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In-System Programmable Analog Circuit pac80_03 1 TM Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Tel. (503) 268-8000; 1-888-477-7537; FAX (503) 268-8037; http://www.latticesemi.com Functional Block DiagramFeatures

• IN-SYSTEM PROGRAMMABLE (ISP™) ANALOG — Instrument Amplifier Gain Stage — Precision Active Filtering (50kHz to 500kHz) — Continuous-Time Fifth Order Low Pass Topology — Dual, A/B Configuration Memory — Non-Volatile E 2CMOS Cells — IEEE 1149.1 JTAG Serial Port Programming
• UNIQUE FLEXIBILITY AND PERFORMANCE — Programmable Gain Range (0dB to 20dB) — Implements Multiple Filter Types: Elliptical, Chebyshev, Bessel, Butterworth, Linear Phase, Gaussian and Legendre — Low Distortion (THD < -74dB max @ 100kHz) — Auto-Calibrated Input Offset Voltage
• TRUE DIFFERENTIAL I/O — High CMR (58dB) Instrument Amplifier Input — 2.5V Common Mode Reference on Chip — Rail-to-Rail Voltage Outputs
• SINGLE SUPPLY 5V OPERATION — Power Dissipation of 165mW — 16-Pin Plastic SOIC, PDIP Packages
• APPLICATIONS INCLUDE INTEGRATED — Single +5V Supply Signal Conditioning — Programmable Filters With Fully Differential I/O — Analog Front Ends, 12-Bit Data Acq. Systems — DSP System Front End Signal Conditioning — High-Performance Reconstruction Filters Typical Application Diagram

Description

The ispPAC80 is a member of the Lattice family of In-System Programmable analog circuits, digitally configured via non- volatile E 2CMOS ® technology. Analog building blocks, called PACell™(s), replace traditional analog components such as opamps, eliminating the need for external resistors and capacitors. With no requirement for external configuration components, ispPAC80 expedites the design process, simplifying prototype circuit implementation and change, while providing high-performance integrated func- tionality. With all components on chip, there is no longer a concern of performance degradation due to component mis- match or other external factors. The ispPAC80 provides reliable and repeatable performance, every time. Designers configure the ispPAC80 and verify its performance using PAC-Designer™, an easy to use, Microsoft Windows compatible program. A filter configuration database is provided whereby thousands of different configurations can be realized. No special understanding of filter synthesis is required beyond that of general specifications such as corner frequency and stopband attenuation, etc. The software lists the possible choices that meet the designer’s specifications which can then be loaded directly into either of two device (A/B) configurations from the lookup table. Device program- ming is supported using PC parallel port I/O operations. The ispPAC80 is configured through its IEEE Standard 1149.1 compliant serial port. The flexible In-System Programming capability enables programming, verification and reconfig- uration, if desired, directly on the printed circuit board. Vin VREFoutA/B & Gain SPI Control Reference Ain- Ain+ 12-Bit Differential DSP Input ADC ispPAC80 OUT+ OUT – IN+ IN– VS VREFOUT TEST TEST E2CMOS Cfg A Ref & Auto-Cal ISP Control E2CMOS Cfg B IA OA 5th Order LPF TDI TDO TCK TMS GND CAL ENSPI CS ispPAC80

Symbol Parameter Condition Min. Typ. Max. Units Analog Input VIN± (1) Input Voltage Range Applied to Either V IN+ or VIN- 14 V VIN-DIFF Differential Input Voltage Swing (2) 2| V IN+ – VIN-| 6V p-p VOS (2) Differential Offset Voltage (Input Referred) G = 10 30 200 µV G = 1 0.3 2 mV ∆VOS /∆ T Differential Offset Voltage Drift -40 to +85 °C4 0 µV/°C R IN Input Resistance 10 9 Ω C IN Input Capacitance 2 pF IB Input Bias Current at DC 1 pA eN Input Noise Voltage Density At 10kHz, Referred to Input, G = 10 80 nV/ √Hz Analog Output VOUT ± Output Voltage Range Present at Either V OUT+ or VOUT – 0.1 4.9 V VOUT-DIFF Differential Output Voltage Swing (2) 2| V OUT+ – VOUT – | 9.6 V p-p IOUT ± Output Current Source/Sink 10 mA VCM Common Mode Output Voltage (V OUT+ + VOUT- )/2 2.495 2.5 2.505 V Static Performance G Programmable Gain Range Input Gain Amplifier (1, 2, 5, 10) 0 20 dB Gain Error R L = 300Ω Differential 0.5 2.5 % ∆ G /∆T Gain Drift -40 to +85 °C 20 ppm/ °C PSR Power Supply Rejection Differential at 1kHz 80 dB Single-ended at 1kHz 70 dB Common Mode Reference Output (VREFOUT ) VREF OUT Reference Output Voltage Range Nominally 2.500V -0.2 0.2 % Reference Output Voltage Drift -40 to +85 °C 50 ppm/ °C IREFOUT Reference Output Current (VREF OUT = ±1%) Source 50 µA (VREF OUT = ±1%) Sink 350 µA Reference Output Noise Voltage 10MHz Bandwidth 40 µVRMS Reference Power Supply Rejection 1kHz 80 dB Programming Erase/Reprogram Cycles 10K 1M cycles Digital I/O VIL Input Low Voltage 0 0.8 V VIH Input High Voltage 2 V S V IIL, IIH Input Leakage Current 0V ≤TCK,ENSPI,CAL Input ≤VS -10/+40 µA 0V≤TDI,TMS,CSb Inputs ≤VS -70/+10 µA VOL Output Low Voltage (TDO) I OL = 4.0mA 0.5 V VOH Output High Voltage (TDO) I OH = -1.0mA 2.4 V TA = 25°C; VS = 5.0V; 1V < VOUT < 4V; Gain = 1; Output load = 200pF, 1MΩ . Filter configuration = CC051042, FP = 50kHz; Auto-Cal initiated immediately prior. (Unless otherwise specified).

Symbol Parameter Condition Min. Typ. Max. Units Dynamic Performance (4) SNR Signal to Noise (G=1 to 10) 0.1Hz to 500kHz, F C = 500kHz 83 dB THD Total Harmonic Distortion (Differential) F IN = 10kHz, VIN = 6Vp-p -90 -74 dB Single-Ended F IN = 10kHz, VIN = 6Vp-p -80 dB Differential (FP = 500kHz) F IN = 100kHz, VIN = 6Vp-p -90 -74 dB Single-Ended (FP = 500kHz) F IN = 100kHz, VIN = 6Vp-p -74 dB CMR Common Mode Rejection (V IN = 1V to 4V) 10kHz 60 50 dB Note: VIN+ and VIN- connected together 100kHz, F C = 500kHz 60 dB Filter Characteristics (4) FC Corner Frequency Programming Range Elliptic Filter Families 50 500 kHz |FC | Absolute Corner Frequency Accuracy Deviation From Calculated -3dB point FC = 50, 200 or 500kHZ 0.6 3 % ∆ FC Maximum Delta Between Corner 50kHz to 500kHz 3.7 % Frequencies ∆FC /∆T Corner Frequency Delta vs. Temperature F C = 50kHz 0.03 %/ °C FC = 500kHz 0.05 ∆FC /∆V Corner Frequency Delta vs. Supply Voltage F C = 50kHz 0.09 %/V Elliptic Filter Response (5) Passband Ripple F C = 50kHz 0.1 dB FC = 500kHz 0.5 dB Power Supplies VS Operating Supply Voltage 4.75 5 5.25 V IS Supply Current V S = 5.0V 33 40 mA PD Power Dissipation V S = 5.0V 210 mW Temperature Range Operation -40 85 °C Storage -65 150 °C Notes: (1) A wider input range of 0.7V to 4.3V is typical, but not guaranteed. Inputs larger than this will be clipped. Input signals are also subject to common-mode voltage limitations. Refer to the table of conditions in this datasheet. (2) Refer to theory of operation section later in this datasheet for explanation of differential voltage swing computation. (3) To insure full spec performance an additional auto-calibration should be performed after initial turn-on and the device reaches thermal stability. (4) Although many hundreds of thousands of filter configurations are available using ispPAC80, not every type will have corner frequencies available from exactly 50kHz to 500kHz, depending on the tables available from within PAC- Designer filter design tools. The general specifications given under this heading are realized using the Elliptic filter types. (5) A Cauer elliptic filter of type CC051042 (see datasheet text) is used to guarantee these specific filter accuracy specifications. It is assumed that all other configurations available in PAC-Designer will exhibit equivalent performance according to the applicability of the individual filter type. Necessary limitations will apply, however, when specifications do not directly apply. See the data sheet text, application notes and guides in PAC-Designer for specific filter type considerations.

Ambient Temperature with Power Applied ... -55 to 125°C Note: Stresses above those listed may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sec- tions of this specification is not implied. ispPAC80 Ordering Information Absolute Maximum Ratings Package Options Part Number Description ispPAC80-01PI 16-Pin PDIP ispPAC80-01SI 16-Pin SOIC PackageOrdering Number ispPAC 80 Device Family Device Number Performance Grade Package Grade 01 = Standard P = PDIP , S = SOIC I = Industrial Temperature ispPAC 80 – XX X X ispPAC 80 16-pin PDIP 16-pin SOIC

Symbol Parameter Condition Min. Typ. Max. Units Dynamic Performance tckmin Minimum Clock Period 200 ns tckh TCK High Time 50 ns tckl TCK Low Time 50 ns tmss TMS Setup Time 15 ns tmsh TMS Hold Time 10 ns tdis TDI Setup Time 15 ns tdih TDI Hold Time 10 ns tdozx TDO Float to Valid Delay 60 ns tdov TDO Valid Delay 60 ns tdoxz TDO Valid to Float Delay 60 ns tpwp Time for a programming operation Executed in Run-Test/Idle 80 100 ms tpwe Time for an erase operation Executed in Run-Test/Idle 80 100 ms tpwcal1 Time for auto-cal operation on power-up Automatically executed at power-up 250 ms tcalmin Minimum auto-cal pulse width 40 ns tpwcal2 Time for user initiated auto-cal operation Executed on rising edge of CAL 100 ms Timing Specifications (JTAG Interface Mode) TA = 25°C; VS = +5.0V (Unless otherwise specified) tckmintckh tckl tmss tdis tmsh tdih tdozx tdov tdoxz TCK TMS TDI TDO tmss tmss TCK TMS tpwp, tpwe *(PRGUSR/UBE executed in Run-Test/Idle state) CAL (Note: CAL internally initiated at device turn-on.) VOUT = 0VDIFF VOUT tpwcal1, tpwcal2 tcalmin *Note: During device JTAG programming, analog output response will deviate from expected behavior. This is because all configuration information is erased and then re-written as part of a normal programming cycle, momentarily changing device filter and gain parameters. Behavior will deviate from that expected during both of these steps since the analog outputs are not clamped during a programming cycle. During erase, a drop in the filter corner frequency and an automatic change to the 10X gain setting can be expected (80ms minimum by specification) and will continue until bits go to there final state after a JTAG write command is issued (less than 2ms later, though the write cycle must still be maintained for a full 80ms to achieve specified data retention).

Symbol Parameter Condition Min. Typ. Max. Units Dynamic Performance tckmin Minimum Clock Period 200 ns tckh TCK High Time 100 ns tckl TCK Low Time 100 ns tcss CS Setup Time 20 ns tcsminhi Minimum CS Pulse Widths 40 ns tdis TDI Setup Time 15 ns tdih TDI Hold Time 10 ns tdozx TDO Float to Valid Delay 60 ns tdov TDO Valid Delay 60 ns tdoxz TDO Valid to Float Delay 60 ns Timing Specifications (SPI Interface Mode) TA = 25°C; VS = +5.0V (Unless otherwise specified) tckmin tcsminhi tckltckh tcss tdis tdih tdozx hi-z hi-z tdov tdoxz TCK CS TDI TDO

Pin(s) Symbol Name Description 1 TMS Test Mode Select Serial interface logic mode select pin (input). JTAG interface mode only. 2 TCK Test Clock Serial interface logic clock pin (input). JTAG interface mode only. 3 TDI Test Data In Serial interface logic pin (input) for both JTAG and SPI operation modes. Input data valid on rising edge of TCK (JTAG), or on rising edge of CS (SPI). 4 TDO Test Data Out Serial interface logic pin (output) for both JTAG and SPI operation modes. Input data valid on falling edge of TCK (JTAG), or on rising edge of CS (SPI). 5 CS Chip Select Chip select logic input pin. SPI data latch. 6 CAL Auto-Calibrate Digital pin (input). Commands an auto-calibration sequence on a rising edge. 7 ENSPI Enable SPI Mode Enable SPI logic input pin. When high, causes serial port to run in SPI mode. 8 GND Ground Ground pin. Should normally be connected to the analog ground plane. 9 VREFout Common-Mode Common-mode voltage reference output pin (+2.5V nominal). Must be Reference bypassed to GND with a 1 µF capacitor. 10, 11 IN Inputs (+ or -) Differential input pins, using two pins (e.g., IN+ and IN-). Plus or minus components of VIN, where differential VIN = VIN+ - VIN-. 12, 15 TEST Test Pin Test pin. Connect to GND for proper circuit operation. 13, 14 OUT Outputs (+ or -) Differential output pins, using two pins (e.g., OUT+ and OUT-). Complementary with respect to VREFOUT . Differential VOUT = VOUT+ - VOUT- . 16 VS Supply Voltage Analog supply voltage pin (5V nominal). Should be bypassed to GND with 1 µF and .01µF capacitors. Pin Descriptions Connection Notes 1. All inputs and outputs are labeled with plus (+) and minus (-) signs. Polarity is labeled for reference and can be selected externally by reversing pin connections. 2. All analog output pins are “hard-wired” to internal output devices and should be left open if not used. VOUT+ and VOUT- should not be tied together as unnecessary power will be dissipated. 3. When the signal input is single-ended, the other half of the unused differential input must be connected to a DC common-mode reference (usually VREFOUT , 2.5V).

Percentage of Devices (%) Offset Tempco (µV/¡C)

3 Wafer Lots

-40¡C to +85¡C -100 -50 0 50 100 -80 dB -40 dB 0 dB 10kHz 100kHz 1MHz Stopband attenuation variation over process < 0.9dB Elliptical filter cc051042 Passband ripple variation over process < 0.02dB Typical Performance Characteristics THD vs. Frequency VOS Tempco Filter Variation (3 Sigma) 50 kHz Corner Freq. Error 200 kHz Corner Freq. Error 500 kHz Corner Freq. Error Noise Voltage (nV Hz)√ 1 10 100 1k 10k 100k 1M Frequency (Hz) 100 10K G = 1 G = 10 (Referred to Input) 10 100 1k 10k 100k 1M Frequency (Hz) Common Mode Rejection (dB) Elliptical filter cc051042 Fc = 50kHz Elliptical filter cc051042 Fc = 500kHz 100 1k 10k 100k 1M Frequency (Hz) Power Supply Rejection (dB) 1k 10k 100k 1M Frequency (Hz) -95 -100 -90 -85 -80 -75 -70Total Harmonic Distortion (dB) G = 10 G = 1 Elliptical filter cc051042 Fc = 500kHz Input Noise Spectrum CMR vs. Frequency PSR vs. Frequency

200 Units

Percentage of Devices (%) Corner Frequency Error (%) Percentage of Devices (%) Corner Frequency Error (%) 5 10 Percentage of Devices (%) Corner Frequency Error (%)

circuits of ispPAC80 are operating correctly. Figure 1. Simplified ispPAC80 Filter Core Schematic

Table 1. SPI Control Bit Sequence Table 2. Gain Bit Settings overridden from within PAC-Designer from the edit symbol dialog. command. Part of user configuration string A only. been determined initially in the design environment using PAC-Designer. SPI control. Refer to Table 2 for bit setting specifics. JTAG user (USRA) bulk erase commands and reprogramming the device. Table 3. JTAG User Configuration Bits device in the SPI interface mode (ENSPI pin = logic high). 2 bits available is listed in Table 3.

please refer to application note AN6019. have a DC bias equal to the DC level of the other input. minimum allowable load impedance. signal is true differential and referenced to 2.5V. Table 4. Input Common-Mode Voltage Range *Peak input voltage for guaranteed performance at a given gain setting.

Figure 2. Initial PAC-Designer Schematic Design Entry Screen that covers all aspects of PAC-Designer operation. well as the PAC-Designer Getting Started Manual.

sponse stored in configuration A and B respectively. changes so performance comparisons can be made. Figure 3. PAC-Designer Simulation Plot Screen

Figure 4. Configuring the ispPAC80 “In-System” from a PC Parallel Port The ispPAC80 is an in-system programmable device. interface section of this data sheet. as ID codes, revision numbers or inventory control data. JEDEC file is created using the PAC-Designer software. are provided to speed debugging of the circuit.

the Run-Test/Idle state via the Exit2 and Update states. Figure 6. Test Access Port (TAP) Contoller State Diagram instructions are executed in the Update state. function of three required and six optional instructions. represents the signal present at TMS at the time of a rising edge at TCK.

all ones by the IEEE 1149.1 standard. instruction is defined by Lattice as shown in Table 5. the 1149.1 standard to be all zeros. Table 5. ispPAC80 TAP Instructions Figure 7. Identification Code (IDCODE) 32-Bit instruction is shown in Table 5. External test. Default to BYPASS. Address user data register (A or B). Verify User A data register. Verify User B data register. Program User A data register. Program User B data register. Enable calibration sequence. Read identification data register. Sample/preload. Default to BYPASS.

IEEE Standard 1149.1 Interface (Continued) retention is given in the TAP signal specifications table. The user must ensure that the recommended program- ming times are observed. The bit code for these instructions is shown in Table 5. VERA and VERB (verify user A or B) are the next Lattice instructions and cause the current A or B configurations of the ispPAC80 to be loaded into the user register. This operation doesn’t interrupt operation of the device. The current configuration of either the A or B configuration memory can then be shifted out of the user register immediately after an ADDUSR instruction is executed. NOTE: The verification of memory configuration “A” is possible only when the A/B bit is set to a logic 0. This must be taken into account if verify will be performed at a later time on parts with unknown configurations (refer to the Lattice application note covering the required algorithms necessary for complete JTAG device programming con- trol of the ispPAC80, specific bit assignments, word lengths, etc.). If the A/B bit has been set to a logic 1, it will not be possible to do a VERA command properly. The bit code for this instruction is shown in Table 5. ENCAL (enable calibration) is a Lattice instruction that enables the start of an auto-calibration sequence. This operation causes all outputs of the device to go to 2.5V until the calibration sequence is completed (see timing specifications). As with the programming instructions above, calibration does not begin until entry of the Run- Test/Idle state. The completion of the calibration is not dependent, however, on any further TAP control. This means the state of the TAP can be returned immediately to the Test-Logic-Reset state. The only consideration would be to not clock the TAP during critical analog operations. The first several milliseconds of the calibra- tion routine are consumed waiting for configurations to settle, though, leaving more than enough time to clock the TAP back to the Test-Logic-Reset state. The bit code for this instruction is shown in Table 5. The last Lattice instructions are ABE and BBE (user A or B bulk erase). Operation of the device is interrupted during an ABE or BBE, during which all inputs are disconnected and all outputs driven to VREFOUT (2.5V). To economize internal circuitry, programming can only be selectively done in one direction (from zeroes to ones). The ABE and BBE are used to return all user bits to a zero state at the same time. An ABE or BBE usually proceeds a PRGA or PRGB operation, otherwise one to zero changes would not be implemented. It can also be used to erase all configuration information from a device and is the default condition of parts shipped from the factory. The same programming time constraints apply to ABE and BBE as for PRGA and PRGB. The bit code for this instruction is shown in Table 5. The ADDUSR, BYPASS, EXTEST, IDCODE and SAMPLE/PRELOAD instructions are all executed in the Update-IR state. Other instructions: PRGUSR, VERUSR and UBE are executed upon entry of the Run-Test/Idle state. It is recommended that when all serial interface opera- tions are completed, the TAP controller be reset and left in the Test-Logic-Reset state (the power-up default) and the TCK and TMS inputs idled. This will insure the best analog performance possible by minimizing the effects of digital logic “feed-through.”

Dimensions in Inches MIN./MAX. (Dimensions in millimeters, shown in parenthesis, are for reference only) .008 / .012 (.20 / .31) 0-15 .195 (4.95) MAX .015 /.022 (.38 / .56) .055 /.065 (1.40 / 1.65) .745 / .755 (18.92 / 19.18) .300 / .325 (6.10 / 6.60) .100 (2.54) BSC .125 / .135 (3.17 / 3.43) .015 (.38) MIN 8 .024 (.61) .040 (1.02) .292 (7.42) .299 (7.59) .400 (10.16) .410 (10.41) .014 (.35) .402 (10.21) .412 (10.46) .0091 (.23) .0125 (.32) .097 (2.46) .104 (2.64) .0050 (.127) .0115 (.292) 16-Pin Plastic SOIC Dimensions in Inches MIN./MAX. (Dimensions in millimeters, shown in parenthesis, are for reference only)