PACPOWR605-P-EVN LATTICE | Alldatasheet
Document overview
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Technical content
The ProcessorPM™ Development Kit is a versatile, ready- to-use hardware platform for evaluating and designing with ProcessorPM power management devices. The kit is based on a 2.5” x 2” evaluation board that features the ProcessorPM- POWR605 device in a lead-free 24-pin QFN package, a Power Manager II POWR6AT6, evaluation circuits that emulate a power supply bus and processor interface, and an expansion header. Processor Support Made Easy To help you get started quickly , the kit includes a pre- configured processor support demonstration design that will support hundreds of microprocessor, DSP , ASSP , or ASIC power management scenarios. The demo integrates three key support functions for a processor: voltage supervisor, watchdog timer (WDT), and reset generator. The board is controlled with switches and push buttons. And a slide potentiometer emulates brown-out conditions on a 2.5V supply rail. A pin header provides access to voltage monitor inputs and digital I/Os of the ProcessorPM and the I2C and power supply margin/trim I/Os of the POWR6AT6. You may extend or modify the pre-configured demo using PAC-Designer® and ispVM™ software. Processor Support Demo The kit includes a processor support demo which shows the versatility of the pre-configured ProcessorPM design by allowing you to modify WDT expiration period and reset pulse enable/disable with DIP switch settings. You can then emulate supply rail conditions, manual reset inputs, and the processor interface with push-buttons and a slide potentiometer. The board indicates reset, interrupt, and IO states with LEDs. If supply rails go out-of-tolerance, a manual reset occurs, or if the WDT period expires, the ProcessorPM will assert processor control signals to indicate reset or WDT interrupt. ProcessorPM Eval Board Block Diagram Reset CPU WDT Int. Processor, DSP, ASSP, or ASIC Watchdog Timer Reset Generator Voltage Supervisor ProcessorPM WDT Trigger Reset Manual ProcessorPM Development Kit Versatile & Ready-to-Use Platform for Processor Power Management Key Features Pre-Configured Processor Support Demo ProcessorPM-POWR605 Device Power Manager II POWR6AT6 Device 3.3V , 2.5V , and 1.8V Supply Rails LEDs Slide Potentiometer 2x14 Expansion Header USB Mini Jack Socket (Program/Power) 2 Push-buttons 4-Bit DIP Switch JTAG and I2C Header Landings USB Connector Cable QuickSTART Guide Marked for CE, China RoHS Environmental-Friendly Use Period (EFUP) and Waste Electrical and Elec- tronic Equipment (WEEE) Directives
Ordering Information
Product Description Ordering Part # ProcessorPM Development Kit ProcessorPM Development Kit with ispPAC- POWR605-01SN24I device, USB cable, QuickSTART Guide, and demonstration design PACPOWR605-P-EVN
Voltage Supervisor Integration Voltage supervisors are a common requirement for processors to ensure reliable operation and ensure safe shut-down if power is interrupted. The ProcessorPM evaluation board provides access to all six programmable threshold monitors of the ProcessorPM device. Three inputs monitor on-board 3.3V , 2.5V , and 1.8V sup- ply rails. Switch and potentiometer circuits allow you to emulate both failure and brown-out conditions. Three other voltage monitor inputs are available at the expansion header. The board provides landings for voltage divider circuits that allow you to monitor other supply rail voltages. If any monitor drops below an analog trip point the ProcessorPM asserts the CPU Reset output indicated by a red LED. You can modify the trip points and glitch filter enable for individual voltage monitors (VMONs) through PAC-Designer software. Watchdog Timer Integration Watchdog timer ICs ensure your processor system can recover from an indeterminate state. The pre-configured ProcessorPM demo design includes selectable timer intervals for 500ms, 2sec, 10sec, or 1min. Interval period is decoded from digital inputs se- lected from DIP switch settings. You can interact with the WDT by activating the WDT trigger input periodically using a push- button. ProcessorPM asserts WDT interrupt output, indicated by an amber LED, if your processor neglects to regularly service the watchdog. You can modify the clock and timer function of the ProcessorPM through PAC-Designer software. Reset Generator Integration Processor reset ICs help ensure stable operation of a processor by asserting reset whenever supplies are out-of-tolerance and then continue to assert until the system starts-up. The processor sup- port demo asserts reset output upon manual reset of the board or if a supply rail fault occurs. You may enable the reset pulse stretch feature of the ProcessorPM from a DIP switch input. The pre-configured design adds 200ms to the pulse which you can visualize with a red LED on the board. The pulse period of the pre-configured demo design employs a ProcessorPM timer/coun- ter block which you can modify through PAC-Designer software. Power-Suppy Monitoring, Margin, & Trim Voltages can be measured using the POWR6AT6 device on the ProcessorPM board. The POWR6AT6 integrates ADC/DACs and I2C interface for power supply trimming and margining. The ProcessorPM board can be used to demonstrate trimming and margining of up to 3 power supplies. Copyright © 2009 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), ispVM, PAC-Designer, and ProcessorPM are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. September 2009 Order #: I0202A Applications Support 1-800-LATTICE (528-8423) (503) 268-8001 techsupport@latticesemi.com www.latticesemi.com Additional Information Documentation including PAC-Designer project source, sub- system descriptions, and schematics are available at: www.latticesemi.com/processorpm-kit PAC-Designer Design Tools FREE ProcessorPM leverages Lattice in-system programmability (ISP™) so you can adapt the ProcessorPM Development Kit to a wide range of power management scenarios. You can modify or extend the pre-configured processor support demo design with software design tools: PAC-Designer and ispVM. PAC-Designer is a graphical, dialog-driven interface that makes it easy for engineers who are specialists in digital or analog design to easily compile custom designs for ProcessorPM. The downloadable PAC-Designer development tools offer a com- prehensive design environment for the ProcessorPM and other Power Manager II power management devices. PAC-Designer includes design entry , simulation, compiler, and a programming interface to ispVM. Download PAC-Designer software at: www.latticesemi.com/products/designsoftware/pacdesigner Download ispVM™ programming software at: www.latticesemi.com/products/designsoftware/ispvmsystem