GAL16V8A-7LPI

GAL16V8A LATTICE | Alldatasheet

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LATTICE SEMICONDUCTOR 4?7E D MM 5346949 000193e 2 MBLAT oon . aH | attice GAL16V8B oun iin 7-46-19-07 GAL16V8A seeeee High Performance E?CMOS PLD * HIGH PERFORMANCE E*CMOS* TECHNOLOGY 1 vee — 7.5 ns Maximum Propagation Delay ox 4 —Fmax = 100 MHz a 20 — 51s Maximum from Clock input to Data Output TS awa Ea © — TTL Compatible 24 mA Outputs ee io — UltraMOS* Advanced CMOS Technology aie aS poi * 50% to 75% REDUCTION IN POWER FROM BIPOLAR feueeat ea a ‘e — 75mA Typ lec on Low Power Device Po ioe — 45mA Typ lec on Quarter Power Device 8 ee ener + ACTIVE PULL-UPS ON ALL PINS (GAL16V8B) pS asriseceets ef Ry ” — Reconfigurable Logic CLs ins — Reprogrammable Cells oie Pah — 100% Tested/Guaranteed 100% Yields eer el a i — High Speed Electrical Erasure (<100ms) ss EEO be — 20 Year Data Retention far s oe [ = = + EIGHT OUTPUT LOGIC MACROCELLS eee 3 a Mie 15 — Maximum Flexibility for Complex Logic Designs see OZ Sh, — Programmable Output Polarity peg ts ro | — Also Emulates 20-pin PAL® Devices with Full Func- pete pune EA, “4 * PRELOAD AND POWER-ON RESET OF ALL REGISTERS ee eee By co | — 100% Functional Testability Hagen: Hie a is Mile 13 + APPLICATIONS INCLUDE: ° ois itstietistiae: Li — High Speed Graphics Processing ferateeenatett + ELECTRONIC SIGNATURE FOR IDENTIFICATION e The GAL16V8B, at 7.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically pip Erasable (E*) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times PLoc (<100ms) allow the devices to be reprogrammed quickly and vou [7 20 [I Vee fficienty. 11 eux Yee yoo g [ vora ‘The generic architecture provides maximum design flexibility by Zot iq b vara allowing the Output Logic Macrocell (OLMC) to be configured by 1) vor the user. An important subset of the many architecture con- q b vova figurations possible with the GAL16V8A/B are the PAL archi {} D) wore GAL bvoe tectures listed in the table of the macrocell description section. if GALIeV8VB fy. 'G 16V8AB H GAL16V8A/B devices are capable of emulating any of these PAL Top View q Di vor architectures with full function/fuse map/parametric compatibility. "(| peo od b vara Unique test circuitry and reprogrammable cells allow complete [| hwe 4 b vor ‘AG, DC, and functional testing during manufacture. Asa resutt, a LATTICE is able to guarantee 100% field programmability and 1 emo WBE vara vora iq D vero functionality of all GAL® products. LATTICE also guarantees 100 ono 10 a fer erase/rewrite cycles and data retention in excess of 20 years. ‘Copy ©1992 Late Somiconducter Corp. GAL. EXOMOS and UlaMOS ae reir ademas of Loe Sericonducer Corp. Ganer Aray Lag a radenark of Lace Semiconduo- terCor. Alban product names mentioned ae radars or repaired ademas Otho respective holders. The specications and rlomation eren ere abject 10 change wat toe Tal. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037 ot

LATTICE SEMICONDUCTOR 47E D MM 5386949 9001933 4 MBLAT oon . Lattice Specifications GAL16V8B Hit GAL16V8A GAL16V8A/B ORDERING INFORMATION T- 46-19 -0 7 ‘Commercial Grade Specifications Fes [Towa Teown [eA] Owner | is [7 A (CLC mine [we _[aatreveo-r.s _______[apiees rice 7 [one _onsevee-ruP [zone [15 —Jontseves-rous_fanteentce [ss __[eatevantsor aor [ss |eatieventsai ~~ aotvea ico] [is Jeatover tate =a Pasi [5 entreventscs [notaries [ss _[earevenasor sao Pinsic oP [ss _eattevenar——Yanieasrtce_— ee [oo [en ven asus Jaana tc Industrial Grade Specifications cA 70 [7 [0 _Jantieveeraum aot] [too [eatseves-toun ____[zioea rice 3 a [es __[GALteven roan [ateea pico] [#5 _Jeatteven asap [zn Pate >] [5 Jontvenzean ____[roteea rico [0 _[entsevenastr_fa Pn Pasio [0 Jeatevanascr fate rt} PART NUMBER DESCRIPTION YOOCOOONK = XXX XK GALI6VBA s Grade Blank = Commercial peed (ne) I= Industrial = Low Power Power Package P = Plastic DIP Q= Quarter Power J=PLCC aT} 2-2

LATTICE SEMICONDUCTOR 47E D MM 5386949 0001934 & MBLAT ase . #Lattice Specifications GAL16V8B SEEEEE GAL16V8A OUTPUT LOGIC MACROCELL (OLMC) T-¥6 19-0 The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is ac- PAL Architectures GALIeveNs complished by development software/hardware and is completely Emulated by GAL16V8A/B Global OLMC Mode transparent to the user. 16R8 Registered There are three global OLMC configuration modes possible: 46RS Registered simple, complex, and registered. Details of each of these 16R6 Rogistered modes are illustrated in the following pages. Two global bits, SYN jenee Revienored and ACO, control the mode configuration for all macrocelis. The tenes aad XOR bit of each macrocell controls the polarity ofthe output in any of the three modes, while the AC1 bit of each of the macrocells 16L8 ‘Complex controls the inpul/output configuration. These two global and 16 16H8 ‘Complex individual architecture bits define all possible configurations in a 166 Complex GAL16V8A,B. The information given on these architecture bits tous simple is only to give a better understanding of the device. Compiler 4208 Simple ‘software will transparently set these architecture bits from the pin 14u4 ‘Simple definitions, so the user should not need to directly manipulate 1612 Simple these architecture bits. we bred 14H4 Simple “The following isa lst of the PAL architectures that the GAL16VBA 46H2 Simple and GAL16V8B can emulate. It also shows the OLMC mode 10P8 ‘Simple under which the GAL16V8A/B emulates the PAL architecture. 12P6 Simple : 14P4 Simple 16P2 ‘Simple COMPILER SUPPORT FOR OLMC Software compilers support the three different global OLMC —_In registered mode pin 1 and pin 11 are permanently configured modes as different device types. These device types are listed as clock and output enable, respectively. These pins cannot be inthe table below. Most compilers have the ability to automati-. configured as dedicated inputs in the registered mode. cally select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device —_Incomplex mode pin 1 and pin 11 become dedicated inputs and forces the software to choose the registered mode. All combi- _use the feadback paths of pia 19 and pin 12 respectively. Because natorial outputs with OE controlled by the product term willforce _of this feedback path usage, pin 19 and pin 12 do not have the the software to choose the complex mode. The software will feedback option in this mode. choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types sted in simple mode all feedback paths of the output pins are routed in the table can be used to override the automatic device selection via the adjacent pins. In doing so, the two inner most pins ( pins by the software. For further details, refer to the compiler software 15 and 16) will not have the feedback option as these pins are manuals. always configured as dedicated combinatorial output. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. es [apeL Cd Piven | Pievec |S Pteveas | Ptova, [cum —s|Gievems | GtevemaA | teveas_— | Gteva_ [Logac | GALteve.R_ | GALieva.c7 | GaLieve.ca | GaLieva | [PLDesigner | Pievarn® | Pievec? | Pigvact | PteveA [Tango-pLo | GteveR_— | Giévec | Gteveas® | Giéve 1) Used with Configuration keyword. 2) Prior to Version 2.0 support, 3)_Supported on Version 1.20 or later.

LATTICE SEMICONDUCTOR 4?E D MM 5386949 0001935 & MBLAT ass . Lattice Specifications GAL16V8B iSeecs sesees GAL16V8A T-46719-0 PREGISTEREDODE CD Inthe Registered mode, macrocelis are configured as dedicated mode. Dedicated input or output functions can be implemented registered outputs or as VO functions. as subsets of the VO function. Architecture configurations available in this mode are similar to Registered outputs have eight product terms per output. /O's the common 16R8 and 16AP4 devices with various permutations __have seven product terms per output. of polarity, VO and register placement. The JEDEC fuse numbers, inching the User Electronic Signature ‘Al registered macrocelis share common clock and output enable (UES) fuses and the Product Term Disable (PTD) fuses, are control pins. Any macrocell can be configured as registered or shown on the logic diagram on the following page. VO. Up to eight registers or up to eight /O's are possible in this CLK yoo Registered Configuration for Regl ‘ a -SYN=0. Ete, «XR defines Actve Low 0 =) o-~ TXORA| defines Active High Oued. t+ ) >" Tbe KA} ——- AC 1=0 defines this output configuration. tt—) ,.2 L ap : - Pin 1 controls common CLK for the registered outputs. poze i - Pin 11 controls common OE for the registered outputs. rd i - Pin 1 & Pin 11 are permanently configured as CLK & dc eseeseeeuneenseeenseteseenseeeeeed OE. OF : i + XOR=0 defines Active Low Output. ; = XOR=1 defines Active High Output. XOA Hl + AC1=1 defines this output configuration. i i ~Fin 1 & Pin 11 are permanenty configured as CLK & Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 2-4

LATTICE SEMICONDUCTOR Y?E D MM 5386949 0001936 T MBLAT #Lattice Specifications GAL16V8B HE GAL16V8A 7-46 79-07 DIP & PLCC Package Pinouts oo 4 a a ro) 0 0010001181181 a = ETE “ i ~ i TT , iA ~ UTICA ~ AETCTET TTT H / iN i error (G+-UBER ELECTRONIC SIGNATURE FUSES io [Bye 7[eyee Be 1] 80 0} NOR we He 2-5

LATTICE SEMICONDUCTOR 47E D MM 5386949 0001937 1 MBLAT #Lattice Specifications GAL16V8B HEH GAL16V8A COMPLEX MODE TH 419-07 In the Complex mode, macrocells are configured as output only —_pability. Designs requiring eight I/O's can be implemented in the ‘or VO functions. Registered mode. Architecture configurations available in this mode are similar to All macrocelis have seven product terms per output. One product ‘the common 16L8 and 16P8 devices with programmable polarity ‘term is used for programmable output enable control. Pins 1 and in each macrocell. 11 are always available as data inputs into the AND array. Up to six /O's are possible in this mode. Dedicated inputs or ‘The JEDEC fuse numbers including the UES fuses and PTD fuses outputs can be implemented as subsets of the /O function. The are shown on the logic diagram on the following page. two outer most macrocells (pins 12 & 19) do not have input ca- Fa! Combinatorial YO Configuration for Complex Mode i H -SYN=1, t H + XOR=0 defines Active Low Output. $ XOR H -XOR=1 defines Active High Output. i } -ACI=1, + + ~ Pin 13 through Pin 18 are configured to this function. i nn Combinatorial Output Configuration for Complex Mode H H -SYN=1, x : + XOR=0 defines Active Low Output. =: H - XOR=1 defines Active High Output. H XOR -ACt=1. H H ~ Pin 12 and Pin 19 are configured to this function. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

LATTICE SEMICONDUCTOR 47E D MM 5386949 0001938 3 MBLAT Lattice Specifications GAL16V8B HHH GAL16V8A T-4o-19-07 DIP & PLCC Package Pinouts 1>—> = - Cafu f ee SS SSSHieeS So | HSCS OLMC 18 Poo am Ne SSS] OLMC 16 aan od sD = ou nnn ea = SE Hinriratitieiteritetsre ita Sol v amid Fro = a a PSHE HESS | SESE Se—e—! OC 4} Deu mm SH SHS | Pee eet (OLMC 13 pes oT SSSR Stree o| | SS Sete] OLMC 12 pon 1D =. oo an ‘G4-UBER ELECTRONIC SIGNATURE FUSES: ™ ii 27 see

LATTICE SEMICONDUCTOR 47E D MM 5386949 0001939 5 MBLAT Pe . : #Lattice Specifications GAL16V8B HEISE GAL16V8A -Y4b6 19-0 SIMPLE MODE Ji%6 J {nthe Simple mode, macrocells are configured as dedicated inputs Pins 1 and 11 are always available es data inputs into the AND or as dedicated, always active, combinatorial outputs. array. The center two macrocells (pins 15 & 16) cannot be used as input or VO pins, and are only available as dedicated outputs. Architecture configurations available in this mode are similar to the common 10L8 and 12P6 devices with many permutations of The JEDEC fuse numbers incxing the UES fuses and PTD fuses ‘generic output polarity or input choices. are shown on the logic diagram. ‘All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has programmable polarity. preterm combl with uration i Vee for Simple Mode i * + SYNe1. =4 i + XOR=0 defines Active Low Output. $ H = XOR=1 defines Active High Output. +: XOR i = AC 10 defines this configuration. i ; - All OLMC except pins 15 & 16 can be configured to H : this function, eee as Combinatorial Output Configuration for Simple Mode =>5 : = XOR=0 defines Active Low Output. r + + XOR=1 defines Active High Output. i ~AC1=0 defines this configuration. = XOR i = Pins 15 & 16 are permanently configured to this H E - XOR=0 defines Active Low Output. H i + XOR=1 defines Active High Output. : - +AC1=1 defines this configuration. Ieecaeecseeenesenntensertneeseeeenel ~All OLMC except pins 15 & 16 can be configured to this function. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

LATTICE SEMICONDUCTOR 4?7E D MM 5386949 0001940 1 MBLAT #Lattice Specifications GAL16V8B HE GAL16V8A DIP & PLCC Package Pinouts a ami - i —_| site tee ttemteiastitettt etter | morass [> Or CO TS ——" on O4-UGER ELECTRONIC SIGNATURE FUSES [2006 sor... 2118, 2110] syianne ane P

LATTICE SEMICONDUCTOR 47E D MM 5386949 0001541 3 MLAT #Lattice Specifications GAL16V8B HHH Commercial ABSOLUTE MAXIMUM RATINGS"? RECOMMENDED OPERATING COND. Supply Voltage Veg wssnesssninninnnnnnO.5t047V Commercial Devices: T-46>19 -07 Ambient Temperature with POWer AppIIOM eseernnsnnesenenieseon BS 10 125°C 1.Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC ELECTRICAL CHARACTERISTICS ‘Over Recommended Operating Conditions (Unless Otherwise Specified) [eer foe = | Vic [inputtowvotage | vaso] — | oe | v | [Vir [inputtignvotage | no | — [vccet | v | [tu inputorvotow Leakage Curent | ovsvnsvarwax) | — | — | -100 | a _| [tii | tnputorvovigh Leakage Curent | asvsvnsvec | — | — | 10 | ua | [Vou [oupttowvotage | xemax. vineveorvn | — | — | os | v | [von [ouput vorage [ owsmax vinzvuorm | 2a | — | — | v | [tor [towtwetoupucwen | ST | | | [tor [riprtnetcupncuen | | | | ae | ma | [Host [ouput ston Great Curent | Varnv Vor=oav Tease | 0 | — | -160 | ma | tcc Operating Power Supply Current Wi =0.5V Vin =3.0V fhooge = 25MHz 75 Outputs Open (no load) 1) The leakage current is due to the intemal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Guaranteed but not 100% tested. 3) Typical values are at Voc = 5V and Ta= 25 °C CAPACITANCE (T, = 25 C, f = 1.0 MHz) [_svwpo, [| Panamerer | waxmuwr | uns | Testconomons | a a “Guaranteed but not 100% tested. 2-10

LATTICE SEMICONDUCTOR 47E D MM 5386949 0002942 5S MMLAT #Lattice Specifications GAL16V8B HE Commercial T-40-19-07 Over Recommended Operating Conditions a lee el ee ee [to | 1 [ovcrwoumtoy sf 2 fs fe [i | oe | [ter | = | crocktoracack Dewy dT Tt | fs | oe | [tay | — | SeteTine ipucrFeetecttetcek =i? [= | |— | w | es |" [eerreamcieeres | | Extemal Feedback, 1/(tsu + tco) a a Intemal Feedback, 1/(tsu + tcf) Ce EEE No Feedback a [tw | — | crockPuseduatintow | |= fe fH [ine | (fk gamibieiapenntes __a_4_a ta ta | 2 | Cetoouputenabled fe Te 2 [10 [ne | [2 [wonorvotooupnoisabiod 2 |e | 2 | 10 | ne | [3 [Oetoupuvisaed tS [18 [10 [oe | 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with intemal feedback. Refer to max Descriptions section. 3) Retor to fmax Descriptions section. [InputPulseteveis | GNDto ov | sv [Input Rise andFallTimes | 3ns 10%-90% | at [Oupuicad | See Figure | 3-state levels are measured 0.5V from steady-state active OUTPUT level, TROERTEST eo) TEST PONT Output Load Conditions (see figure) ce [_Testconaiion [| ms | me | cx | me | Activetow | 200n | s00a | S0pF | | > Peesetie =o CLaetines a mo oR OTA CNC [ Activelow | 200n | 3000 [Spr |

LATTICE SEMICONDUCTOR 4?7E D MM 5386949 0001943 7 MBLAT om . og gt #Lattice Specifications GAL16V8A HEE Commercial HEH . ABSOLUTE MAXIMUM RATINGS” RECOMMENDED OPERATING COND. Supply voltage Vo -wnninnnenenmmntimnnnnO-5t04+7V Commercial Devices: T-$¢6~19-07 Ambient Temperature with Power Applied ..sscsssecsseesesseereeserneeee 55 10 125°C 1.Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC ELECTRICAL CHARACTERISTICS ‘Over Recommended Operating Conditions (Unless Otherwise Specified) Palme fem me [Vic [inputtowvonage | esos] — | om |v | [Vix | inputtigh vonage || 0 | | ees | [tn | nputorvo Low Leckage Current | ovsvmsvqwaxy | -— | — | 10 | a | [tr | inputorvorigh Leakage Curent [vusvwsvec | — | — | vo | ma | [Vou | ouputtowVotage | a= MAX. Vineveory | — [| — | os | v | [Vou [oumstinvonage [twa MAK Vineveorvy | ze | — | — | v | i ee [los [pu son Grow Guron | Wer varvoav vane | 30 | — | 10 | ma | Operating Power | Vi=05V Va=3.0V [tow n2emHz |u-ts [| — | 75 | ns | ma | Sipycue | Oapasopen tubal [terstomie [tas =| 75 | | ma | [teow =tomnz [assis | — | 45 | ss | ma | 1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester (ground degradation. Guaranteed but not 100% tested. 2) Typical values are at Voc = 5V and Ta= 25°C CAPACITANCE (T, = 25 C, f = 1.0 MHz) [_srmee[——anmneren [aur [re | vesTeovorens a a “Guaranteed but not 100% tested. 592 212

LATTICE SEMICONDUCTOR W7E D MM 5386949 0001944 9 MMLAT #Lattice Specifications GAL16V8A HIE Commercial AC SWITCHING CHARACTERISTICS. T- 4b V9 ~07 ‘Over Recommended Operating Conditions a Jramaucren) 55, [a an |_ted | 1 | tmoutorvoto combinational opt | sts | 3 | 25 | ne | | teo | 1 [crocktoouputdeay st to Le fe | ne | [toe | — | cocktorecdback doy | | a | to | ne | [__ tou | — | sowpime, nputorFeedbeckbetorecick | az | — | 15 |— | mw | li ia Extemal Feedback, 1/(tsu + tco) meee EE intemal Feedback, 1/(tsu + tcf) eee bd ed No Feedback ee ee ee ee [tw [ — [clock Puice Duration tow | 8 | — [te | | re | | [4 fipssvonowatnmee t= ts f= ta ta | 2 | cetouptenabed Ls [= [eo [ioe | | | ¢fapeetoseoummmntes __} — fis [fos fe | 3 [O€tooupudienbled Tt [= [20 | rw | 1) Reter to Switching Test Conditions section. 2) Calculated from fmax with intemal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. [input Puise Levels | GND too _| + [Input Rise and Fal Times | ns 10% ~90% __| | OutputTiming Reference Levels | 1.5V | Rt 3-state levels: red 0.5V from active Output Load Conditions (see figure) Re CL [ Testconaion | mx [| om | a | | @ | xpos afr] | ActveLow | 20a |" 3900 | S0pF | = | * HS ae (CL ncLuDes nc AND PRORE TOTAL CAPACITANCE | AciveLow [200 | soon | Ser | 213 see

LATTICE SEMICONDUCTOR 47E D M@ 5386949 OOOLS4S 0 MBLAT esa . Le Fle x19- 07 ELatti ce Specifications GAL16V8B siti Industrial ABSOLUTE MAXIMUM RATINGS" RECOMMENDED OPERATING COND. Supply voltage Veg -..-sssssesssssnsssssseneerseeneeeees O05 10 +7V Industrial Devices: Ambient Temperature with 1.Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC ELECTRICAL CHARACTERISTICS Over Recommended Operating Conditions (Uniess Otherwise Specified) fermce[ ramen | mmm fam re. re a [tu [ inputorvo Low Leakage Curent | ovsvasveamaxy | — | — | 100 | ya | [tr [imputorvo righ Leakage Curent | ssvsvusvec | = | — | 10 | wa | | Vor [ouputtowvorape | tx MAX. vin=Veorvn | — {| — | os | v | [vou [ouparign vonage [teva max vineveorvn | 24 | — | — | v | [tor [towiewiouacwen tT = | | | | [ton [rentewoupncomen [| — (| — | 2 | ma | | Tost | Oupu sont GicuitCurent | Voo=SV Vor=osv T=25¢ | -s0 | — | -150 | ma | Operating Power Supply Current Vu =0.5V Vin =3.0V fhogge = 25MHz 75 mA Outputs Open (no load) 1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second, Vout = 0.5V was selected to avoid test problems caused by tester (ground degradation. Guaranteed but not 100% tested. 3) Typical values are at Voc = SV and Ta= 25°C CAPACITANCE (T, = 25 C, f = 1.0 MHz) ' [_seeot[Panaweren | waxmowe [urs | resTeowomons | a a *Guaranteed but not 100% tested. ‘5/92 214

LATTICE SEMICONDUCTOR 47E D MM 5386949 0001946 2 MBLAT Lattice Specifications GAL1 6V8B SS5nte Industrial 4-19-07 Over Recommended Operating Conditions [ ocsewrron ne |

DESCRIPTION

Panamera [ min. [MAx. | win [MAx. | |__tea_| 1 | irptorvotocombinational Out | | to | 3 [5 | ne | [to [1 | ooxtoumoy Lt [7 [2 [0 [ow | | tor | — | CocktoFeedackDewy dT | OL [8 | ne | es ee eee esses Extemal Feedback, 1/(tsu + tco) freee TE Intemal Feedback, 1/(tsu + tcf) I a al No Feedback | tw | — [ciockruse ouationtow | TL | | re | a ee | 2 | Getoupuenades | 2 | to | [15 | re | | f-$- | rpsauomomumaves __}'2te |= fos ae | | 3 [Oetoupupicadied Lt | 10 [— fs | rw | 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with intemal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. [Input Rise and FallTimes | ns 10%-90% _| [ Output Timing Reference Levela | 1sV___| as 3-state levels are measured 0.5V from steady-state active FROM OUTPUT (0/Q) level, UNDER TEST TEST POINT Output Load Conditions (see figure) ce [_Testconawon | om [om | a | " [make igh [= [3800s vn L Accraroe—| goon | seon | eoor ¢ . || LLINCLUDES 5G AND PROBE TOTAL CAPACITANCE. S92 215

LATTICE SEMICONDUCTOR 47E D MM 5386949 000194? 4 MLAT Lattice Specifications GAL16V8A Ath Industrial shssee ABSOLUTE MAXIMUM RATINGS” RECOMMENDED OPERATING COND. Supply Voltage Vig vnsnsesenemnenmnnnnnnn0-510+7V Industrial Devices: T-$6-19-07 Ambient Temperature with Power Applied ...messsesesestnerenenenn 65 10 125°C 1.Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC ELECTRICAL CHARACTERISTICS Over Recommended Operating Conditions (Uniess Otherwise Specified) [ewe] remem | common | me [| [er [Wu | inputtowvorage | vena] — | oe |v [vir | inputtipmvorago | to | = | vce |v [tn | inputor vO Low Leakage Curent | ovsvwsvagmxy | — | — | 10 | ua | | [ieputorvo righ teatage cure | vusvusvoc | — | — | v0 | va | [Vou [oupurowvorage | x= Max vin=veorvm | — | — | os | v | [te [tewiawioupacoret | = | | ol [tow [Hionteverouputcurent [| = = | 2 | mm | [ tos" | Ouma ston Gicut Curent | vas=sv vorsosv tase | 2 | — | -160 | ma | Operating Power | Vi=05V Vi=3.0V | fesse =26mez [u26 | — | 7s | 190 | ma | Sip Gut | Otrte Cron ee ssix | o-nis | — | as | ss | ma | 1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Guaranteed but not 100% tested. 2) Typical values are at Voc = SV and Ta= 25 °C CAPACITANCE (T, = 25 C, f= 1.0 MHz) [_saeoc [paramere [waxwowr [urs [resTeowomons | a a “Guaranteed but not 100% tested. 2-16

LATTICE SEMICONDUCTOR 4?7E D MM 5386949 0001948 & MMLAT Lattice Specifications GAL16V8A HH Industrial T-4o-19-07 Over Recommended Operating Conditions st | pescnnion [_*_] Pere c| orem | | es | too | 1 | clocktooupuooay fe To fe fie [ne | [ter | — | ciccktoFecdbackoowy T= fe | Tt |e | |_ teu | — | sotupTine,tnputorFeecbackbetore cick | ta | — [ts | — | ne _| | tr [| — | Woatine,tnptorFeedbeckanercoce | o | — | o [— | ne | a a al Extemal Feedback, 1/(tsu + tco) mere EP Intemal Feedback, 1/(tsu + tef) ere EE No Feedback i a a eesonamee Ta To P| A [3 [oto te | = Ye Tne | 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with intemal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. e [input Rise and Fall Times _— | Sns 10%-90% | Sata levels are measured 0.5V from steady-state active FROM OUTPUT (Oy TEST PONT Output Load Conditions (see figure) cu [Teetconahen | m [ | & | me rs | ? exes {Sef or 592 217

LATTICE SEMICONDUCTOR Q?7E D MM 5386949 0001949 & MLAT # i Specifications GAL16V8B SWITCHING WAVEFORMS T- Yo VG -O7 VoFESDaAcK Were AM , Wo eepBACK NUN VALID INUT ak to OUTPUT imax (extemal tibk) ‘Combinatorial Output Registered Output WeUTor OE VO FEEDBACK = = ‘tds. ten Input or VO to Output Enable/Disable OE to Output EnableDisable Pwr a oK te te ‘REGISTERED Clock Width FEEDBACK ‘fmax with Feedback 2-18 see

LATTICE SEMICONDUCTOR 4?E D MM 5386949 OOOL9SO 4 MBLAT #Lattice Specifications GAL16V8B Hie GAL16V8A imax DESCRIPTIONS | i i b | Annay | ; ‘fmax with External Feedback 1/(tsu+tco) iL scan see senesnnsenneneseessness : Note: fmax with extemal feedbacks calculated from measured "a tsu and teo. fmax with intemal Feedback 1(tsustct) Note: tct is a calculated value, derived by subtracting tsu from the period of fmax w/intemal feedback (tof = 1/fmax - tsu). The value of tof is used primarily when calculating the delay from ork clocking a register to a combinatorial output (through registered H af : to.@ combinatorial output is equal to tcf + tpd. - ARRAY $ fimax With No Feedback Note: fmax with no feedback may be less than 1/(twh + tw)). This is to allow for a clock duty cycle of other than 50% 219 see

LATTICE SEMICONDUCTOR 47E D MM 5386949 0001951 b MBLAT eas . Lattice Specifications GAL16V8B H BH GAL16V8A mee ELECTRONIC SIGNATURE OUTPUT REGISTER PRELOAD @etlAgL mtoia ‘An electronic signature is provided in every GAL16VBAVB device. When testing state machine designs, all possible states and state | Itcontains 64 bits of reprogrammable memory that can contain _transitions must be verified in the design, not just those required User defined data, Some uses include user ID codes, revision _in the normal machine operations. This is because, in system numbers, orinventory control. The signature data is aways avai- operation, certain events occur that may throw the logic into an able to the user independent of the state of the security cell. illegal state (power-up, line voltage glitches, brown-outs, etc.), To test a design for proper treatment ofthese conditions, a way must NOTE: The electronic signature is included in checksum calcu- _be provided to break the feedback pathe, and force any desired ‘sequenced and the outputs tested for correct next state conditions. PSeCURITY CELL Mines ten eae SECURITY CELL present state condition can be forced for test sequencing. If j ; necessary, approved GAL programmers capable of executing text A security cel is provided in the GAL16V8AVB devices to prevent 4 4 tmnauthonced copying ofthe aray pattems. Once programmed, @71ors Perform output register proload aulomaticaly. this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, 80 the original configuration can never be examined once this colis programmed. The Electronic Signatureis always avait NIN] hs\\ Waals able to the user, regardless of the state of this control cell. GAL16V@AB devices are designed with TTL level compatible in- put buffers. These butfers have a characteristically high imped- | ance, and present a much lighter load to the driving logic than | LATCH-UP PROTECTION bipolar TTL devices. “The GAL16VEB input and VO pins have built-in active pull-ups. Rae ee eee a ee ee cr eae icorare, _A#.8 Fesull, unused inputs and V/O's wil float to a TTL “high* fcient magnitude fo prevent input undershoots from causing the (OSA) 1"). in contrast. the GAL 16VaA dogs not have acive Pu roulty to laich, Additionally, outpus are designed with n-channel UPS within their input structures. Lattice recommencie that al pulhups instead ofthe traditional p-channel pul-ups to eliminale Unueed in bth ve trent Dong tie wl ‘con- ; i or og this wl end | any possibility of SCR induced latching. to improve noise immunity and reduce |, for the device. | DEVICE PROGRAMMING ‘Typical input Pull-up Characteristic | GAL devices are programmed using a Lattice-approved Logic _ | Programmer, available from a number of manufacturers (see the g° GAL Development Tools section). Complete programming of the 2 | dovice takes only @ few seconds. Erasing of the device is 3 20 transparent o the user, and is done automatically as part of the 3 programming cycle. Z40 ~ 60 o 10 20 90 40 8.0 Input Voltage (Volts) 220 2

LATTICE SEMICONDUCTOR 47E D MM 5386949 0001952 & MBLAT Lattice Specifications GAL16V8B HH GAL16V8A POWER-UP RESET T-$¥6-19-07 Vee soy, ‘tsu- CLK wi tpr G FEEDBACK AND Circuitry within the GAL16V8A/B provides a reset signal to all reg- conditions must be met to guarantee a valid power-up reset of the isters during power-up. All internal registers will have theirQ device. First, the Vcc rise must be monotonic. Second, the clock outputs set low after a specified time (tpr, 11s MAX). As a result, input must be at static TTL level as shown in the diagram during the state on the registered output pins (if they are enabled) will power up. The registers will reset within a maximum of tpr time. always be high on power-up, regardiess of the programmed Asin normal system operation, avoid clocking the device until all polarity of the output pins. This feature can greatly simplify state _input and feedback path setup times have been met. The clock machine design by providing a known state on power-up. Be- must also meet the minimum pulse width requirements. cause of the asynchronous nature of system power-up, some INPUT/OUTPUT EQUIVALENT SCHEMATICS Ve ‘Active Pukup = ‘Ciroult ‘Acie Pullip (GAL16V88 only) Creat ¥ (GAL16028 ery) : Voc i i Wel} Voc Teste YE Vet } ehrealt ie : Lh PIN Ouiput Pw Lossceeeeeeeeeee Med {To Input Butter) Typ. Veet = 3.2V Typ. Vret = 3.2V Typical input Typical Output 592 2-21

LATTICE SEMICONDUCTOR 4?7E D MM $386949 0001953 T MBLAT Lattice Specifications GAL16V8B FH Typical Characteristics ( T- $619 -07 Normalized Tpd vs Veo Normalized Tco vs Veo Normalized Tsu vs Veo res} bres) recto BOL ey EE re BLT “ETT “ETT (Ett ‘Normalized Tpd vs Temp. Normalized Tco vs Temp Normalized Tsu vs Temp. "SLES eS ee eee ee ee er eee Peer Seer) op Ee Eiger) perry eer a wLLETT TT I wt ETT es a amputee 69.6) wT angen (tog) ne enowrn (669.0) ava Sal -LLLEEP?) _ CLEP ferry Facet {| T at tL fm att =| , ees) LE ees | vote Te Cup ening oats Ov Long Tee eS coo Jot =the PO ee) SS ae POO gO Che) Ree cd ce aetlmdie eh apt tdeg er) 592 2-22

LATTICE SEMICONDUCTOR 4?E D MM 5386949 0001954 1 MBLAT #Lattice Specifications GAL16V8B HEE Typical Characteristics T-¢b-19-01 Valve tt Von vaion Vonvatoh wt. . 2.11] = :. mt PTT | OF » Ltt tt | a ae ie el ec Normalized tov Veo Normatzed lo v9 Tame Normal lo v8 Frog Delta Icc vs Vin (1 Input) ‘Input Clamp (Vik) TOT see ait ATi TT spr et TUM TTT) f2- A+ STTUINT TT) © PAR + LLLYT ST BA -F } ea a a 2-23 sme

LATTICE SEMICONDUCTOR 47E D MM 5386949 0001955 3 MBLAT #Lattice Specifications GAL16V8A HA Typical Characteristics HE 9-07 Nea Tr a Nowmalaad Ta v8 Vee o_o 08 ra | [TT |, pt tt ,. a ow | tT tT | op yy | of ft tt nt) “e “Supply Vonage) Supp Votage (9) 1 Normalized Tpd vs. Temperature 1 ‘Normalized Tsu vs. Temperature Normalized Too vs. Temperature w-TTT TTT LETT T TTT “py yy | 2+ Pty tT er nL TT ber nas | ie PT MoM Tt Ty ic (Tho ttt) ie CEPT PB TYVET TTT) a.p Yt tt tg. aa “ALLE Sy} eT TE | SCTTETTyT] <tr o~LE ttt te) | © ambien Temperature (C) AmbirtTempeatie(C) bet Tampuatse (6) | Normaitzed Tpd vs. # of Oupute Switching . Delta Tp vs. Ourput Loading a Normalized ice vs. Vor | z” 3 ge i. i. : , | oo a aa a a fot Ouputs: Output Loading Capacitance (pf) ‘Supply Voltage (V)_ wo Jot vs, Vou lon vs. Vou Normalized loc vs. Temperature “TO oe - eX} ] ft : wEE TTT TT I z #1] tT gv RALTT Bm re i a | a | PEN. . | | INE 2 ES Jt TN) LEE TT TT mm van ert Temperate 6) | 2-24