PLSI1016E100LJ

ISP1016E LATTICE | Alldatasheet

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Technical content

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic
• HIGH-PERFORMANCE E 2CMOS ® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES — In-System Programmable™ (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Device for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity
• pLSI/ispLSI DEVELOPMENT TOOLS pDS ® Software — Easy to Use PC Windows™ Interface — Boolean Logic Compiler — Manual Partitioning — Automatic Place and Route — Static Timing Table ispDS+™ Software — Industry Standard, Third-Party Design Environments — Schematic Capture, State Machine, HDL — Automatic Partitioning and Place and Route — Comprehensive Logic and Timing Simulation — PC and Workstation Platforms Functional Block Diagram CLK Output Routing Pool Output Routing Pool Global Routing Pool (GRP) Logic Array DQ DQ DQ DQ GLB 0139C1-isp

Description

The ispLSI and pLSI 1016E are High-Density Programmable Logic Devices containing 96 Registers,

32 Universal I/O pins, four Dedicated Input pins, three

Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016E features 5-Volt in-system programming and in-system diagnostic capabilities. The ispLSI 1016E offers non-volatile “on-the-fly” reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. It is architecturally and parametrically compatible to the pLSI 1016E device, but multiplexes four input pins to control in-system programming. A functional superset of the ispLSI and pLSI 1016 architecture, the ispLSI and pLSI 1016E devices add a new global output enable pin. The basic unit of logic on the ispLSI and pLSI 1016E devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (see figure 1). There are a total of 16 GLBs in the ispLSI and pLSI 1016E devices. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. ispLSI and pLSI 1016E High-Density Programmable Logic 1016E_04 Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com February 1997

1996 ISP Encyclopedia

Specifications ispLSI and pLSI 1016E Absolute Maximum Ratings 1 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions TA = 0°C to + 70°C TA = -40°C to + 85°C SYMBOL Table 2-0005/1016E VCC VIH VIL PARAMETER Supply Voltage Input High Voltage Input Low Voltage MIN. MAX. UNITS 4.75 4.5 2.0 5.25 5.5 Vcc+1 0.8 V V V V Commercial Industrial Capacitance (TA =25oC, f=1.0 MHz) Data Retention Specifications C SYMBOL Table 2-0006/1016E C PARAMETER Y0 Clock Capacitance 12 UNITSTYPICAL TEST CONDITIONS 8Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance (Commercial/Industrial) pf pf V = 5.0V, V = 2.0V V = 5.0V, V = 2.0VCC CC PIN PIN Table 2-0008/1016E PARAMETER pLSI Erase/Reprogram Cycles 100 Data Retention MINIMUM MAXIMUM UNITS ispLSI Erase/Reprogram Cycles 10000 Cycles Years Cycles

Figure 2. Test Load *C L includes Test Fixture and Probe Capacitance.

1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems

by tester ground degradation. Guaranteed but not 100% tested.

1. Measured using four 16-bit counters.
2. Typical values are at V = 5V and T = 25°C.
3. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption

Specifications ispLSI and pLSI 1016E External Timing Parameters Over Recommended Operating Conditions tpd1 UNITS -125 MIN. TEST COND. 1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions Section. Table 2-0030-16/125,100, 80 tsu2 + tco1( ) -100 MIN.MAX. MAX.DESCRIPTION#2PARAMETER A 1 Data Prop. Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 ns tpd2 A 2 Data Prop. Delay, Worst Case Path – – ns fmax A 3 Clk. Frequency with Int. Feedback 125 – 100 – MHz fmax (Ext.) – 4 Clk. Frequency with Ext. Feedback – – MHz fmax (Tog.) – 5 Clk. Frequency, Max. Toggle – – MHz tsu1 – 6 GLB Reg. Setup Time before Clk., 4 PT Bypass – – ns tco1 A 7 GLB Reg. Clk. to Output Delay, ORP Bypass – – ns th1 – 8 GLB Reg. Hold Time after Clk., 4 PT Bypass 0.0 – ns tsu2 – 9 GLB Reg. Setup Time before Clk. 5.5 – ns tco2 – 10 GLB Reg. Clk. to Output Delay – – ns th2 – 11 GLB Reg. Hold Time after Clk. 0.0 – ns tr1 A 12 Ext. Reset Pin to Output Delay – – ns trw1 – 13 Ext. Reset Pulse Duration 5.0 – ns tptoeen B 14 Input to Output Enable – – ns tptoedis C 15 Input to Output Disable – – ns 100 167 5.0 4.5 5.5 10.0 12.0 12.0 10.0 125 7.0 0.0 8.0 0.0 6.5 3.5 0.0 13.0 5.0 6.0 13.5 15.0 15.0 ( ) twh + tw1 tgoeen B 16 Global OE Output Enable – – ns 7.0 9.0 tgoedis C 17 Global OE Output Disable – – ns 7.0 9.0 -80 MIN. MAX. 15.0 18.5 84.0 57.0 100 8.5 8.0 0.0 9.5 9.5 0.0 17.0 10.0 20.0 20.0 10.5 10.5 5.0 0.0 4.5 5.0

Specifications ispLSI and pLSI 1016E Internal Timing Parameters1 tiobp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Lattice hard macros. Table 2-0036-16/125,100, 80 Inputs UNITS -125 MIN. -100 MIN.MAX. MAX.DESCRIPTION#2PARAMETER 22 I/O Register Bypass – – 0.4 ns tiolat 23 I/O Latch Delay – – 2.4 ns tgrp1 29 GRP Delay, 1 GLB Load – – 1.9 ns GLB t1ptxor 36 1 Product Term/XOR Path Delay –– 6.1 ns t20ptxor 37 20 Product Term/XOR Path Delay –– 6.1 ns txoradj 38 XOR Adjacent Path Delay –– 6.6 ns tgbp 39 GLB Register Bypass Delay –– 1.6 ns tgsu 40 GLB Register Setup Time before Clock – 0.2 – ns tgh 41 GLB Register Hold Time after Clock – 2.5 – ns tgco 42 GLB Register Clock to Output Delay – – 1.9 ns tgro 43 GLB Register Reset to Output Delay – – 6.3 ns tptre 44 GLB Product Term Reset to Register Delay – – 5.1 ns tptoe 45 GLB Product Term Output Enable to I/O Cell Delay– – 7.1 ns tptck 46 GLB Product Term Clock Delay 4.8 5.3 ns ORP 0.3 1.8 GRP 1.8 t4ptbpc 34 4 Product Term Bypass Path Delay (Combinatorial)–– 5.7 ns 4.4 4.4 4.4 1.0 3.9 t4ptbpr 35 4 Product Term Bypass Path Delay (Registered) –– 5.6 ns3.9 0.2 1.5 1.8 4.4 3.5 5.5 3.2 3.5 torp 47 ORP Delay – – 1.0 ns torpbp 48 ORP Bypass Delay – – 0.0 ns 1.0 0.0 tiosu 24 I/O Register Setup Time before Clock 3.0 3.5 – ns– tioh 25 I/O Register Hold Time after Clock -0.3 -0.4 – ns– tioco 26 I/O Register Clock to Out Delay – – 5.0 ns4.0 tior 27 I/O Register Reset to Out Delay – – 5.0 ns4.0 tdin 28 Dedicated Input Delay – – 2.6 ns2.2 -80 MIN. MAX. 0.6 3.6 4.5 -0.6 7.5 7.5 3.9 2.9 7.1 8.2 8.3 1.9 8.1 7.3 -0.6 4.3 2.9 7.0 7.2 9.7 6.8 7.5 1.5 0.0 tgrp16 32 GRP Delay, 16 GLB Loads –– 3.1 ns tgrp4 30 GRP Delay, 4 GLB Loads –– 2.2 ns 2.4 1.9 tgrp8 31 GRP Delay, 8 GLB Loads –– 2.5 ns2.1 4.7 3.3 3.8

Specifications ispLSI and pLSI 1016E Internal Timing Parameters1 tob 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Table 2-0037-16/125,100,80 Outputs UNITS -125 MIN. -100 MIN.MAX. MAX.DESCRIPTION#2PARAMETER 49 Output Buffer Delay – – 1.7 ns tgy0 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)1.3 1.4 1.4 ns Global Reset 1.4 tsl 50 Output Slew Limited Delay Adder – – 10.0 ns 10.0 toen 51 I/O Cell OE to Output Enabled – – 5.3 ns 4.3 Clocks 1.3 tgr 59 Global Reset to GLB and I/O Registers – – 5.5 ns 3.2 todis 52 I/O Cell OE to Output Disabled – – 5.3 ns 4.3 tgoe 53 Global Output Enable – – 3.7 ns 2.7 tgy1/2 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.3 2.4 2.9 ns2.7 tgcp 56 Clock Delay, Clock GLB to Global GLB Clock Line0.8 0.8 1.8 ns1.8 tioy1/2 57 Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line0.0 0.0 0.4 ns0.3 tiocp 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line0.8 0.8 1.8 ns1.8 -80 MIN. MAX. – 3.0 – 10.0 – 6.4 – 6.4 – 4.1 4.5 2.1 2.1 3.6 4.4 1.2 2.7 0.0 0.6 1.2 2.7

Specifications ispLSI and pLSI 1016E ispLSI and pLSI 1016E Timing Model GLB Reg Delay I/O Pin (Output) ORP Delay Feedback Reg 4 PT Bypass 20 PT XOR Delays Control PTs Input Register Clock Distribution I/O Pin (Input) Y1,2 D Q GLB Reg Bypass ORP Bypass DQ RST RE OE CK I/O Reg Bypass I/O CellORPGLBGRPI/O Cell #23 - 27 #30 #35 #36-38 #55-58 #44-46 #54 #47 #48 Reset Ded. In GOE 0 #28 #22 RST #59 #59 #39 #40-43 #51, 52 0491-16 Comb 4 PT Bypass #34 #53 GRP Loading Delay #29, 31, 32 #49, 50 Derivations of tsu, th and tco from the Product Term Clock1 tsu Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) th Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) tco Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) Table 2-0042-16 Derivations of tsu, th and tco from the Clock GLB1 tsu Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) th Clock (max) + Reg h - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) tco Clock (max) + Reg co + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) 1. Calculations are based upon timing specifications for the ispLSI and pLSI 1016E- 125

value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. Figure 3. Typical Device Power Consumption vs fmax

even when the power is turned off. is generated when a read ID command is performed. Figure 4. ISP Programming Interface

Specifications ispLSI and pLSI 1016E ispLSI 1016E Shift Register Layout E2CMOS Cell Array High Order Shift Register Low Order Shift Register 79... 159... ...0 ...80 D A T A D A T A Data In (SDI) SDO 109. .Address Shift Register SDO SDI 0182B-16 Note: A logic “1” in the Address Shift Register bit position enables the row for programming or verification. A logic “0” disables it.

Specifications ispLSI and pLSI 1016E Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. It is a dedicated input pin when ispEN is logic high.SDI/IN0 also is used as one of the two control pins for the isp state machine. Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. This pin performs two functions: Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK controls become active. This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. Input/Output Pins - These are the general purpose I/O pins used by the logic array. NAME Table 2-0002C-16-isp SDI*/IN 0 ispEN**/NC MODE*/IN 2 Input - This pin performs two functions. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. It is a dedicated input pin when ispEN is logic high. GND VccVCC - Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. Output/Input - This pin performs two functions. When ispEN is logic low, it functions as an ouput pin to read serial shift register data. It is a dedicated input pin when ispEN is logic high. SDO*/IN 1 Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. It is a dedicated clock input when ispEN is logic high. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. SCLK*/Y2 Ground (GND) - Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. PLCC PIN NUMBERS 15, 19, 25, 29, 37, 41, 16, 20, 26, 30, 38, 42, 17, 21, 27, 31, 39, 43, 18, 22, 28, 32, 40, 44, 12, * ispLSI 1016E only ** ispEN for ispLSI 1016E; NC for pLSI 1016E must be left floating or tied to Vcc, must not be grounded or tied to any other signal. TQFP PIN NUMBERS 13, 19, 23, 31, 35, 41, 10, 14, 20, 24, 32, 36, 42, 11, 15, 21, 25, 33, 37, 43, 12, 16, 22, 26, 34, 38, 44, 17, Pin Description

Specifications ispLSI and pLSI 1016E Pin Configurations ispLSI and pLSI 1016E 44-pin PLCC Pinout Diagram ** Pins have dual function capability which is software selectable. I/O 18 I/O 17 I/O 16 *MODE/IN 2 Y1/RESET VCC *SCLK/Y2 I/O 15 I/O 14 I/O 13 I/O 12 I/O 28 I/O 29 I/O 30 I/O 31 VCC *ispEN/NC *SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 27 I/O 26 I/O 25 I/O 24 **GOE 0/IN 3 GND I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 GND *SDO/IN 1 I/O 8 I/O 9 I/O 10 I/O 11 ispLSI 1016E pLSI 1016E Top View 0123A-isp1016 * Pins have dual function capability for ispLSI 1016E only (except pin 13, which is ispEN only). ispLSI 1016E 44-pin TQFP Pinout Diagram I/O 18 I/O 17 I/O 16 *MODE/IN 2 Y1/RESET VCC *SCLK/Y2 I/O 15 I/O 14 I/O 13 I/O 12 I/O 28 I/O 29 I/O 30 I/O 31 VCC ispEN *SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 27 I/O 26 I/O 25 I/O 24 **GOE 0/IN 3 GND I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 GND *SDO/IN 1 I/O 8 I/O 9 I/O 10 I/O 11 ispLSI 1016E Top View 0851-16E/TQFP * Pins have dual function capability. ** Pins have dual function capability which is software selectable.

Specifications ispLSI and pLSI 1016E Part Number Description ispLSI and pLSI 1016E Ordering Information Device Number Grade Blank = Commercial I = Industrial ispLSI pLSI 1016E XXX X XXX X Speed Power L = Low Package J = PLCC T44 = TQFP Device Family 0212/1016E (is)pLSI 125 100

125 MHz fmax

100 MHz fmax

84 MHz fmax

44-Pin TQFPispLSI 1016E-80LT44 pLSI Table 2-0041A/1016E 125 100 44-Pin PLCC7.5 pLSI 1016E-125LJ 44-Pin PLCCpLSI 1016E-100LJ 84 15 44-Pin PLCCpLSI 1016E-80LJ FAMILY fmax (MHz) 125 125 100 ORDERING NUMBER PACKAGE 44-Pin PLCC 44-Pin TQFP tpd (ns) 7.5 7.5 10ispLSI ispLSI 1016E-125LJ ispLSI 1016E-125LT44 44-Pin PLCCispLSI 1016E-100LJ 100 44-Pin TQFP10 ispLSI 1016E-100LT44 COMMERCIAL Table 2-0041B/1016E FAMILY fmax (MHz) ORDERING NUMBER PACKAGE 44-Pin PLCC 44-Pin TQFP tpd (ns) ispLSI ispLSI 1016E-80LJI ispLSI 1016E-80LT44I INDUSTRIAL

Copyright © 1997 Lattice Semiconductor Corporation. E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation. Generic Array Logic, ISP, ispATE, ispCODE, ispDOWNLOAD, ispGDS, ispDS, ispDS+, ispStarter, ispSTREAM, ispTEST, ispTURBO, Latch-Lock, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders. Lattice Semiconductor Corporation (LSC) products are made under one or more of the following U.S. and international patents: 4,761,768 US, 4,766,569 US, 4,833,646 US, 4,852,044 US, 4,855,954 US, 4,879,688 US, 4,887,239 US, 4,896,296 US, 5,130,574 US, 5,138,198 US, 5,162,679 US, 5,191,243 US, 5,204,556 US, 5,231,315 US, 5,231,316 US, 5,237,218 US, 5,245,226 US, 5,251,169 US, 5,272,666 US, 5,281,906 US, 5,295,095 US, 5,329,179 US, 5,331,590 US, 5,336,951 US, 5,353,246 US, 5,357,156 US, 5,359,573 US, 5,394,033 US, 5,394,037 US, 5,404,055 US, 5,418,390 US, 5,493,205 US, 0194091 EP, 0196771B1 EP, 0267271 EP, 0196771 UK, 0194091 GB, 0196771 WG, P3686070.0-08 WG. LSC does not represent that products described herein are free from patent infringement or from any third-party right. The specifications and information herein are subject to change without notice. Lattice Semiconductor Corporation (LSC) reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors contained herein or to advise any user of this document of any correction if such be made. LSC recommends its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current. LSC warrants performance of its products to current and applicable specifications in accordance with LSC’s standard warranty. Testing and other quality control procedures are performed to the extent LSC deems necessary. Specific testing of all parameters of each product is not necessarily performed, unless mandated by government requirements. LSC assumes no liability for applications assistance, customer’s product design, software performance, or infringements of patents or services arising from the use of the products and services described herein. LSC products are not authorized for use in life-support applications, devices or systems. Inclusion of LSC products in such applications is prohibited. LATTICE SEMICONDUCTOR CORPORATION

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Hillsboro, Oregon 97124 U.S.A. Tel.: (503) 681-0118 FAX: (503) 681-3037 http://www.latticesemi.com February 1997