PAC-POWR1208 LATTICE | Alldatasheet
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Technical content
power-supply designer with a rich set of features in a single device. is accomplished through an industry-standard JTAG IEEE 1149.1 interface. Figure 1. PAC-POWR1208-EV Evaluation Board
A complete schematic for the evaluation board is shown in Figure 2. Figure 2. Schematic connector which plugs directly into a mating connector provided on the PAC-POWR1208-EV evaluation board.
On the evaluation board, VDD and VDDINP are normally connected together with a user-removable jumper (J7.5). This jumper can be removed to allow for independent VDD and VDDINP supplies. supplied through two color coded (RED = +, BLACK = -) banana jacks in the upper right corner of the board. PAC-POWR1208-EV evaluation boards into a multi-device programming chain. the JTAG programming interface) are accessible. Figure 3. I/O and Jumpers to be removed when using separate VDD and VDDINP supplies.
tializing the ispPAC-POWR1208. Figure 4. Silk Screen
ispPAC-POWR1208 Evaluation Board Lattice Semiconductor PAC-POWR1208-EV Component List Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-408-826-6002 (Outside North America) e-mail: isppacs@latticesemi.com Internet: www .latticesemi.com Quantity Ref. Designators Description 2 C1, C3 0.1µF capacitor
1 C2 1µF capacitor
1C 4 0.1µF capacitor 1C 5 4.7µF capacitor 1J 72 x 5 header strip, dual row, 0.1” spacing 2 J8,J9 1 x 3 header strip, single row, 0.1” spacing
5 LED_A, LED_B, LED_C, LED_D,
POWER_LED T-1-3/4 red LED 1P 1 1x8 header strip, single row, 0.1” spacing 1P 3 Red banana jack 1P 4 Black banana jack 1R 1 470 ohm SIP-8 resnet, 7-resistor SIP , bussed type 1R 2 10K resistor