MS85RS1MTY RAMXEED | Alldatasheet
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Copyright 2024 RAMXEED LIMITED Fujitsu Semiconductor Memory Solutions Limited has changed its name to RAMXEED Limited. RAMXEED Limited will continue to offer and support existing products while maintaining Fujitsu's part number unchanged. Memory FeRAM 1M (128K 8) Bit SPI MS85RS1MTY(AEC-Q100 Compliant) DESCRIPTION MS85RS1MTY is a FeRAM (Ferroelectric Random Access Memory) chip in a configuration of 131,072 words 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. This product is specifically targeted for high-temperature environment such as automobile applications. MS85RS1MTY adopts the Serial Peripheral Interface (SPI). The MS85RS1MTY is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MS85RS1MTY can be used for 1013 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. As MS85RS1MTY does not need any waiting time in writing process, the write cycle time of MS85RS1MTY is much shorter than that of Flash memories or E2PROM. FEATURES
- Bit configuration : 131,072 words 8 bits
- Special Sector Region : 256 words 8 bits In this region, data storage after (by) three times reflow based on JEDEC MSL-3 standard condition is guaranteed.
- Unique ID
- Serial Number : 64 bits In this region, data storage after (by) three times reflow based on JEDEC MSL-3 standard condition is guaranteed.
- Serial Peripheral Interface : SPI (Serial Peripheral Interfaces) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
- Operating frequency : 50 MHz (Max)
- High endurance : 1013 times (+125 C),
- Data retention : 70.4 years (+85 C), 19.1 years (+105 C), 5.9 years (+125 C) or more Under evaluation for more than 5.9 years(+125 C)
- Operating power supply voltage : 1.8 V to 3.6 V
- Low power consumption : Operating power supply current 4mA (Max@50 MHz) Standby current 150A (Max) Deep Power Down current 30A (Max) Hibernate current 10A (Max)
- Operation ambient temperature range : 40 C to +125 C
- Package 8-pin plastic SOP (150mil) 8-pin plastic DFN (5mm x 6mm) RoHS compliant DS501-00096-1v0-E
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PIN ASSIGNMENT PIN FUNCTIONAL DESCRIPTIONS Pin No. Pin Name Functional description 1 CS Chip Select pin This is an input pin to make chips select. When CS is “H” level, device is in deselect (standby) status and SO becomes High-Z. Inputs from other pins are ignored for this time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before inputting op-code. 3 WP Write Protect pin This is a pin to control writing to a status register. The writing of status register (see “ STATUS REGISTER”) is protected in related with WP and WPEN. See “ WRITING PROTECT” for detail.
7 HOLD
This pin is used to interrupt serial input/output without making chips deselect. When HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become do not care. See “ HOLD OPERATION” for detail. The Hold pin is pulled up internally to the VDD pin.
6 SCK
This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge.
5 SI Serial Data Input pin
This is an input pin of serial data. This inputs op-code, address, and writing data. 2 SO Serial Data Output pin This is an output pin of serial data. Reading data of FeRAM memory cell array and status register data are output. This is High-Z during standby.
8 VDD Supply Voltage pin
4 VSS Ground pin
8-pin plastic SOP(150mil) (TOP VIEW) VSS SI SO VDD SCKWP CS HOLD 8-pin plastic DFN(5mm x 6mm) (TOP VIEW) VSS SI SO VDD SCKWP CS HOLD DIE PAD
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 3 BLOCK DIAGRAM SPI MODE MS85RS1MTY corresponds to the SPI mode 0 (CPOL 0, CPHA 0) , and SPI mode 3 (CPOL 1, CPHA 1) . SCK SO SI Serial-Parallel Converter FeRAM Cell Array 131,072 x 8 Column Decoder/Sense Amp/ Write Amp FeRAM Status Register Data Register Parallel-Serial Converter Control Circuit Address Counter Row DecoderCS WP FeRAM Special Sector 256 x 8 FeRAM Serial Number 8 x 8 FeRAM UID 8 x 8 HOLD SCK SI CS SCK SI CS 76543210 76543210 MSB LSB MSB LSB SPI Mode 0 SPI Mode 3
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SERIAL PERIPHERAL INTERFACE (SPI) MS85RS1MTY works as a slave of SPI. More than 2 devices can be connected by using microcontroller equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus connected to use. SCK SS1 HS1 MOSI MISO SS2 HS2 SCK CS HOLD SI SO SCK CS HOLD SI SO MS85RS1MTY MS85RS1MTY SCK CS HOLD SI SO MS85RS1MTY SPI Microcontroller MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select HS : Hold Select System Configuration with SPI Port System Configuration without SPI Port Microcontroller
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 5 STATUS REGISTER Bit No. Bit Name Function
7 WPEN
Status Register Write Protect This is a bit composed of nonvolatile memories (FeRAM). WPEN protects writing to a status register (refer to “ WRITING PROTECT”) relating with WP input. Writing with the WRSR command and reading with the RDSR command are possible. 6 to 4 Not Used Bits These are bits composed of nonvolatile memories, writing with the WRSR command is possible. These bits are not used but they are read with the RDSR command.
3 BP1 Block Protect
This is a bit composed of nonvolatile memory. This defines size of write protect block for the WRITE command (refer to “ BLOCK PROTECT”). Writing with the WRSR command and reading with the RDSR command are possible.
2 BP0
1 WEL
This indicates FeRAM Array and status register are writable. The WREN command is for setting, and the WRDI command is for resetting. With the RDSR command, reading is possible but writing is not possible with the WRSR command. WEL is reset after the following operations. After power ON. After WRDI command recognition. After return from DPD mode. After return from Hibernate mode. Achieving continuous writing mode, WEL is not reset after following oper- ations making it possible to execute writing commands continuously. After WRSR command recognition. After WRITE command recognition. After WRSN command recognition. After SSWR command recognition. 0 0 This is a bit fixed to “0”.
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OP-CODE MS85RS1MTY accepts 16 kinds of command specified in op-code. Op-code is a code composed of 8 bits shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code, the command are not performed. Name Description Op-code WREN Set Write Enable Latch 0000 0110B WRDI Reset Write Enable Latch 0000 0100B RDSR Read Status Register 0000 0101B WRSR Write Status Register 0000 0001B READ Read Memory Code 0000 0011B WRITE Write Memory Code 0000 0010B FSTRD Fast Read Memory Code 0000 1011B DPD Deep Power Down Mode 1011 1010B HIBERNATE Hibernate Mode 1011 1001B RDID Read Device ID 1001 1111B RUID Read Unique ID 0100 1100B WRSN Write Serial Number 1100 0010B RDSN Read Serial Number 1100 0011B SSWR Write Special Sector 0100 0010B SSRD Read Special Sector 0100 1011B FSSRD Fast Read Special Sector 0100 1001B RFU Reserved 1100 1110B 1100 1111B 1100 1100B
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 7 COMMAND WREN The WREN command sets WEL (Write Enable Latch) bit to 1. WEL has to be set with the WREN command before writing operation (WRSR command, WRITE command, WRSN command and SSWR command) . WRDI The WRDI command resets WEL (Write Enable Latch) bit to 0. Writing operation (WRSR command, WRITE command, WRSN command and SSWR command) are not performed when WEL is reset. SO SCK SI CS 00000110 High-Z 7 6 5 432 1 0 InvalidInvalid SO SCK SI CS 00000100 High-Z 7 6 5 432 1 0 InvalidInvalid
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RDSR The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising of CS. WRSR The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot be written. The SI value corresponding to bit 0 is ignored. WP signal level shall be fixed before performing WRSR command, and do not change the WP signal level until the end of command sequence. SO SCK SI CS 00000101 High-Z 7 6 5 432 1 0 Invalid MSB 7 6 5 432 1 0 Data Out LSB Invalid SO SCK SI CS 00000001 7 6 5 432 1 0 Data In MSB 7 6 5 432 1 0 High-Z LSB 76543 210 Instruction
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 9 READ The READ command reads FeRAM memory cell array data. Arbitrary 24 bits address and op-code of READ are input to SI. The 7-bit upper address is invalid.Then, 8-cycle clock is input to SCK. SO is output synchro- nously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. WRITE The WRITE command writes data to FeRAM memory cell array. WRITE op-code, arbitrary 24 bits of address and 8 bits of writing data are input to SI. The 7-bit upper address is invalid.When 8 bits of writing data is input, data is written to FeRAM memory cell array. Risen CS will terminate the WRITE command, but if you continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing with automatic address increment. When it reaches the most significant address, it rolls over to the starting address, and writing cycle can be continued infinitely. FSTRD The FSTRD command reads FeRAM memory cell array data. Arbitrary 24bits address and op-code of FSTRD are input to SI followed by 8 bits dummy. The 7-bit upper address is invalid.Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the FSTRD command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. SO SCK SI CS 00 0 0X 1X X MSB 7 6 5 4 3 2 1 0 Data OutMSB High-Z LSB 420 1 Invalid 13 1211109 8 33 323130292827 26 39 3837 36 35 34 00 1 X X X 35 Invalid LSB 20 1 364 5 7 X1 6 14 15 OP-CODE 24-bit Address SO SCK SI CS 00 0 0X 1 XX MSB 7 6 5 4 3 2 1 0 Data In MSB High-Z LSB 420 1 13 1211109 8 33 32 31 30292827 26 3938 37 36 35 34 00 0 X X X 35 LSB 20 1364 5 7X1 6 14 15 OP-CODE CS SCK SI Invalid MSB LSB MSB Data Out LSBHigh-Z Invalid 450123 2 9 3 0 6 7 8 9 10 11 12 13 1415 46 47 31 32 38 39 40 41 42 43 44 45 00001011 X 210X XX SO 7 XX 0543 X XX XX 1 6 OP-CODE 24-bit Address 8-bit Dummy
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RDID The RDID command reads fixed Device ID. After performing RDID op-code to SI, 32-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte). In the RDID command, 32-bit Device ID is output by continuously sending SCK clock, and SO holds the output state of the last bit until CS is risen. RUID The RUID command reads an unique ID which is defined in 64bits for each device. After performing RUID op-code to SI, 64-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The unique ID is stable between before and after reflow. Refer “ REFLOW CONDITIONS AND FLOOR LIFE” for the reflow condition. SO SCK SI CS MSB 7 6 5 4 3 2 1 0 Data OutData Out High-Z LSB 11 109 8 33 32 31 39 38 37 36 35 34 Invalid 30 2829 31 10011111 20 1 364 5 7 8 bit 7 6 5 4 3 2 1 0 Hex Manufacturer ID 0 0 0 0 0 1 0 0 04 H Continuation code 0 1 1 1 1 1 1 1 7F H Proprietary use Density Hex Product ID (1st Byte) 0 1 0 0 0 1 1 1 47 H Density: 00111B 1Mbit Proprietary use Hex Product ID (2nd Byte) 0 0 0 0 0 0 1 1 03 H SO SCK SI CS MSB 7 6 5 4 3 2 1 0 Data OutData Out High-Z LSB 11 109 8 65 64 63 71 70 69 68 67 66 Invalid 62 6061 63 01001100 20 1 364 5 7 8
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 11 WRSN The WRSN command writes data to serial number region which is allowed to write only one time. After performing WRSN op-code to SI, 64bits of writing data is input. Once wrote, the serial number region is protected, disabling to overwrite even when issuing WRSN command. WP signal level shall be fixed before performing WRSN command, and do not change the WP signal level until the end of command sequence. RDSN The RDSN command reads 64 bits of serial number which is written using WRSN command. After performing RDSN op-code to SI, 64-cycle clock to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. When reading serial number from devices which no WRSN com- mand is executed, “0” for all bits are output. The serial number is stable between before and after reflow. Refer “ REFLOW CONDITIONS AND FLOOR LIFE” for the reflow condition. SO SCK SI CS 7 6 5 4 3 2 1 0 Data inData in High-Z 11 109 8 65 64 63 71 70 69 68 67 66 62 6061 631100001 0 20 1 364 5 7 8 SO SCK SI CS MSB 7 6 5 4 3 2 1 0 Data OutData Out High-Z LSB 11 109 8 65 64 63 71 70 69 68 67 66 Invalid 62 6061 63 11000011 20 1 364 5 7 8
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SSWR The SSWR command writes data to special sector (a special region of 256 Byte in FeRAM). SSWR op-code, arbitrary 24 bits address and 8-bit writing data are input to SI. The 16-bit upper address is invalid. When input of 8-bit writing data is completed, it starts writing data to special sector. Risen CS will terminate the SSWR command, but if you continue the writing data for each before CS rising, it is possible to continue writing with automatic address increment. When it reaches the most significant address, roll over is not happen, the data hereafter is ignored. The data in special sector is stable between before and after reflow. Refer “ REFLOW CONDITIONS AND FLOOR LIFE” for the reflow condition. SSRD The SSRD command reads data from special sector (a special region of 256 Byte in FeRAM). SSWR op- code and arbitrary 24 bits address are input to SI. The 16-bit upper address is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the SSRD command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, roll over is not happen. The data in special sector is stable between before and after reflow. Refer “ REFLOW CONDITIONS AND FLOOR LIFE” for the reflow condition. CS SCK Data In SI MSB LSB MSB LSB High-Z 10 110123456789 24 25 26 31 3223 27 28 29 30 33 34 35 36 37 38 39 0100001 30XXXX 6 210 SO X7 54 32107654 24 bit addressesope. code CS SCK SI Invalid MSB LSB MSB Data Out LSBHigh-Z Invalid 450123 2 6 2 7 6 7 8 9 10 11 23 24 25 38 39 28 29 30 31 32 33 34 35 36 37 01001011X 32XXX 6 X7 54 SO 76 3 54 210 24 bit addressesope. code
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 13 FSSRD The SSRD command reads data from special sector (a special region of 256 Byte in FeRAM). SSWR op- code and arbitrary 24 bits address are input to SI followed by 8 bits dummy. The 7-bit upper address is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the SSRD command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, roll over is not happen. The data in special sector is stable between before and after reflow. Refer “ REFLOW CONDITIONS AND FLOOR LIFE” for the reflow condition. CS SCK SI Invalid MSB LSB MSB Data Out LSBHigh-Z Invalid 450123 2 9 3 0 6 8 9 1 01 1 2 52 62 7 2 8 4 64 7 31 32 38 39 40 41 42 43 44 45 01001001X 4 210X XX SO 7 XXX 65 0543 X 24 23 7 X 24 bit addressesope. code 8 bit dummy
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DPD(Deep Power Down) The DPD command shifts the LSI to a low power mode called “DPD mode”. The transition to the DPD mode is carried out at the rising edge of CS after operation code in the DPD command. However, when at least one SCK clock is inputted before the rising edge of CS after operation code in the DPD command, this DPD command is canceled. After the DPD mode transition, SCK and SI inputs are ignored and SO changes to a High-Z state. Returning to an normal operation from the DPD mode is carried out after tRECDPD (Max 10 s) time from the falling edge of CS (see the figure below). It is possible to return CS to H level before tRECDPD time. However, it is prohibited to bring down CS to L level again during tRECDPD period. Enter DPD Mode CS SCK SI Invalid Invalid High-Z DPD Mode Entry 67012345 SO 01011101 CS CS tRECDPD Exit DPD Mode DPD Mode Exit tCSWL From this time Command input enable
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 15 HIBERNATE The HIBERNATE command shifts the LSI to a low power mode called “HIBERNATE mode”. The transition to the HIBERNATE mode is carried out at the rising edge of CS after operation code in the HIBERNATE command. However, when at least one SCK clock is inputted before the rising edge of CS after operation code in the HIBERNATE command, this HIBERNATE command is canceled. After the HIBERNATE mode transition, SCK and SI inputs are ignored and SO changes to a High-Z state. Returning to an normal operation from the HIBERNATE mode is carried out after tRECHIB (Max 450 s) time from the falling edge of CS (see the figure below). It is possible to return CS to H level before tRECHIB time. However, it is prohibited to bring down CS to L level again during tRECHIB period. Enter Hibernate Mode CS SCK SI Invalid Invalid High-Z Hibernate Mode Entry 67012345 SO 0101110 1 CS CS tRECHIB Exit Hibernate Mode Hibernate Mode Exit tCSWL From this time Command input enable
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BLOCK PROTECT Writing protect block for WRITE command is configured by the value of BP0 and BP1 in the status register. WRITING PROTECT Writing operation of the WRITE command and the WRSR command are protected with the value of WEL, WPEN, WP as shown in the table. HOLD OPERATION Hold status is retained without aborting a command if HOLD is “L” level while CS is “L” level. The timing for starting and ending hold status depends on the SCK to be “H” level or “L” level when a HOLD pin input is transited to the hold condition as shown in the diagram below. In case the HOLD pin transited to “L” level when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the same manner, in case the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H” level at SCK being “H” level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become do not care. And, SO becomes High-Z while reading command (RDSR, READ). If CS is rising during hold status, a command is aborted. In case the command is aborted before its recognition, WEL holds the value before transition to hold status. BP1 BP0 Protected Block 0 0 None 0 1 18000 H to 1FFFFH (upper 1/4) 1 0 10000 H to 1FFFFH (upper 1/2) 1 1 00000 H to 1FFFFH (all) WEL WPEN WP Protected Blocks Unprotected Blocks Status Register
0 X X Protected Protected Protected
1 0 X Protected Unprotected Unprotected 1 1 0 Protected Unprotected Protected 1 1 1 Protected Unprotected Unprotected SCK CS Hold Condition HOLD Hold Condition
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 17 ABSOLUTE MAXIMUM RATINGS *: These parameters are based on the condition that VSS is 0 V. WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. RECOMMENDED OPERATING CONDITIONS *1: These parameters are based on the condition that VSS is 0 V. *2: Ambient temperature when only this device is working. Please consider it to be the almost same as the package surface temperature. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Parameter Symbol Rating Unit Min Max Power supply voltage* VDD 0.5 4.0 V Input voltage* VIN 0.5 V DD 0.5( 4.0) V Output voltage* VOUT 0.5 V DD 0.5( 4.0) V Operation ambient temperature T A 40 125 C Storage temperature Tstg 55 150 C Parameter Symbol Value Unit Min Typ Max Power supply voltage*1 VDD 1.8 3.3 3.6 V Operation ambient temperature*2 TA 40 125 C
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ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) *1 : Applicable pin : CS, WP, SCK, SI *2 : Applicable pin : SO *3 : Input voltage magnitude : VDD 0.2 V or VSS Parameter Sym- bol Condition Value Unit Min Typ (TA=25 C) Max Input leakage current*1 |ILI| CS VDD 25 C 1 125 C 2 WP, SCK,CS SI 0 V to VDD 25 C 1 125 C 2 HOLD 0 V to VDD 25 C 100 125 C 100 Output leakage current*2 |ILO| SO 0 V to V DD 25 C 1 125 C 2 Operating power supply current*3 IDD SCK 50MHz 3 4 mA Standby current ISB SCK SI CS WP VDD 12 150 A Hibernate current I ZZHIB CS VDD All inputs VSS or VDD 0.3 10 A DPD current IZZDPD CS VDD All inputs VSS or VDD 6 30 A Input high voltage V IH VDD = 1.8 V to 3.6 V V DD 0.8 VDD 0.5 V Input low voltage VIL VDD = 1.8 V to 3.6 V 0.5 VDD 0.2 V Output high voltage V OH IOH 2 mA VDD 0.5 V Output low voltage V OL IOL 2 mA 0.4 V Pull up resistance for HOLD RP 36 66 230 kΩ
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 19 2. AC Characteristics *1: In SSRD command, 60ns(max.) AC Test Condition Power supply voltage : 1.8 V to 3.6 V Operation Operation ambient temperature : 40 C to 125 C Input voltage magnitude : V DD 0.8 VIH VDD 0 VIL VDD 0.2 Input rising time : 5 ns Input falling time : 5 ns Input judge level : VDD/2 Output judge level : VDD/2 Parameter Symbol Value Unit Condition VDDMin Max SCK clock frequency fCK 50 MHz all commands ex- cept for READ/ SSRD 40 READ command 10 SSRD command Clock high time tCH 9 ns Clock low time tCL 9 ns Chip select set up time tCSU 5 ns Chip select hold time tCSH 5 ns Output disable time tOD 10 ns Output data valid time tODV 8 ns *1 Output hold time tOH 0 ns Deselect time tD 40 ns Data in rising time tR 50 ns Data falling time tF 50 ns Data set up time tSU 5 ns Data hold time tH 5 ns HOLD set uptime tHS 10 ns HOLD hold time tHH 10 ns HOLD output floating time tHZ 20 ns HOLD output active time tLZ 20 ns DPD/Hibernate recovery pulse width tCSWL 100 ns DPD recovery time tRECDPD 10 s Hibernate recovery time tRECHIB 450 s
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AC Load Equivalent Circuit 3. Pin Capacitance Parameter Symbol Condition Value Unit Min Max Output capacitance CO VDD 3.3 V, VIN VOUT 0 V to VDD, f 1 MHz, TA +25 C 8 pF Input capacitance CI 6 pF 30 pF Output VDD
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 21 TIMING DIAGRAM Serial Data Timing
- Hold Timing SCK CS Valid inSI SO High-Z : H or L tCSU tCH tCHtCL tSU tH tODV tOH tOD tCSH tD High-Z SCK CS SO tHS tHS tHHtHH tHH tHH tHZ tLZ tHZ tLZ tHS tHS HOLD High-ZHigh-Z
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POWER ON/OFF SEQUENCE In case relative short V DD pulse whose peak level is beyond 1.7 is applied, please set V DD falling time, tf, longer than 0.4ms/V. (When VDD rises beyond 1.7V, and falls just after, if this term is very short the device may loose its function.) If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed. Parameter Symbol Value Unit Condition VDDMin Max CS level hold time at power OFF tpd 400 ns 1.8V to 2.7V 0 2.7V to 3.6V CS level hold time at power ON tpu 450 s Power supply rising time tr 0.05 ms/V Power supply falling time tf 0.1 ms/V CS >VDD /g117 0.8 /g13 tpd tputrtf VIL (Max) 1.7 V VIH (Min) VDD (Min) VDD CS : don't care CS >VDD /g117 0.8 /g13CS CS VIL (Max) 1.7 V V IH (Min) VDD (Min) VDD VSS VSS * : CS (Max) < VDD 0.5 V
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 23 FeRAM CHARACTERISTICS *1:The value for Read/Write endurance apply to the total number of read and write operations per row in FeRAM. This is because FeRAM needs writing operation after each reading operations. Each row in the memory array has 32 internal outputs, and 8 outputs are selected by A0 and A1. In continuous Read/Write operations, after selecting a certain address and automatically incrementing until A0 and A1 change from (0,0) to (1,1), the Read/Write count endurance count is totaled as one operation. Subsequently, when incrementing auto- matically and switching to the next row, each row is counted as a new Read/Write operation. If /CS is raised and then the same row is selected again, it is counted as the second operation for that row. *2: Minimum values define retention time of the first reading/writing data right after shipment, and these values are calculated by qualification results. *3: Under evaluation for more than 5.9 years(+125 C). NOTE ON USE We recommend programming of the device after reflow except for special sector region and serial number region. Data written before reflow cannot be guaranteed. Parameter Value Unit RemarksMin Max Read/Write Endurance*1 1013 Times Operation Ambient Temperature T A 125 C Data Retention*2 5.9 or more*3 Years Operation Ambient Temperature TA 125 C 19.1 Operation Ambient Temperature TA 105 C 70.4 Operation Ambient Temperature TA 85 C
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ESD AND LATCH-UP REFLOW CONDITIONS AND FLOOR LIFE [ JEDEC MSL ] : Moisture Sensitivity Level 3 (IPC/JEDEC J-STD-020E) Current status on Contained Restricted Substances This product complies with the regulations of REACH Regulations, EU RoHS Directive and China RoHS. Test DUT Value ESD HBM (Human Body Model) JEDEC JS001 compliant MS85RS1MTYPNF-GS-BDE1 MS85RS1MTYPNF-GS-BDERE1 MS85RS1MTYPN-GS-AWE1 MS85RS1MTYPN-GS-AWEWE1 |2000 V| ESD CDM (Charged Device Model) JEDEC JS002 compliant |1000 V| Latch-Up (I-test) JESD78 compliant |125mA| Latch-Up (Vsupply overvoltage test) JESD78 compliant 5.4V
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 25 ORDERING INFORMATION : * : Please contact our sales office about minimum shipping quantity. Part number Package Shipping form Minimum shipping quantity MS85RS1MTYPNF-GS-BDE1 8-pin plastic SOP Tube * MS85RS1MTYPNF-GS-BDERE1 8-pin plastic SOP Embossed Carrier tape 1500 MS85RS1MTYPN-GS-AWE1 8-pin plastic DFN Tray * MS85RS1MTYPN-GS-AWEWE1 8-pin plastic DFN Embossed Carrier tape 1500
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PACKAGE DIMENSION (1) MS85RS1MTYPNF-GS-BDE1/MS85RS1MTYPNF-GS-BDERE1 8-pin plastic SOP(150mil) Lead pitch 1.27m m Lead shape Gullwing Sealing method Plastic mold Mounting height 1.75mm MAX. 8-pin plastic SOP Dimension in mm㸸 (1.40) Details of “F”part 1.75 MAX. “F” Note *: These dimension do not include resin protrution. Pins width do not include tie bar cutting remaindar. 0.10 S S Package width x Package length 3.90mm x 4.90mm 0.05 MIN. 0.40 MIN. 㹼 1pin 4pin 5pin8pin 3.90s* 0.41±0.101.27 s
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 27 (2) MS85RS1MTYPN-GS-AWE1/MS85RS1MTYPN-GS-AWEWE1 0.05 8-pin plastic DFN Lead pitch 1.27 mm Package width x Package length 5.00 mm × 6.00 mm Sealing method Plastic mold Mounting height 0.90 mm MAX 8-pin plastic DFN (LCC-8P-M05) 5.00±0.10 INDEX AREA 6.00±0.10 0.40±0.10 4.10±0.10 1.27 BSC. 0.90 MAX. Dimensions in mm. Note: The values in parentheses are reference values. 4.00±0.100.60±0.10 C0.30 0.05 MAX. 0.17 WR0.25 1PIN CORNER
MS85RS1MTY(AEC-Q100 Compliant)
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MARKING (Example) (1) MS85RS1MTYPNF-GS-BDE1/MS85RS1MTYPNF-GS-BDERE1 (2) MS85RS1MTYPN-GS-AWE1/MS85RS1MTYPN-GS-AWEWE1 [MS85RS1MTYPNF-GS-BDE1] [MS85RS1MTYPNF-GS-BDERE1] S1MTY: Product name A2300 : A(CS code) + 2300(Year and Week code) 701 : Trace code S1MTY A2300 701 [MS85RS1MTYPN-GS-AWE1] [MS85RS1MTYPN-GS-AWEWE1] MS85RS1MTY: Product name AE1 : A(CS code) + E1(Lead free code) 2300R00：2300(Year and Week code) + R00(Trace code) MS85RS1MTY AE1 2300R00
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 29 PACKING INFORMATION (1) MS85RS1MTYPNF-GS-BDE1/MS85RS1MTYPNF-GS-BDERE1 1. Tube (MS85RS1MTYPNF-GS-BDE1)
1.1 Tube Dimensions
- Tube/stopper shape (example)
- Tube cross-sections and Maximum quantity
- Direction of index in tube Maximum quantity pcs/tube(500mm) pcs/inner box pcs/outer box No heat resistance. Package should not be baked by using tube. 85 4,250 17,000 (Dimensions in mm) Stopper Tube 9.5 Index mark
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1.2 Product label indicators (example)
Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm 100mm) Supplemental Label (20mm 100mm)] C-3 Label Supplemental Label Perforated line (Part number) (Part number) (Control number bar code) XX/XX XXXX-XXX XXX XXXX-XXX XXX (Lot Number and quantity) (Package count) (Part number bar code) (Part number and quantity) (Control number bar code) QC PASS XXXXXXXXXXXXXX XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx (3N)1 XXXXXXXXXXXXXX XXX (Quantity) (3N)2 XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX (Part number)XXXXXXXXXXXXXX (Comment)XXXXXXXXXXXXXX (Control number )XXXXXXXXXX (LEAD FREE mark)
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1.3 Dimensions for Containers
(1) Dimensions for inner box (2) Dimensions for outer box L W H 540 125 75 (Dimensions in mm) L W H 565 270 180 (Dimensions in mm) L W H L W H
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- Emboss Tape (MS85RS1MTYPNF-GS-BDERE1)
2.1 Tape Dimensions (not drawn to scale) (8-pin plastic SOP)
pcs/reel(Φ254mm) pcs/inner box pcs/outer box 1500 1500 (1 pack/inner box) 9000 (6 inner boxes/outer box:Max) (Dimensions in mm) Heat proof temperature : No heat resistance. Package should not be baked by using tape and reel. 1.75 B BA A SEC.A- A SEC.B- B
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 33
2.2 IC orientation
2.3 Reel dimensions
254 100 13 13.5 17.5 Index mark
- example (User Direction of Feed) (Reel Side) (User Direction of Feed) B A Reel cutout dimensions C
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2.4 Product label indicators (examples)
Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm 100mm) Supplemental Label (20mm 100mm)] Label II:Moisture Barrier Bag (It sticks it on the Aluminum laminated bag) [MSL Label] C-3 Label Supplemental Label Perforated line (Part number) (Part number) (Control number bar code) XX/XX XXXX-XXX XXX XXXX-XXX XXX (Lot Number and quantity) (Package count) (Part number bar code) (Part number and quantity) (Control number bar code) QC PASS XXXXXXXXXXXXXX XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx (3N)1 XXXXXXXXXXXXXX XXX (Quantity) (3N)2 XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX (Part number)XXXXXXXXXXXXXX (Comment)XXXXXXXXXXXXXX (Control number )XXXXXXXXXX (LEAD FREE mark) MSL label
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 35
2.5 Dimensions for Containers
(1) Dimensions for inner box (2) Dimensions for outer box Tape width L W H 12 265 260 50 (Dimensions in mm) L W H 565 270 180 (Dimensions in mm) L W H L W H
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(2) MS85RS1MTYPN-GS-AWE1/MS85RS1MTYPN-GS-AWEWE1 1. Tray (MS85RS1MTYPN-GS-AWE1)
1.1 Tray Dimensions
DFN8 Maximum storage capacity pcs/tray pcs/inner box pcs/outer box 455 4550 9100 (Dimensions in mm) Heat proof temperature : 150 C Max
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1.2 IC orientation
1.3 Product label indicators(example)
Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm 100mm) Supplemental Label (20mm 100mm)] IC Index mark 3URGXFW IC) 7UD\\ &KDPIHUHGFRUQHU C-3 Label Supplemental Label Perforated line (Part number) (Part number) (Control number bar code) XX/XX XXXX-XXX XXX XXXX-XXX XXX (Lot Number and quantity) (Package count) (Part number bar code) (Part number and quantity) (Control number bar code) QC PASS XXXXXXXXXXXXXX XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx (3N)1 XXXXXXXXXXXXXX XXX (Quantity) (3N)2 XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX (Part number)XXXXXXXXXXXXXX (Comment)XXXXXXXXXXXXXX (Control number )XXXXXXXXXX (LEAD FREE mark)
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1.4 Dimensions for Containers
(1) Dimensions for inner box (2) Dimensions for outer box L W H 175 375 110 (Dimensions in mm) L W H 190 380 330 (Dimensions in mm) L W H L W H
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 39 2. Emboss Tape (MS85RS1MTYPN-GS-AWEWE1)
2.1 Tape Dimensions (not drawn to scale)(8-pin plastic DFN 5mm x 6mm)
pcs/reel(Φ330mm) pcs/inner box pcs/outer box 1500 1500 (1 pack/inner box) 7500 (5 inner boxes/outer box:Max) (Dimensions in mm) Heat proof temperature : No heat resistance. Package should not be baked by using tape and reel. 8.00 4.00 5.50 1.25 1.75 0.30 2.00 B BA A 6.50 12.00 5.50 SEC.A-A SEC.B-B
MS85RS1MTY(AEC-Q100 Compliant)
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330 100 13 13.5 17.5 Index mark
- example (User Direction of Feed) (Reel side) (User Direction of Feed) B A Reel cutout dimensions C
MS85RS1MTY(AEC-Q100 Compliant) DS501-00096-1v0-E 41
2.4 Product label indicators (example)
Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm 100mm) Supplemental Label (20mm 100mm)] Label II:Moisture Barrier Bag (It sticks it on the Aluminum laminated bag) [MSL Label ] C-3 Label Supplemental Label Perforated line (Part number) (Part number) (Control number bar code) XX/XX XXXX-XXX XXX XXXX-XXX XXX (Lot Number and quantity) (Package count) (Part number bar code) (Part number and quantity) (Control number bar code) QC PASS XXXXXXXXXXXXXX XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx (3N)1 XXXXXXXXXXXXXX XXX (Quantity) (3N)2 XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX (Part number)XXXXXXXXXXXXXX (Comment)XXXXXXXXXXXXXX (Control number )XXXXXXXXXX (LEAD FREE mark) MSL label
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(1) Dimensions for inner box (2) Dimensions for outer box Tape width L W H 12 350 335 35 (Dimensions in mm) L W H 384 368 225 (Dimensions in mm) L W H L W H
MS85RS1MTY(AEC-Q100 Compliant) RAMXEED LIMITED Shin-Yokohama Chuo Building, 2-100-45 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan https://ramxeed.com/ All Rights Reserved. RAMXEED LIMITED, its subsidiaries and affiliates (collectively, "RAMXEED ") reserves the right to make changes to the infor- mation contained in this document without notice. Please contact your RAMXEED sales representatives before order of RAMXEED device. Information contained in this document, such as descriptions of function and application circuit examples is presented solely for reference to examples of operations and uses of RAMXEED device. RAMXEED disclaims any and all warranties of any kind, wheth- er express or implied, related to such information, including, without limitation, quality, accuracy, performance, proper operation of the device or non-infringement. If you develop equipment or product incorporating the RAMXEED device based on such informa- tion, you must assume any responsibility or liability arising out of or in connection with such information or any use thereof. RAMX- EED assumes no responsibility or liability for any damages whatsoever arising out of or in connection with such information or any use thereof. Nothing contained in this document shall be construed as granting or conferring any right under any patents, copyrights, or any other intellectual property rights of RAMXEED or any third party by license or otherwise, express or implied. RAMXEED assumes no responsibility or liability for any infringement of any intellectual property rights or other rights of third parties resulting from or in connection with the information contained herein or use thereof. The products described in this document are designed, developed and manufactured as contemplated for general use including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured, could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear facility, aircraft flight control system, air traffic control system, mass transport control system, medical life support system and military application), or (2) for use requiring extremely high level of reliability (including, without limitation, submersible repeater and artificial satellite). RAMXEED shall not be liable for you and/or any third party for any claims or damages arising out of or in connection with above-mentioned uses of the products. Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring compliance with such laws and regulations relating to export or re-export of the products and technical information described herein. All company names, brand names and trademarks herein are property of their respective owners.