MS85RC1MTYPNF-GS-BDE1

MS85RC1MTY RAMXEED | Alldatasheet

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Copyright 2024 RAMXEED LIMITED Fujitsu Semiconductor Memory Solutions Limited has changed its name to RAMXEED Limited. RAMXEED Limited will continue to offer and support existing products while maintaining Fujitsu's part number unchanged. Memory FeRAM 1M (128 K  8) Bit I2C MS85RC1MTY(AEC-Q100 Compliant)  DESCRIPTION The MS85RC1MTY is an FeRAM (Ferroelectric Random Access Memory) chip in a configuration of 131,072 words  8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. Unlike SRAM, the MS85RC1MTY is able to retain data without using a data backup battery. The read/write endurance of the nonvolatile memory cells used for the MS85RC1MTY has improved to be at least 1013 cycles, significantly outperforming other nonvolatile memory products in the number. The MS85RC1MTY does not need a polling sequence after writing to the memory such as the case of Flash memory or E2PROM.  FEATURES

• Bit configuration : 131,072 words  8 bits
• Two-wire serial interface : Fully controllable by two ports: serial clock (SCL) and serial data (SDA).
• Operating frequency : 3.4 MHz (Max @HIGH SPEED MODE)

1 MHz (Max @FAST MODE PLUS)

• Read/write endurance : 10 13 times (  125 C)
• Data retention : 70.4 years (  85 C), 19.1 years (  105 C), 5.9 years (  125 C)
• Operating power supply voltage: 1.8 V to 3.6 V
• Low-power consumption : Operating power supply current 0.24mA (Typ @3.4 MHz) 0.4 mA (Max @3.4 MHz) Standby current 12μA (Typ), 150μA (Max) Sleep current 0.3μA (Typ), 16μA (Max)
• Operation ambient temperature range :  40 C to  125 C
• Package : 8-pin plastic SOP (150mil) 8-pin plastic DFN (5mm  6mm) RoHS compliant DS501-00095-0v1-E

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 PIN ASSIGNMENT  PIN FUNCTIONAL DESCRIPTIONS Pin Number Pin Name Functional Description 1 NC Not used. Floating or connect to VDD or VSS. 2 to 3 A1 to A2 Device Address pins The MS85RC1MTY can be connected to the same data bus up to 8 devices. Device addresses are used in order to identify each of these devices. Connect these pins to VDD pin or VSS pin externally. Only if the combination of VDD and VSS pins matches Device Address Code inputted from the SDA pin, the device operates. In the open pin state, A1 and A2 pins are internally pulled-down and r ecognized as the "L" level.

4 VSS Ground pin

5 SDA

This is an I/O pin which performs bidirectional communication for both memory address and writing/reading data. It is possible to connect multiple devices. It is an open drain output, so a pull-up resistor is required to be connected to the ex- ternal circuit.

6 SCL

This is a clock input pin for input/output serial data. Data is sampled on the ris- ing edge of the clock and output on the falling edge. 7 WP Write Protect pin When the Write Protect pin is the “H” level, the writing operation is disabled. When the Write Protect pin is the “L” level, the entire memory region can be overwritten. The reading operation is always enabled regardless of the Write Protect pin input level. The Write Protect pin is internally pulled down to VSS pin, and that is recognized as the “L” level (write enabled) when the pin is the open state.

8 VDD Supply Voltage pin

(TOP VIEW) 8-pin plastic SOP (150mil) VSS SDA VDD SCLA2 NC WP DIE PAD (TOP VIEW) 8-pin plastic DFN (5mm  6mm) VSS SDA VDD SCLA2 NC WP

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 3  BLOCK DIAGRAM  I2C (Inter-Integrated Circuit) The MS85RC1MTY has the two-wire serial interface; the I 2C bus, and operates as a slave device. The I2C bus defines communication roles of “master” and “slave” devices, with the master side holding the authority to initiate control. Furthermore, the I2C bus connection is possible where a single master device is connected to multiple slave devices in a party-line configuration. In this case, it is necessary to assign a unique device address to the slave device, the master side starts communication after specifying the slave to communicate by addresses.  I2C Interface System Configuration Example WP A1, A2 SDA SCL Row Decoder Address Counter FeRAM Array 131,072  8 Serial/Parallel Converter Column Decoder/Sense Amp/ Write Amp Control Circuit SCL SDA A2 A1 A2 A1 A2 A1 ... VDD I2C Bus Master I2C Bus MS85RC1MTY I2C Bus MS85RC1MTY I2C Bus MS85RC1MTY Pull-up Resistors Device address

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 I2C COMMUNICATION PROTOCOL The I2C bus is a two wire serial interface that uses a bidirectional data bus (SDA) and serial clock (SCL). A data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. The SDA signal should change while the SCL is the “L” level. However, as an exception, when starting and stopping communication sequence, the SDA is allowed to change while the SCL is the “H” level.

• Start Condition To start read or write operations by the I2C bus, change the SDA input from the “H” level to the “L” level while the SCL input is in the “H” level.
• Stop Condition To stop the I2C bus communication, change the SDA input from the “L” level to the “H” level while the SCL input is in the “H” level. In the reading operation, inputting the stop condition finishes reading and enters the standby state. In the writing operation, inputting the stop condition finishes inputting the rewrite data and enters the standby state.  Start Condition, Stop Condition Note : At the write operation, the FeRAM device does not need the programming wait time (t WC) after issuing the Stop Condition.  ACKNOWLEDGE (ACK) In the I2C bus, serial data including memory address or memory information is sent and received in units of 8 bits. The acknowledge signal indicates that every 8 bits of the data is successfully sent and received. The receiver side usually outputs the “L” level every time on the 9th SCL clock after each 8 bits are successfully transmitted and received. On the transmitter side, the bus is temporarily released to Hi-Z every time on this 9th clock to allow the acknowledge signal to be received and checked. During this Hi-Z released period, the receiver side pulls the SDA line down to indicate the “L” level that the previous 8 bits communication is successfully received. In case the slave side receives Stop condition before sending or receiving the ACK “L” level, the slave side stops the operation and enters to the standby state. On the other hand, the slave side releases the bus state after sending or receiving the NACK “H” level. The master side generates Stop condition or Start condition in this released bus state.  Acknowledge timing overview diagram SCL SDA Start Stop H or L SCL 123 89 SDA Start ACK The transmitter side should always release SDA on the 9th bit. At this time, the receiver side outputs a pull-down if the previous 8 bits data are received correctly (ACK response).

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 5  DEVICE ADDRESS WORD (Slave address) Following the start condition, the master inputs the 8 bits device address word to start I2C communication. The device address word (8 bits) consists of a device Type code (4 bits), device address code (2 bits), MSB(1bit) and a read/write code (1 bit).

• Device Type Code (4 bits) The upper 4 bits of the device address word are a device type code that identifies the device type, and are fixed at “1010” for the MS85RC1MTY .
• Device Address Code (2 bits) Following the device type code, the 2 bits of the device address code are input in order of A2 and A1. The device address code identifies one device from up to four devices connected to the bus. Each MS85RC1MTY is given a unique 2 bits code on the device address pin (external hardware pin A2 and A1). The slave only responds if the received device address code is equal to this unique 3 bits code.
• The most significant address(1 bit) The seventh bit of device address word is A16(1 bit) that is the most significant address.
• Read/Write Code (1 bit) The 8th bit of the device address word is the R/W (read/write) code. When the R/W code is “0”, a write operation is enabled, and the R/W code is “1”, a read operation is enabled for the MS85RC1MTY . It turns to a stand-by state if the device code is not “1010” or device address code does not equal to pin A2, A1 and A0.  Device Address Word Start 1 2 34567891 2 SCL SDA ACK A S S 10 10 A2 A1 A16 R/W A Access from master Access from slave Devide Code Start Condition ACK(SDA is the “L” level) Devide Address Code Read/Write Code The most significant address

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 DATA STRUCTURE In the I2C bus, the acknowledge “L” level is output on the 9th bit by a slave, after the 8 bits of the device address word following the start condition are input by a master. After confirming the acknowledge response by the master, the master outputs remained 8 bits  2 memory address to the slave. When the each memory address input ends, the slave again outputs the acknowledge “L” level. After this operation, the I/O data follows in units of 8 bits, with the acknowledge “L” level output after every 8 bits. It is determined by the R/W code whether the data line is driven by the master or the slave. However, the clock line shall be driven by the master. For a write operation, the slave will accept 8 bits from the master, then send an acknowledge. If the master detects the acknowledge, the master will transfer the next 8 bits. For a read operation, the slave will place 8 bits on the data line, then wait for an acknowledge from the master.  FeRAM ACKNOWLEDGE -- POLLING NOT REQUIRED The MS85RC1MTY performs the high speed write operations, so any waiting time for an ACK polling* does not occur. *: In E 2PROM, the Acknowledge Polling is performed as a progress check whether rewriting is executed or not. It is normal to judge by the 9th bit of Acknowledge whether rewriting is performed or not after inputting the start condition and then the device address word (8 bits) during rewriting.  WRITE PROTECT (WP) The entire memory array can be write protected using the Write Protect pin. When the Write Protect pin is set to the “H” level, the entire memory array will be write protected. When the Write Protect pin is the “L” level, the entire memory array will be rewritten. Reading is allowed regardless of the WP pin's “H” level or “L” level. Note : The Write Protect pin is pulled down internally to the VSS pin, therefore if the Write Protect pin is open, the pin status is detected as the “L” level (write enabled).

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 7  COMMAND

• Byte Write If the device address word (R/W “0” input) is sent following the start condition, the slave responds with an ACK. After this ACK, write addresses and data are sent in the same way, and the write ends by generating a stop condition at the end.
• Page Write If additional 8 bits are continuously sent after the same command (except stop condition) as Byte Write, a page write is performed. The memory address rolls over to first memory address (0 0000H) at the end of the address. Therefore, if more than 128K bytes are sent, the data is overwritten in order starting from the start of the memory address that was written first. Because FeRAM performs the high-speed write operations, the data will be written to FeRAM right after the ACK response finished. Note: It is not necessary to take a period for internal write operation cycles from the buffer to the memory after the stop condition is generated. LSB A S P MSB XXXXXXXX XXXXXXXX S A2 A1A16 A A A A PAddress High 8bits Address Low 8bits Write Data 8bits01010 X Access from master Access from slave Start Condition ACK(SDA is the “L” level) Stop Condition A S P S A2 A1 A A A A A PAddress High 8bits Address Low 8bits Write Data 8bits Write Data ...01010 A16 Access from master Access from slave Start Condition ACK(SDA is the “L” level) Stop Condition

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• Current Address Read When the previous write or read operation finishes successfully up to the stop condition, the memory address accessed last time is remain in memory address buffer(17bits). As it is, then send the command without turning off the power, the memory address "n", total 17 bits consist of the 1 bit of the top memory address from the Device Address Word input and lower 16 bits of memory address buffer, is read from the address +1". If the memory address “n” is last address, the address counter will roll over to (0000 H). The current address in memory address buffer is undefined immediately after the power is turned on.
• Random Read The one byte of data from the memory address saved in the memory address buffer can be read out synchronously to SCL by specifying the address in the same way as for a write, and then issuing another start condition and sending the Device Address Word (R/W “1” input). The top address input at second time need to same value as top address inputed first time. If input the different value at first time and second time, the second value is reflected as the address to access. The final NACK (SDA is the “H” level) is issued by the receiver that receives the data. In this case, this bit is issued by the master side. A S P N S A2 A1 A N P Read Data 8bits11010 A16 Access from master Access from slave Start Condition ACK(SDA is the “L” level) Stop Condition NACK(SDA is the “H” level) Address n+1 A S P N S A2 A1 A A A P Address High 8bits Address Low 8bits01010 S A2 A1 A 11010 Read Data 8bits NA16 A16 Access from master Access from slave Start Condition ACK(SDA is the “L” level) Stop Condition NACK(SDA is the “H” level)

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• Sequential Read Data can be received continuously following the Device address word (R/W “1” input) after specifying the address in the same way as for Random Read. If the read reaches the end of address, the internal read address automatically rolls over to first memory address (0 0000H) and keeps reading.
• High Speed Mode MS85RC1MTY supports High Speed mode up to 3.4 MHz. By sending an entry command (0000 1XXX) after start condition from the master side, it informs to the slave that the data transmission with High Speed mode will start. Since there is no slave side which is allowed to respond to this entry command, NACK response continues from the slave side. After the master side recognizes this NACK response, the master side changes its state to High Speed mode and enables the bidirectional communication up to 3.4 MHz. By sending Stop condition, it exits out of the state in High Speed communication. A P N AA A N PRead Data 8bits Read Data 8bits Read Data Access from master Access from slave Stop Condition ACK(SDA is the “L” level) NACK(SDA is the “H” level) A S P N S A2 A1 A N P Read Data 8bits11010S1 X N X0000 X AA A N PRead Data 8bits Read Data 8bits Read Data S A2 A1 A A A A P Address High 8bits Address Low 8bits Write Data 8bits01010S1 X N X0000 X S A2 A1 A A A A A PAddress High 8bits Address Low 8bits Write Data 8bits Write Data0 ...1010S1 X N X0000 X S A2 A1 A A A P Address High 8bits Address Low 8bits01010 S A2 A1 A 11010 Read Data 8bits NS1 X N X0000 X S A2 A1 A A A Address High 8bits Address Low 8bits01010 S A2 A1 A 11010 Read Data 8bits AS1 X N X0000 X ... A N A16 A16 A16 A16 A16 A16 A16 Access from slave Start Condition Stop Condition ACK(SDA is the “L” level) NACK(SDA is the “H” level) Byte Write @High Speed Mode Page Write @High Speed Mode Current Address Read @High Speed Mode Random Address Read @High Speed Mode Sequential Read @High Speed Mode High Speed ModeStandard Mode Fast Mode Fast Mode Plus Access from master

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• Sleep Mode MS85RC1MTY provides Sleep mode which reduces less current consumption than Standby mode, by stooping the internal regulator circuits. Following sequences enable the Sleep mode transition. <Transition to Sleep mode> a) The master sends start condition followed by F8h. b) After ACK response from slave, the master sends the device address word. In this device address word, Read/Write code is Don't care. c) After ACK response from slave, the master re-sends the start condition followed by 86h. d) The slave moves to Sleep mode after ACK response to the master. Even if the MS85RC1MTY stays in the Sleep mode, SDA and SCL signals are monitored. Following se - quences enable the transition to Standby mode after recovery time (tREC) of internal regulator circuits. <Exit from Sleep mode> a) The master sends start condition followed by device address word. In this device address word, Read/Write code is Don't care. b) At the rising edge of 9th clock from start condition, an internal regulator starts to operate its recovery sequence. c) After the recovery time (tREC) passed, standby mode enabled. After returning to Standby mode, reading and writing are enabled by sending each command starts with start condition. S11111000 1010 A 2 A 1 A S1000011A 0R/W AP A S P X Access from slave Start Condition Stop Condition ACK(SDA is the “L” level) Access from master 1 0 1 0 A2 A1 XS R/W A S 1 0 1 0 A2 A1 AS R/W ͐XA 16 Access from slave Start Condition ACK(SDA is the “L” level) Access from master Recovery operation Start recovery operation

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• Device ID The Device ID command reads fixed Device ID. The size of Device ID is 3 bytes and consists of manufacturer ID and product ID. The Device ID is read-only and can be read out by following sequences. a) The master sends the Reserved Slave ID F8H after the START condition. b) The master sends the device address word after the ACK response from the slave. In this device address word, R/W code is “Don't care”. c) The master re-sends the START condition followed by the Reserved Slave ID F9H after the ACK response from the slave. d) The master read out the Device ID succeedingly in order of Data Byte 1st / 2nd / 3rd after the ACK response from the slave. e) The master responds the NACK (SDA is the “H” level) after reading 3 bytes of the Device ID. In case the master respond the ACK after reading 3 bytes of the Device ID, the master re-reading the Device ID from the 1st byte. 1 1 1 0 9876543210 1 1 1 0 9876543210 000000001010011110011000 Density = 7H Proprietary use Manufacture ID = 00AH Product ID = 598H Data Byte 1st Data Byte 2nd Data Byte 3rd Reserved Slave ID (F8H) Reserved Slave ID (F9H) A1010 A2 A1 R/W ASS A Data Byte 1st Data Byte 2nd Data Byte 3rdAAN P S P A N X Access from master Access from slave Stop Condition ACK (SDA is the "L" level) NACK (SDA is the "H" level) Start Condition

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 SOFTWARE RESET SEQUENCE OR COMMAND RETRY In case the malfunction has occurred after power on, the master side stopped the I2C communication during processing, or unexpected malfunction has occurred, execute the following (1) software recovery sequence just before each command, or (2) retry command just after failure of each command. (1) Software Reset Sequence Since the slave side may be outputting “L” level, do not force to drive “H” level, when the master side drives the SDA port. This is for preventing a bus conflict. The additional hardware is not necessary for this software reset sequence. (2) Command Retry Command retry is useful to recover from failure response during I2C communication. SCL SDA 9 set of “Start Conditions and one “1” data” Send “Start Condition and one data “1””. Repeat these 9 times just before Write or Read command. Hi-Z state by pull up Resistor

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 13  ABSOLUTE MAXIMUM RATINGS *: These parameters are based on the condition that VSS is 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.  RECOMMENDED OPERATING CONDITIONS *1: These parameters are based on the condition that VSS is 0 V. *2: Ambient temperature when only this device is working. Please consider it to be the almost same as the package surface temperature. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Parameter Symbol Rating Unit Min Max Power supply voltage* VDD  0.5 +4.0 V Input voltage* VIN  0.5 V DD  0.5 (  4.0) V Output voltage* VOUT  0.5 V DD  0.5 (  4.0) V Operation ambient temperature T A  40  125 C Storage temperature Tstg  55  125 C Parameter Symbol Value Unit Min Typ Max Power supply voltage*1 VDD 1.8 3.3 3.6 V Operation ambient temperature*2 TA  40   125 C

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 ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) *1: Applicable pin: SCL,SDA *2: Applicable pin: SDA Parameter Symbol Condition Value UnitMin Typ (TA=25 C) Max Input leakage current*1 |ILI| V IN  0 V to VDD   1 A Output leakage current*2 |ILO| V OUT  0 V to VDD   1 A Operating power supply current IDD SCL  0.1 MHz    mA SCL  1 MHz  0.09 0.25 mA SCL  3.4 MHz  0.24 0.4 mA Standby current ISB SCL, SDA  VDD A1, A2, WP  0 V or Open Under Stop Condition  12 150 A Sleep current IZZ SCL, SDA  VDD A1, A2, WP  0 V 0.3 16 A “H” level input voltage V IH VDD  1.8 V to 3.6 V V DD  0.8  VDD +0.5 V “L” level input voltage V IL VDD  1.8 V to 3.6 V -0.5  VDD  0.2 V “L” level output voltage V OL IOL  3 mA   0.4 V Input resistance for WP, A1 and A2 pins RIN  11 33 125 k

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 15 2. AC Characteristics AC characteristics were measured under the following measurement conditions. Power supply voltage : 1.8 V to 3.6 V Operation ambient temperature :  40 C to  125 C Input voltage magnitude : V DD  0.2 to VDD  0.8 Input rising time : 5 ns Input falling time : 5 ns Input judge level : VDD/2 Output judge level : VDD/2 Output load capacitance : 100 pF Parameter Symbol Value UnitSTANDARD MODE FAST MODE FAST MODE PLUS HIGH SPEED MODE Min Max Min Max Min Max Min Max SCL clock frequency FSCL 0 100 0 400 0 1000 0 3400 kHz Clock high time T HIGH 4000  600  260  60  ns Clock low time TLOW 4700  1300  500  160  ns SCL/SDA rising time T r  1000  300  300  80 ns SCL/SDA falling time T f  300  300  120  80 ns Start condition hold T HD:STA 4000  600  250  160  ns Start condition setup T SU:STA 4700  600  250  160  ns SDA input hold T HD:DAT 0  0  0  0  ns SDA input setup T SU:DAT 250  100  50  10  ns SDA output hold T DH:DAT 0  0  0  0  ns Stop condition setup T SU:STO 4000  600  250  160  ns SDA output access af- ter SCL falling TAA  3000  900  450  130 ns Pre-charge time T BUF 4700  1300  500  300  ns Noise suppression time (SCL and SDA) TSP  50  50  50  10 ns

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1. AC Timing Definitions 4. Pin Capacitance 5. AC Test Load Circuit Parameter Symbol Conditions Value UnitMin Typ Max I/O capacitance CI/O VDD  3.3 V, f  1 MHz, TA   25 C   8 pF Input capacitance CIN   8 pF Start StartStop Stop Valid SCL SDA SCL SDA SCL SDA VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIH VIH TSU:DAT TSU:STA THD:STA THIGH TLOW TDH:DAT 1/FSCL TSU:STO THD:DAT VIH VIH VIH VIL VIL VIL VIL VIL VIL VIL VIL TBUF TfTr TfTr TAA Tsp VDD 100 pF Output 1.1 kΩ

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 17  POWER ON/OFF SEQUENCE When applying relatively short term VDD pulse whose peak is more than 1.7V, it is required to set falling time, tf more than 0.4ms/V. (In case VDD rises over 1.7V and falls just after that, if this term is short, device may lose its function.). If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed.  FeRAM CHARACTERISTICS *1 : The value for Read/Write endurance apply to the total number of read and write operations per row in FeRAM. This is because FeRAM needs writing operation after each reading operations. *2 : Minimum values define retention time of the first reading/writing data right after shipment. *3: Under evaluation for more than 5.9 years(+125 C). These values are calculated by qualification results. Parameter Symbol Value Unit Min Max SDA, SCL level hold time during power down tpd 85  ns SDA, SCL level hold time during power up tpu 450  s Power supply rising time tr 0.05  ms/V Power supply falling time tf 0.1  ms/V Internal regulator recovery time tREC  450 s Item Min Max Unit Parameter Read/Write Endurance*1 1013  Times Operation Ambient Temperature T A   125 C Data Retention*2 5.9*3  Years Operation Ambient Temperature TA   125 C 19.1  Operation Ambient Temperature TA   105 C 70.4  Operation Ambient Temperature TA   85 C 0 V SDA, SCL > VDD × 0.8 * SDA, SCL > VDD × 0.8 * tpd tputrtf VIL (Max) VIH (Min) VDD (Min) VDD SDA, SCL : Don't careSDA, SCL SDA, SCL 0 V VIL (Max) VIH (Min) VDD (Min) VDD * : SDA, SCL (Max) < VDD  0.5 V

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 NOTE ON USE

• We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed.
• During the access period from the start condition to the stop condition, keep the level of WP , A0, A1 and A2 pins to the “H” level or the “L” level.  ESD AND LATCH-UP  REFLOW CONDITIONS AND FLOOR LIFE [ JEDEC MSL ] : Moisture Sensitivity Level 3 (IPC/JEDEC J-STD-020E)  CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES This product complies with the regulations of REACH Regulations, EU RoHS Directive and China RoHS. Test DUT Value ESD HBM (Human Body Model) JEDEC JS001 compliant MS85RC1MTYPNF-GS-BDE1 MS85RC1MTYPNF-GS-BDERE1 MS85RC1MTYPN-GS-AWE1 MS85RC1MTYPN-GS-AWEWE1  |2000 V| ESD CDM (Charged Device Model) JEDEC JS002 compliant  |1000 V| Latch-Up (I-test) JESD78 compliant  |80mA| Latch-Up (Vsupply overvoltage test) JESD78 compliant  5.4V

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 19  ORDERING INFORMATION *: Please contact our sales office about minimum shipping quantity. Part number Package Shipping form Minimum shipping quantity MS85RC1MTYPNF-GS-BDE1 8-pin, plastic SOP Tube * MS85RC1MTYPNF-GS-BDERE1 8-pin, plastic SOP Embossed Carrier tape 1500 MS85RC1MTYPN-GS-AWE1 8-pin, plastic DFN Tray * MS85RC1MTYPN-GS-AWEWE1 8-pin, plastic DFN Embossed Carrier tape 1500

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8-pin plastic SOP(150mil) Lead pitch 1.27m m Lead shape Gullwing Sealing method Plastic mold Mounting height 1.75mm MAX. 8-pin plastic SOP Dimension in mm㸸 (1.40) Details of “F”part 1.75 MAX. “F” Note *: These dimension do not include resin protrution. Pins width do not include tie bar cutting remaindar. 0.10 S S Package width x Package length 3.90mm x 4.90mm 0.05 MIN. 0.40 MIN. 㹼 1pin 4pin 5pin8pin 3.90s* 0.41±0.101.27 s  PACKAGE DIMENSION (1) MS85RC1MTYPNF-GS-BDE1/MS85RC1MTYPNF-GS-BDERE1

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 21 0.05 8-pin plastic DFN Lead pitch 1.27 mm Package width x Package length 5.00 mm × 6.00 mm Sealing method Plastic mold Mounting height 0.90 mm MAX 8-pin plastic DFN (LCC-8P-M05) 5.00±0.10 INDEX AREA 6.00±0.10 0.40±0.10 4.10±0.10 1.27 BSC. 0.90 MAX. Dimensions in mm. Note: The values in parentheses are reference values. 4.00±0.100.60±0.10 C0.30 0.05 MAX. 0.17 WR0.25 1PIN CORNER (2) MS85RC1MTYPN-GS-AWE1/MS85RC1MTYPN-GS-AWEWE1

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 MARKING (Example) (1) MS85RC1MTYPNF-GS-BDE1/MS85RC1MTYPNF-GS-BDERE1 (2) MS85RC1MTYPN-GS-AWE1/MS85RC1MTYPN-GS-AWEWE1 [MS85RC1MTYPNF-GS-BDE1] [MS85RC1MTYPNF-GS-BDERE1] C1MTY: Product name A2300 : A(CS code) + 2300(Year and Week code) 701 : Trace code C1MTY A2300 701 [MS85RC1MTYPN-GS-AWE1] [MS85RC1MTYPN-GS-AWEWE1] MS85RC1MTY: Product name AE1 : A(CS code) + E1(Lead free code) 2300R00：2300(Year and Week code) + R00(Trace code) MS85RC1MTY AE1 2300R00

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 23  PACKING INFORMATION (1) MS85RC1MTYPNF-GS-BDE1/MS85RC1MTYPNF-GS-BDERE1 1. Tube (MS85RC1MTYPNF-GS-BDE1)

1.1 Tube Dimensions

• Tube/stopper shape (example)
• Tube cross-sections and Maximum quantity
• Direction of index in tube Maximum quantity pcs/tube(500mm) pcs/inner box pcs/outer box No heat resistance. Package should not be baked by using tube. 85 4,250 17,000 (Dimensions in mm) Stopper Tube 9.5 Index mark

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1.2 Product label indicators (example)

Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm  100mm) Supplemental Label (20mm  100mm)] C-3 Label Supplemental Label Perforated line (Part number) (Part number) (Control number bar code) XX/XX XXXX-XXX XXX XXXX-XXX XXX (Lot Number and quantity) (Package count) (Part number bar code) (Part number and quantity) (Control number bar code) QC PASS XXXXXXXXXXXXXX XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx (3N)1 XXXXXXXXXXXXXX XXX (Quantity) (3N)2 XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX (Part number)XXXXXXXXXXXXXX (Comment)XXXXXXXXXXXXXX (Control number )XXXXXXXXXX (LEAD FREE mark)

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 25

1.3 Dimensions for Containers

(1) Dimensions for inner box (2) Dimensions for outer box L W H 540 125 75 (Dimensions in mm) L W H 565 270 180 (Dimensions in mm) L W H L W H

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1. Emboss Tape (MS85RC1MTYPNF-GS-BDERE1)

2.1 Tape Dimensions (not drawn to scale) (8-pin plastic SOP)

pcs/reel(Φ254mm) pcs/inner box pcs/outer box 1500 1500 (1 pack/inner box) 9000 (6 inner boxes/outer box:Max) (Dimensions in mm) Heat proof temperature : No heat resistance. Package should not be baked by using tape and reel. 1.75 B BA A SEC.A- A SEC.B- B

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 27

2.2 IC orientation

2.3 Reel dimensions

254 100 13 13.5 17.5 Index mark

• example (User Direction of Feed) (Reel Side) (User Direction of Feed) B A Reel cutout dimensions C

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2.4 Product label indicators (examples)

Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm  100mm) Supplemental Label (20mm  100mm)] Label II:Moisture Barrier Bag (It sticks it on the Aluminum laminated bag) [MSL Label ] C-3 Label Supplemental Label Perforated line (Part number) (Part number) (Control number bar code) XX/XX XXXX-XXX XXX XXXX-XXX XXX (Lot Number and quantity) (Package count) (Part number bar code) (Part number and quantity) (Control number bar code) QC PASS XXXXXXXXXXXXXX XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx (3N)1 XXXXXXXXXXXXXX XXX (Quantity) (3N)2 XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX (Part number)XXXXXXXXXXXXXX (Comment)XXXXXXXXXXXXXX (Control number )XXXXXXXXXX (LEAD FREE mark) MSL label

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 29

2.5 Dimensions for Containers

(1) Dimensions for inner box (2) Dimensions for outer box Tape width L W H 12 265 260 50 (Dimensions in mm) L W H 565 270 180 (Dimensions in mm) L W H L W H

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(2) MS85RC1MTYPN-GS-AWE1/MS85RC1MTYPN-GS-AWEWE1 1. Tray (MS85RC1MTYPN-GS-AWE1)

1.1 Tray Dimensions

DFN8 Maximum storage capacity pcs/tray pcs/inner box pcs/outer box 455 4550 9100 (Dimensions in mm) Heat proof temperature : 150 C Max

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 31

1.2 IC orientation

1.3 Product label indicators(example)

Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm  100mm) Supplemental Label (20mm  100mm)] IC Index mark 3URGXFW IC) 7UD\\ &KDPIHUHGFRUQHU C-3 Label Supplemental Label Perforated line (Part number) (Part number) (Control number bar code) XX/XX XXXX-XXX XXX XXXX-XXX XXX (Lot Number and quantity) (Package count) (Part number bar code) (Part number and quantity) (Control number bar code) QC PASS XXXXXXXXXXXXXX XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx (3N)1 XXXXXXXXXXXXXX XXX (Quantity) (3N)2 XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX (Part number)XXXXXXXXXXXXXX (Comment)XXXXXXXXXXXXXX (Control number )XXXXXXXXXX (LEAD FREE mark)

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1.4 Dimensions for Containers

(1) Dimensions for inner box (2) Dimensions for outer box L W H 175 375 110 (Dimensions in mm) L W H 190 380 330 (Dimensions in mm) L W H L W H

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 33 2. 1. Emboss Tape (MS85RC1MTYPN-GS-AWEWE1)

2.1 Tape Dimensions (not drawn to scale)(8-pin plastic DFN 5mm  6mm)

pcs/reel(Φ330mm) pcs/inner box pcs/outer box 1500 1500 (1 pack/inner box) 7500 (5 inner boxes/outer box:Max) (Dimensions in mm) Heat proof temperature : No heat resistance. Package should not be baked by using tape and reel. 8.00 4.00 5.50 1.25 1.75 0.30 2.00 B BA A 6.50 12.00 5.50 SEC.A-A SEC.B-B

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330 100 13 13.5 17.5 Index mark

• example (User Direction of Feed) (Reel side) (User Direction of Feed) B A Reel cutout dimensions C

MS85RC1MTY(AEC-Q100 Compliant) DS501-00095-0v1-E 35

2.4 Product label indicators (example)

Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm  100mm) Supplemental Label (20mm  100mm)] Label II:Moisture Barrier Bag (It sticks it on the Aluminum laminated bag) [MSL Label ] C-3 Label Supplemental Label Perforated line (Part number) (Part number) (Control number bar code) XX/XX XXXX-XXX XXX XXXX-XXX XXX (Lot Number and quantity) (Package count) (Part number bar code) (Part number and quantity) (Control number bar code) QC PASS XXXXXXXXXXXXXX XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx (3N)1 XXXXXXXXXXXXXX XXX (Quantity) (3N)2 XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX (Part number)XXXXXXXXXXXXXX (Comment)XXXXXXXXXXXXXX (Control number )XXXXXXXXXX (LEAD FREE mark) MSL label

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(1) Dimensions for inner box (2) Dimensions for outer box Tape width L W H 12 350 335 35 (Dimensions in mm) L W H 384 368 225 (Dimensions in mm) L W H L W H

MS85RC1MTY(AEC-Q100 Compliant) RAMXEED LIMITED Shin-Yokohama Chuo Building, 2-100-45 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan https://ramxeed.com/ All Rights Reserved. RAMXEED LIMITED, its subsidiaries and affiliates (collectively, "RAMXEED ") reserves the right to make changes to the infor- mation contained in this document without notice. Please contact your RAMXEED sales representatives before order of RAMXEED device. Information contained in this document, such as descriptions of function and application circuit examples is presented solely for reference to examples of operations and uses of RAMXEED device. RAMXEED disclaims any and all warranties of any kind, wheth- er express or implied, related to such information, including, without limitation, quality, accuracy, performance, proper operation of the device or non-infringement. If you develop equipment or product incorporating the RAMXEED device based on such informa- tion, you must assume any responsibility or liability arising out of or in connection with such information or any use thereof. RAMX- EED assumes no responsibility or liability for any damages whatsoever arising out of or in connection with such information or any use thereof. Nothing contained in this document shall be construed as granting or conferring any right under any patents, copyrights, or any other intellectual property rights of RAMXEED or any third party by license or otherwise, express or implied. RAMXEED assumes no responsibility or liability for any infringement of any intellectual property rights or other rights of third parties resulting from or in connection with the information contained herein or use thereof. The products described in this document are designed, developed and manufactured as contemplated for general use including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured, could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear facility, aircraft flight control system, air traffic control system, mass transport control system, medical life support system and military application), or (2) for use requiring extremely high level of reliability (including, without limitation, submersible repeater and artificial satellite). RAMXEED shall not be liable for you and/or any third party for any claims or damages arising out of or in connection with above-mentioned uses of the products. Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring compliance with such laws and regulations relating to export or re-export of the products and technical information described herein. All company names, brand names and trademarks herein are property of their respective owners.