MB85R256F RAMXEED | Alldatasheet
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Copyright 2024 RAMXEED LIMITED Fujitsu Semiconductor Memory Solutions Limited has changed its name to RAMXEED Limited. RAMXEED Limited will continue to offer and support existing products while maintaining Fujitsu's part number unchanged. Memory FeRAM
256 K (32 K 8) Bit
DESCRIPTIONS The MB85R256F is an FeRAM (Ferroelectric Random Access Memory) chip in a configuration of 32,768 words 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. The MB85R256F is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85R256F can be used for 1012 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. The MB85R256F uses a pseudo - SRAM interface. FEATURES
- Bit configuration : 32,768 words 8 bits
- Read/write endurance : 10 12 times / byte
- Data retention : 10 years ( 85 C), 95 years ( 55 C), over 200 years ( 35 C)
- Operating power supply voltage : 2.7 V to 3.6 V
- Low power consumption : Operating power supply current 5 mA (Typ) Standby current 5 A (Typ)
- Operation ambient temperature range: 40 C to 85 C
- Package : 28-pin plastic TSOP RoHS compliant DS501-00011-9v1-E
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PIN ASSIGNMENTS PIN FUNCTIONAL DESCRIPTIONS Pin no. Pin name Functional description 1 to 10, 21, 23 to 26 A0 to A14 Address input pins 11 to 13, 15 to 19 I/O0 to I/O7 Data input/output pins
20 CE Chip enable input pin
27 WE Write Enable input pin
22 OE Output enable input pin
28 VDD Supply Voltage pin
14 GND Ground pin
A A12 A3 A2 I/O0 I/O1 I/O2 GND VDD A13 A11 A10 CE I/O I/O6 I/O5 I/O4 I/O3 WE OE (28-pin plastic TSOP)
BLOCK DIAGRAM FUNCTION LIST H: High level, L: Low level, : can be either H, L, or , Hi-Z: High impedance, : Latch address at falling edge Operation mode CE WE OE I/O0 to I/O7 Power supply current Standby precharge H Hi-Z Standby (ISB) L L H H Latch address L H L L H Write L L H Data input Operation (IDD) Read L H L Data output A10 to A14 A0 to A7 A8, A9 CE WE OE I/O0-I/O7 A0 to A14 Row decoder Address latch FeRAM array: 32,768 8 Block decoder Column decoder Control logic I/O latch bus driver Pseudo-SRAM interface logic circuit I/O0 to I/O7
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ABSOLUTE MAXIMUM RANGES * : These parameters are based on the condition that VSS is 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING CONDITIONS *1 : These parameters are based on the condition that VSS is 0 V. *2 : Ambient temperature when only this device is working. Please consider it to be the almost same as the package surface temperature. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Parameter Symbol Rating Unit Min Max Power supply voltage* VDD 0.5 4.0 V Input voltage* VIN 0.5 VDD 0.5 V Output voltage* VOUT 0.5 VDD 0.5 V Operation ambient temperature T A 40 85 C Storage temperature Tstg 55 125 C Parameter Symbol Value Unit Min Typ Max Power supply voltage*1 VDD 2.7 3.3 3.6 V Operation ambient temperature*2 TA 40 85 C
ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) *1: During the measurement of IDD, the Address and Data In were taken to only change once per active cycle. Iout: output current *2: All pins other than setting pins shall be input at the CMOS level voltages such as H VDD, L 0 V. Parameter Symbol Conditions Value Unit Min Typ Max Input leakage current | I LI | V IN 0 V to VDD 10 A Output leakage current | ILO | VOUT 0 V to VDD, CE VIH or OE VIH 10 A Operating power supply current*1 IDD CE 0.2 V, Other inputs VDD 0.2 V/0.2 V, tRC (Min), Iout 0 mA 5 10 mA Standby current*2 ISB CE, WE, OE VDD 5 50 A High level input voltage V IH VDD = 2.7 V to 3.6 V VDD 0.8 VDD 0.5 ( 4.0) V Low level input voltage V IL VDD = 2.7 V to 3.6 V 0.5 0.6 V High level output voltage VOH IOH 2.0 mA VDD 0.8 V Low level output voltage VOL IOL 2.0 mA 0.4 V
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- AC Characteristics AC Characteristics Test Condition Power supply voltage : 2.7 V to 3.6 V Operation ambient temperature: 40 C to 85 C Input voltage amplitude : 0.3 V to 2.7 V Input rising time : 10 ns Input falling time : 10 ns Input evaluation level : V DD/2 Output evaluation level : V DD/2 Output Load Capacitance: 100 pF (1) Read cycle (2) Write cycle Parameter Symbol Value Unit Min Max Read cycle time tRC 150 ns CE active time tCA 70 500 Read pulse width tRP 70 500 Precharge time tPC 80 Address setup time tAS 0 Address hold time tAH 25 CE access time tCE 70 OE access time tOE 70 CE output floating time tHZ 25 OE output floating time tOHZ 25 Parameter Symbol Value Unit Min Max Write cycle time tWC 150 ns CE active time tCA 70 500 Write pulse width tWP 70 500 Precharge time tPC 80 Address setup time tAS 0 Address hold time tAH 25 Data setup time tDS 50 Data hold time tDH 0
- Pin Capacitance Parameter Symbol Conditions Value Unit Min Typ Max Input capacitance C IN VDD VIN VOUT 0 V, f 1 MHz, TA 25 C 10 pF Output capacitance C OUT 10 pF
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TIMING DIAGRAM 1. Read cycle (CE Control) 2. Read cycle (OE Control) CE OE I/O0 to I/O7 A0 to A14 WE Valid Valid : Don't care Valid High-Z High-ZValid tRC tCA tAS tAH tPC tCE tHZ tPC tAS tAH “H” level CE OE I/O0 to I/O7 A0 to A14 WE Valid Valid : Don't care Valid High-Z High-ZValid tAS tAH tOE tOHZ tPC tPC tAS tAH tRP tRC “H” level
- Write cycle (CE Control) 4. Write cycle (WE Control) CE OE A0 to A14 WE Data In Valid Valid : Don't care Valid Valid tWC tCA tAS tAH tDS tDH tPCtPC tAS tAH tDS tDH “H” level CE OE A0 to A14 WE Data In Valid Valid : Don't care Valid Valid tAS tAH tDS tDH tPC tPC tAS tAH tDS tDH tWP tWC “H” level
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POWER ON/OFF SEQUENCE If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed. FeRAM CHARACTERISTICS *1 : Total number of reading and writing defines the minimum value of endurance, as an FeRAM memory operates with destructive readout mechanism. *2 : Minimum values define retention time of the first reading/writing data right after shipment, and these values are calculated by qualification results. NOTES ON USE We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed. Parameter Symbol Value Unit Min Typ Max CE level hold time at power OFF tpd 80 ns CE level hold time at power ON tpu 80 ns Power supply rising time tr 0.05 200 ms Item Min Max Unit Parameter Read/Write Endurance*1 1012 Times/byte Operation Ambient Temperature TA 85 C Data Retention*2 10 Years Operation Ambient Temperature TA 85 C 95 Operation Ambient Temperature TA 55 C 200 Operation Ambient Temperature TA 35 C tpd tputr CE > VDD × 0.8*CE : Don't careCE > VDD × 0.8* CE CE VDD 2.7 V VIH (Min) 1.0 V VIL (Max) GND VDD 2.7 V VIH (Min) 1.0 V VIL (Max) GND * : CE (Max) < VDD 0.5 V
ESD AND LATCH-UP
- Current method of Latch-Up Resistance Test Note : The voltage V IN is increased gradually and the current IIN of 300 mA at maximum shall flow. Confirm the latch up does not occur under IIN 300 mA. In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be increased to the level that meets the specific requirement. Test DUT Value ESD HBM (Human Body Model) JESD22-A114 compliant MB85R256FPFCN-G-BNDE1 |2000 V| ESD MM (Machine Model) JESD22-A115 compliant |200 V| ESD CDM (Charged Device Model) JESD22-C101 compliant |1000 V| Latch-Up (I-test) JESD78 compliant Latch-Up (Vsupply overvoltage test) JESD78 compliant Latch-Up (Current Method) Proprietary method |300 mA| Latch-Up (C-V Method) Proprietary method A VDD VSS DUT V IIN VIN Test terminal Protection Resistor VDD (Max.Rating) Reference terminal
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- C-V method of Latch-Up Resistance Test Note : Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is considered as one cycle. Repeat this process 5 times. However, if the latch-up condition occurs before completing 5 times, this test must be stopped immediately. REFLOW CONDITIONS AND FLOOR LIFE [ JEDEC MSL ] : Moisture Sensitivity Level 3 (IPC/JEDEC J-STD-020E) CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES This product complies with the regulations of REACH Regulations, EU RoHS Directive and China RoHS. VDD VSS DUT VIN SW 1 2 C 200pF V A Test terminal Protection Resistor VDD (Max.Rating) Reference terminal
ORDERING INFORMATION *: Please contact our sales office about minimum shipping quantity. Part number Package Shipping form Minimum shipping quantity MB85R256FPFCN-G-BNDE1 28-pin plastic TSOP Tray *
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PACKAGE DIMENSION 28-pin plastic TSOP Lead pitch 0.55 mm Package width × package length 11.80 × 8.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.20 mm Max 28-pin plastic TSOP 7 8 INDEX 13.40±0.20 11.80±0.20 0.20±0.10 0.55 typ. 8.00±0.20 1.20 max. (Mounting height) 0.10(.004) 0.10 to 0.20 LEAD No. 1 0.00 min. (Stand off) Dimensions in mm.
MARKING(Example) MB85R256F JAPAN
1150 E00
[MB85R256FPFCN-G-BNDE1] [TSOP 28] MB85R256F
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PACKING INFORMATION 1. Tray
1.1 Tray Dimensions
TSOP28 Maximum storage capacity pcs/tray pcs/inner box pcs/outer box 128 1280 5120 (Dimensions in mm) Heat proof temperature : 150 C Max 7.62 9.5 9.5 13.7 15 19 1.27 SEC. A-A 1.27 0.85 8.2 15.8 14.9 SEC. B-B 34.3 25.4 2.54 255.3 0.85 7.62 1.27 25.4 135.9 15.815.8 A 14.9 × 7 = 104.3 AC3 7.62 1.27 15 1519 × 15 = 285 315 322.6 B B R4.75 0.76 8-NO HOLES 1.27
1.2 IC orientation
IC) 7UD\\ &KDPIHUHGFRUQHU
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1.3 Product label indicators(example)
Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm 100mm) Supplemental Label (20mm 100mm)] C-3 Label Supplemental Label Perforated line (Part number) (Part number) (Control number bar code) XX/XX XXXX-XXX XXX XXXX-XXX XXX (Lot Number and quantity) (Package count) (Part number bar code) (Part number and quantity) (Control number bar code) QC PASS XXXXXXXXXXXXXX XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx (3N)1 XXXXXXXXXXXXXX XXX (Quantity) (3N)2 XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX (Part number)XXXXXXXXXXXXXX (Comment)XXXXXXXXXXXXXX (Control number )XXXXXXXXXX (LEAD FREE mark)
1.4 Dimensions for Containers
(1) Dimensions for inner box (2) Dimensions for outer box L W H 165 360 75 (Dimensions in mm) L W H 355 385 195 (Dimensions in mm) L W H L W H
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MAJOR CHANGES IN THIS EDITION A change on a page is indicated by a vertical line drawn on the left side of that page. Page Section Change Results 15 MARKING New making format is added.
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